1 /* 2 * Copyright © 2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: atomic modeset support 26 * 27 * The functions here implement the state management and hardware programming 28 * dispatch required by the atomic modeset infrastructure. 29 * See intel_atomic_plane.c for the plane-specific atomic functionality. 30 */ 31 32 #include <drm/drm_atomic.h> 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_fourcc.h> 35 #include <drm/drm_plane_helper.h> 36 37 #include "intel_atomic.h" 38 #include "intel_cdclk.h" 39 #include "intel_display_types.h" 40 #include "intel_global_state.h" 41 #include "intel_hdcp.h" 42 #include "intel_psr.h" 43 #include "skl_universal_plane.h" 44 45 /** 46 * intel_digital_connector_atomic_get_property - hook for connector->atomic_get_property. 47 * @connector: Connector to get the property for. 48 * @state: Connector state to retrieve the property from. 49 * @property: Property to retrieve. 50 * @val: Return value for the property. 51 * 52 * Returns the atomic property value for a digital connector. 53 */ 54 int intel_digital_connector_atomic_get_property(struct drm_connector *connector, 55 const struct drm_connector_state *state, 56 struct drm_property *property, 57 u64 *val) 58 { 59 struct drm_device *dev = connector->dev; 60 struct drm_i915_private *dev_priv = to_i915(dev); 61 struct intel_digital_connector_state *intel_conn_state = 62 to_intel_digital_connector_state(state); 63 64 if (property == dev_priv->force_audio_property) 65 *val = intel_conn_state->force_audio; 66 else if (property == dev_priv->broadcast_rgb_property) 67 *val = intel_conn_state->broadcast_rgb; 68 else { 69 drm_dbg_atomic(&dev_priv->drm, 70 "Unknown property [PROP:%d:%s]\n", 71 property->base.id, property->name); 72 return -EINVAL; 73 } 74 75 return 0; 76 } 77 78 /** 79 * intel_digital_connector_atomic_set_property - hook for connector->atomic_set_property. 80 * @connector: Connector to set the property for. 81 * @state: Connector state to set the property on. 82 * @property: Property to set. 83 * @val: New value for the property. 84 * 85 * Sets the atomic property value for a digital connector. 86 */ 87 int intel_digital_connector_atomic_set_property(struct drm_connector *connector, 88 struct drm_connector_state *state, 89 struct drm_property *property, 90 u64 val) 91 { 92 struct drm_device *dev = connector->dev; 93 struct drm_i915_private *dev_priv = to_i915(dev); 94 struct intel_digital_connector_state *intel_conn_state = 95 to_intel_digital_connector_state(state); 96 97 if (property == dev_priv->force_audio_property) { 98 intel_conn_state->force_audio = val; 99 return 0; 100 } 101 102 if (property == dev_priv->broadcast_rgb_property) { 103 intel_conn_state->broadcast_rgb = val; 104 return 0; 105 } 106 107 drm_dbg_atomic(&dev_priv->drm, "Unknown property [PROP:%d:%s]\n", 108 property->base.id, property->name); 109 return -EINVAL; 110 } 111 112 int intel_digital_connector_atomic_check(struct drm_connector *conn, 113 struct drm_atomic_state *state) 114 { 115 struct drm_connector_state *new_state = 116 drm_atomic_get_new_connector_state(state, conn); 117 struct intel_digital_connector_state *new_conn_state = 118 to_intel_digital_connector_state(new_state); 119 struct drm_connector_state *old_state = 120 drm_atomic_get_old_connector_state(state, conn); 121 struct intel_digital_connector_state *old_conn_state = 122 to_intel_digital_connector_state(old_state); 123 struct drm_crtc_state *crtc_state; 124 125 intel_hdcp_atomic_check(conn, old_state, new_state); 126 127 if (!new_state->crtc) 128 return 0; 129 130 crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc); 131 132 /* 133 * These properties are handled by fastset, and might not end 134 * up in a modeset. 135 */ 136 if (new_conn_state->force_audio != old_conn_state->force_audio || 137 new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb || 138 new_conn_state->base.colorspace != old_conn_state->base.colorspace || 139 new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio || 140 new_conn_state->base.content_type != old_conn_state->base.content_type || 141 new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode || 142 new_conn_state->base.privacy_screen_sw_state != old_conn_state->base.privacy_screen_sw_state || 143 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) 144 crtc_state->mode_changed = true; 145 146 return 0; 147 } 148 149 /** 150 * intel_digital_connector_duplicate_state - duplicate connector state 151 * @connector: digital connector 152 * 153 * Allocates and returns a copy of the connector state (both common and 154 * digital connector specific) for the specified connector. 155 * 156 * Returns: The newly allocated connector state, or NULL on failure. 157 */ 158 struct drm_connector_state * 159 intel_digital_connector_duplicate_state(struct drm_connector *connector) 160 { 161 struct intel_digital_connector_state *state; 162 163 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL); 164 if (!state) 165 return NULL; 166 167 __drm_atomic_helper_connector_duplicate_state(connector, &state->base); 168 return &state->base; 169 } 170 171 /** 172 * intel_connector_needs_modeset - check if connector needs a modeset 173 * @state: the atomic state corresponding to this modeset 174 * @connector: the connector 175 */ 176 bool 177 intel_connector_needs_modeset(struct intel_atomic_state *state, 178 struct drm_connector *connector) 179 { 180 const struct drm_connector_state *old_conn_state, *new_conn_state; 181 182 old_conn_state = drm_atomic_get_old_connector_state(&state->base, connector); 183 new_conn_state = drm_atomic_get_new_connector_state(&state->base, connector); 184 185 return old_conn_state->crtc != new_conn_state->crtc || 186 (new_conn_state->crtc && 187 drm_atomic_crtc_needs_modeset(drm_atomic_get_new_crtc_state(&state->base, 188 new_conn_state->crtc))); 189 } 190 191 /** 192 * intel_any_crtc_needs_modeset - check if any CRTC needs a modeset 193 * @state: the atomic state corresponding to this modeset 194 * 195 * Returns true if any CRTC in @state needs a modeset. 196 */ 197 bool intel_any_crtc_needs_modeset(struct intel_atomic_state *state) 198 { 199 struct intel_crtc *crtc; 200 struct intel_crtc_state *crtc_state; 201 int i; 202 203 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 204 if (intel_crtc_needs_modeset(crtc_state)) 205 return true; 206 } 207 208 return false; 209 } 210 211 struct intel_digital_connector_state * 212 intel_atomic_get_digital_connector_state(struct intel_atomic_state *state, 213 struct intel_connector *connector) 214 { 215 struct drm_connector_state *conn_state; 216 217 conn_state = drm_atomic_get_connector_state(&state->base, 218 &connector->base); 219 if (IS_ERR(conn_state)) 220 return ERR_CAST(conn_state); 221 222 return to_intel_digital_connector_state(conn_state); 223 } 224 225 /** 226 * intel_crtc_duplicate_state - duplicate crtc state 227 * @crtc: drm crtc 228 * 229 * Allocates and returns a copy of the crtc state (both common and 230 * Intel-specific) for the specified crtc. 231 * 232 * Returns: The newly allocated crtc state, or NULL on failure. 233 */ 234 struct drm_crtc_state * 235 intel_crtc_duplicate_state(struct drm_crtc *crtc) 236 { 237 const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state); 238 struct intel_crtc_state *crtc_state; 239 240 crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL); 241 if (!crtc_state) 242 return NULL; 243 244 __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi); 245 246 /* copy color blobs */ 247 if (crtc_state->hw.degamma_lut) 248 drm_property_blob_get(crtc_state->hw.degamma_lut); 249 if (crtc_state->hw.ctm) 250 drm_property_blob_get(crtc_state->hw.ctm); 251 if (crtc_state->hw.gamma_lut) 252 drm_property_blob_get(crtc_state->hw.gamma_lut); 253 254 crtc_state->update_pipe = false; 255 crtc_state->disable_lp_wm = false; 256 crtc_state->disable_cxsr = false; 257 crtc_state->update_wm_pre = false; 258 crtc_state->update_wm_post = false; 259 crtc_state->fifo_changed = false; 260 crtc_state->preload_luts = false; 261 crtc_state->inherited = false; 262 crtc_state->wm.need_postvbl_update = false; 263 crtc_state->fb_bits = 0; 264 crtc_state->update_planes = 0; 265 crtc_state->dsb = NULL; 266 267 return &crtc_state->uapi; 268 } 269 270 static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state) 271 { 272 drm_property_blob_put(crtc_state->hw.degamma_lut); 273 drm_property_blob_put(crtc_state->hw.gamma_lut); 274 drm_property_blob_put(crtc_state->hw.ctm); 275 } 276 277 void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state) 278 { 279 intel_crtc_put_color_blobs(crtc_state); 280 } 281 282 void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state, 283 const struct intel_crtc_state *from_crtc_state) 284 { 285 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 286 from_crtc_state->uapi.degamma_lut); 287 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 288 from_crtc_state->uapi.gamma_lut); 289 drm_property_replace_blob(&crtc_state->hw.ctm, 290 from_crtc_state->uapi.ctm); 291 } 292 293 /** 294 * intel_crtc_destroy_state - destroy crtc state 295 * @crtc: drm crtc 296 * @state: the state to destroy 297 * 298 * Destroys the crtc state (both common and Intel-specific) for the 299 * specified crtc. 300 */ 301 void 302 intel_crtc_destroy_state(struct drm_crtc *crtc, 303 struct drm_crtc_state *state) 304 { 305 struct intel_crtc_state *crtc_state = to_intel_crtc_state(state); 306 307 drm_WARN_ON(crtc->dev, crtc_state->dsb); 308 309 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 310 intel_crtc_free_hw_state(crtc_state); 311 kfree(crtc_state); 312 } 313 314 static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state, 315 int num_scalers_need, struct intel_crtc *intel_crtc, 316 const char *name, int idx, 317 struct intel_plane_state *plane_state, 318 int *scaler_id) 319 { 320 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); 321 int j; 322 u32 mode; 323 324 if (*scaler_id < 0) { 325 /* find a free scaler */ 326 for (j = 0; j < intel_crtc->num_scalers; j++) { 327 if (scaler_state->scalers[j].in_use) 328 continue; 329 330 *scaler_id = j; 331 scaler_state->scalers[*scaler_id].in_use = 1; 332 break; 333 } 334 } 335 336 if (drm_WARN(&dev_priv->drm, *scaler_id < 0, 337 "Cannot find scaler for %s:%d\n", name, idx)) 338 return; 339 340 /* set scaler mode */ 341 if (plane_state && plane_state->hw.fb && 342 plane_state->hw.fb->format->is_yuv && 343 plane_state->hw.fb->format->num_planes > 1) { 344 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 345 if (DISPLAY_VER(dev_priv) == 9) { 346 mode = SKL_PS_SCALER_MODE_NV12; 347 } else if (icl_is_hdr_plane(dev_priv, plane->id)) { 348 /* 349 * On gen11+'s HDR planes we only use the scaler for 350 * scaling. They have a dedicated chroma upsampler, so 351 * we don't need the scaler to upsample the UV plane. 352 */ 353 mode = PS_SCALER_MODE_NORMAL; 354 } else { 355 struct intel_plane *linked = 356 plane_state->planar_linked_plane; 357 358 mode = PS_SCALER_MODE_PLANAR; 359 360 if (linked) 361 mode |= PS_PLANE_Y_SEL(linked->id); 362 } 363 } else if (DISPLAY_VER(dev_priv) >= 10) { 364 mode = PS_SCALER_MODE_NORMAL; 365 } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) { 366 /* 367 * when only 1 scaler is in use on a pipe with 2 scalers 368 * scaler 0 operates in high quality (HQ) mode. 369 * In this case use scaler 0 to take advantage of HQ mode 370 */ 371 scaler_state->scalers[*scaler_id].in_use = 0; 372 *scaler_id = 0; 373 scaler_state->scalers[0].in_use = 1; 374 mode = SKL_PS_SCALER_MODE_HQ; 375 } else { 376 mode = SKL_PS_SCALER_MODE_DYN; 377 } 378 379 drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n", 380 intel_crtc->pipe, *scaler_id, name, idx); 381 scaler_state->scalers[*scaler_id].mode = mode; 382 } 383 384 /** 385 * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests 386 * @dev_priv: i915 device 387 * @intel_crtc: intel crtc 388 * @crtc_state: incoming crtc_state to validate and setup scalers 389 * 390 * This function sets up scalers based on staged scaling requests for 391 * a @crtc and its planes. It is called from crtc level check path. If request 392 * is a supportable request, it attaches scalers to requested planes and crtc. 393 * 394 * This function takes into account the current scaler(s) in use by any planes 395 * not being part of this atomic state 396 * 397 * Returns: 398 * 0 - scalers were setup succesfully 399 * error code - otherwise 400 */ 401 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, 402 struct intel_crtc *intel_crtc, 403 struct intel_crtc_state *crtc_state) 404 { 405 struct drm_plane *plane = NULL; 406 struct intel_plane *intel_plane; 407 struct intel_plane_state *plane_state = NULL; 408 struct intel_crtc_scaler_state *scaler_state = 409 &crtc_state->scaler_state; 410 struct drm_atomic_state *drm_state = crtc_state->uapi.state; 411 struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state); 412 int num_scalers_need; 413 int i; 414 415 num_scalers_need = hweight32(scaler_state->scaler_users); 416 417 /* 418 * High level flow: 419 * - staged scaler requests are already in scaler_state->scaler_users 420 * - check whether staged scaling requests can be supported 421 * - add planes using scalers that aren't in current transaction 422 * - assign scalers to requested users 423 * - as part of plane commit, scalers will be committed 424 * (i.e., either attached or detached) to respective planes in hw 425 * - as part of crtc_commit, scaler will be either attached or detached 426 * to crtc in hw 427 */ 428 429 /* fail if required scalers > available scalers */ 430 if (num_scalers_need > intel_crtc->num_scalers){ 431 drm_dbg_kms(&dev_priv->drm, 432 "Too many scaling requests %d > %d\n", 433 num_scalers_need, intel_crtc->num_scalers); 434 return -EINVAL; 435 } 436 437 /* walkthrough scaler_users bits and start assigning scalers */ 438 for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) { 439 int *scaler_id; 440 const char *name; 441 int idx; 442 443 /* skip if scaler not required */ 444 if (!(scaler_state->scaler_users & (1 << i))) 445 continue; 446 447 if (i == SKL_CRTC_INDEX) { 448 name = "CRTC"; 449 idx = intel_crtc->base.base.id; 450 451 /* panel fitter case: assign as a crtc scaler */ 452 scaler_id = &scaler_state->scaler_id; 453 } else { 454 name = "PLANE"; 455 456 /* plane scaler case: assign as a plane scaler */ 457 /* find the plane that set the bit as scaler_user */ 458 plane = drm_state->planes[i].ptr; 459 460 /* 461 * to enable/disable hq mode, add planes that are using scaler 462 * into this transaction 463 */ 464 if (!plane) { 465 struct drm_plane_state *state; 466 467 /* 468 * GLK+ scalers don't have a HQ mode so it 469 * isn't necessary to change between HQ and dyn mode 470 * on those platforms. 471 */ 472 if (DISPLAY_VER(dev_priv) >= 10) 473 continue; 474 475 plane = drm_plane_from_index(&dev_priv->drm, i); 476 state = drm_atomic_get_plane_state(drm_state, plane); 477 if (IS_ERR(state)) { 478 drm_dbg_kms(&dev_priv->drm, 479 "Failed to add [PLANE:%d] to drm_state\n", 480 plane->base.id); 481 return PTR_ERR(state); 482 } 483 } 484 485 intel_plane = to_intel_plane(plane); 486 idx = plane->base.id; 487 488 /* plane on different crtc cannot be a scaler user of this crtc */ 489 if (drm_WARN_ON(&dev_priv->drm, 490 intel_plane->pipe != intel_crtc->pipe)) 491 continue; 492 493 plane_state = intel_atomic_get_new_plane_state(intel_state, 494 intel_plane); 495 scaler_id = &plane_state->scaler_id; 496 } 497 498 intel_atomic_setup_scaler(scaler_state, num_scalers_need, 499 intel_crtc, name, idx, 500 plane_state, scaler_id); 501 } 502 503 return 0; 504 } 505 506 struct drm_atomic_state * 507 intel_atomic_state_alloc(struct drm_device *dev) 508 { 509 struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 510 511 if (!state || drm_atomic_state_init(dev, &state->base) < 0) { 512 kfree(state); 513 return NULL; 514 } 515 516 return &state->base; 517 } 518 519 void intel_atomic_state_free(struct drm_atomic_state *_state) 520 { 521 struct intel_atomic_state *state = to_intel_atomic_state(_state); 522 523 drm_atomic_state_default_release(&state->base); 524 kfree(state->global_objs); 525 526 i915_sw_fence_fini(&state->commit_ready); 527 528 kfree(state); 529 } 530 531 void intel_atomic_state_clear(struct drm_atomic_state *s) 532 { 533 struct intel_atomic_state *state = to_intel_atomic_state(s); 534 535 drm_atomic_state_default_clear(&state->base); 536 intel_atomic_clear_global_state(state); 537 538 state->dpll_set = state->modeset = false; 539 } 540 541 struct intel_crtc_state * 542 intel_atomic_get_crtc_state(struct drm_atomic_state *state, 543 struct intel_crtc *crtc) 544 { 545 struct drm_crtc_state *crtc_state; 546 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); 547 if (IS_ERR(crtc_state)) 548 return ERR_CAST(crtc_state); 549 550 return to_intel_crtc_state(crtc_state); 551 } 552