1 /* 2 * Copyright © 2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: atomic modeset support 26 * 27 * The functions here implement the state management and hardware programming 28 * dispatch required by the atomic modeset infrastructure. 29 * See intel_atomic_plane.c for the plane-specific atomic functionality. 30 */ 31 32 #include <drm/drm_atomic.h> 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_fourcc.h> 35 #include <drm/drm_plane_helper.h> 36 37 #include "i915_drv.h" 38 #include "i915_reg.h" 39 #include "intel_atomic.h" 40 #include "intel_cdclk.h" 41 #include "intel_display_types.h" 42 #include "intel_global_state.h" 43 #include "intel_hdcp.h" 44 #include "intel_psr.h" 45 #include "skl_universal_plane.h" 46 47 /** 48 * intel_digital_connector_atomic_get_property - hook for connector->atomic_get_property. 49 * @connector: Connector to get the property for. 50 * @state: Connector state to retrieve the property from. 51 * @property: Property to retrieve. 52 * @val: Return value for the property. 53 * 54 * Returns the atomic property value for a digital connector. 55 */ 56 int intel_digital_connector_atomic_get_property(struct drm_connector *connector, 57 const struct drm_connector_state *state, 58 struct drm_property *property, 59 u64 *val) 60 { 61 struct drm_device *dev = connector->dev; 62 struct drm_i915_private *dev_priv = to_i915(dev); 63 struct intel_digital_connector_state *intel_conn_state = 64 to_intel_digital_connector_state(state); 65 66 if (property == dev_priv->force_audio_property) 67 *val = intel_conn_state->force_audio; 68 else if (property == dev_priv->broadcast_rgb_property) 69 *val = intel_conn_state->broadcast_rgb; 70 else { 71 drm_dbg_atomic(&dev_priv->drm, 72 "Unknown property [PROP:%d:%s]\n", 73 property->base.id, property->name); 74 return -EINVAL; 75 } 76 77 return 0; 78 } 79 80 /** 81 * intel_digital_connector_atomic_set_property - hook for connector->atomic_set_property. 82 * @connector: Connector to set the property for. 83 * @state: Connector state to set the property on. 84 * @property: Property to set. 85 * @val: New value for the property. 86 * 87 * Sets the atomic property value for a digital connector. 88 */ 89 int intel_digital_connector_atomic_set_property(struct drm_connector *connector, 90 struct drm_connector_state *state, 91 struct drm_property *property, 92 u64 val) 93 { 94 struct drm_device *dev = connector->dev; 95 struct drm_i915_private *dev_priv = to_i915(dev); 96 struct intel_digital_connector_state *intel_conn_state = 97 to_intel_digital_connector_state(state); 98 99 if (property == dev_priv->force_audio_property) { 100 intel_conn_state->force_audio = val; 101 return 0; 102 } 103 104 if (property == dev_priv->broadcast_rgb_property) { 105 intel_conn_state->broadcast_rgb = val; 106 return 0; 107 } 108 109 drm_dbg_atomic(&dev_priv->drm, "Unknown property [PROP:%d:%s]\n", 110 property->base.id, property->name); 111 return -EINVAL; 112 } 113 114 int intel_digital_connector_atomic_check(struct drm_connector *conn, 115 struct drm_atomic_state *state) 116 { 117 struct drm_connector_state *new_state = 118 drm_atomic_get_new_connector_state(state, conn); 119 struct intel_digital_connector_state *new_conn_state = 120 to_intel_digital_connector_state(new_state); 121 struct drm_connector_state *old_state = 122 drm_atomic_get_old_connector_state(state, conn); 123 struct intel_digital_connector_state *old_conn_state = 124 to_intel_digital_connector_state(old_state); 125 struct drm_crtc_state *crtc_state; 126 127 intel_hdcp_atomic_check(conn, old_state, new_state); 128 129 if (!new_state->crtc) 130 return 0; 131 132 crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc); 133 134 /* 135 * These properties are handled by fastset, and might not end 136 * up in a modeset. 137 */ 138 if (new_conn_state->force_audio != old_conn_state->force_audio || 139 new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb || 140 new_conn_state->base.colorspace != old_conn_state->base.colorspace || 141 new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio || 142 new_conn_state->base.content_type != old_conn_state->base.content_type || 143 new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode || 144 new_conn_state->base.privacy_screen_sw_state != old_conn_state->base.privacy_screen_sw_state || 145 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) 146 crtc_state->mode_changed = true; 147 148 return 0; 149 } 150 151 /** 152 * intel_digital_connector_duplicate_state - duplicate connector state 153 * @connector: digital connector 154 * 155 * Allocates and returns a copy of the connector state (both common and 156 * digital connector specific) for the specified connector. 157 * 158 * Returns: The newly allocated connector state, or NULL on failure. 159 */ 160 struct drm_connector_state * 161 intel_digital_connector_duplicate_state(struct drm_connector *connector) 162 { 163 struct intel_digital_connector_state *state; 164 165 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL); 166 if (!state) 167 return NULL; 168 169 __drm_atomic_helper_connector_duplicate_state(connector, &state->base); 170 return &state->base; 171 } 172 173 /** 174 * intel_connector_needs_modeset - check if connector needs a modeset 175 * @state: the atomic state corresponding to this modeset 176 * @connector: the connector 177 */ 178 bool 179 intel_connector_needs_modeset(struct intel_atomic_state *state, 180 struct drm_connector *connector) 181 { 182 const struct drm_connector_state *old_conn_state, *new_conn_state; 183 184 old_conn_state = drm_atomic_get_old_connector_state(&state->base, connector); 185 new_conn_state = drm_atomic_get_new_connector_state(&state->base, connector); 186 187 return old_conn_state->crtc != new_conn_state->crtc || 188 (new_conn_state->crtc && 189 drm_atomic_crtc_needs_modeset(drm_atomic_get_new_crtc_state(&state->base, 190 new_conn_state->crtc))); 191 } 192 193 /** 194 * intel_any_crtc_needs_modeset - check if any CRTC needs a modeset 195 * @state: the atomic state corresponding to this modeset 196 * 197 * Returns true if any CRTC in @state needs a modeset. 198 */ 199 bool intel_any_crtc_needs_modeset(struct intel_atomic_state *state) 200 { 201 struct intel_crtc *crtc; 202 struct intel_crtc_state *crtc_state; 203 int i; 204 205 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 206 if (intel_crtc_needs_modeset(crtc_state)) 207 return true; 208 } 209 210 return false; 211 } 212 213 struct intel_digital_connector_state * 214 intel_atomic_get_digital_connector_state(struct intel_atomic_state *state, 215 struct intel_connector *connector) 216 { 217 struct drm_connector_state *conn_state; 218 219 conn_state = drm_atomic_get_connector_state(&state->base, 220 &connector->base); 221 if (IS_ERR(conn_state)) 222 return ERR_CAST(conn_state); 223 224 return to_intel_digital_connector_state(conn_state); 225 } 226 227 /** 228 * intel_crtc_duplicate_state - duplicate crtc state 229 * @crtc: drm crtc 230 * 231 * Allocates and returns a copy of the crtc state (both common and 232 * Intel-specific) for the specified crtc. 233 * 234 * Returns: The newly allocated crtc state, or NULL on failure. 235 */ 236 struct drm_crtc_state * 237 intel_crtc_duplicate_state(struct drm_crtc *crtc) 238 { 239 const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state); 240 struct intel_crtc_state *crtc_state; 241 242 crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL); 243 if (!crtc_state) 244 return NULL; 245 246 __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi); 247 248 /* copy color blobs */ 249 if (crtc_state->hw.degamma_lut) 250 drm_property_blob_get(crtc_state->hw.degamma_lut); 251 if (crtc_state->hw.ctm) 252 drm_property_blob_get(crtc_state->hw.ctm); 253 if (crtc_state->hw.gamma_lut) 254 drm_property_blob_get(crtc_state->hw.gamma_lut); 255 256 crtc_state->update_pipe = false; 257 crtc_state->disable_lp_wm = false; 258 crtc_state->disable_cxsr = false; 259 crtc_state->update_wm_pre = false; 260 crtc_state->update_wm_post = false; 261 crtc_state->fifo_changed = false; 262 crtc_state->preload_luts = false; 263 crtc_state->inherited = false; 264 crtc_state->wm.need_postvbl_update = false; 265 crtc_state->fb_bits = 0; 266 crtc_state->update_planes = 0; 267 crtc_state->dsb = NULL; 268 269 return &crtc_state->uapi; 270 } 271 272 static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state) 273 { 274 drm_property_blob_put(crtc_state->hw.degamma_lut); 275 drm_property_blob_put(crtc_state->hw.gamma_lut); 276 drm_property_blob_put(crtc_state->hw.ctm); 277 } 278 279 void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state) 280 { 281 intel_crtc_put_color_blobs(crtc_state); 282 } 283 284 void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state, 285 const struct intel_crtc_state *from_crtc_state) 286 { 287 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 288 from_crtc_state->uapi.degamma_lut); 289 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 290 from_crtc_state->uapi.gamma_lut); 291 drm_property_replace_blob(&crtc_state->hw.ctm, 292 from_crtc_state->uapi.ctm); 293 } 294 295 /** 296 * intel_crtc_destroy_state - destroy crtc state 297 * @crtc: drm crtc 298 * @state: the state to destroy 299 * 300 * Destroys the crtc state (both common and Intel-specific) for the 301 * specified crtc. 302 */ 303 void 304 intel_crtc_destroy_state(struct drm_crtc *crtc, 305 struct drm_crtc_state *state) 306 { 307 struct intel_crtc_state *crtc_state = to_intel_crtc_state(state); 308 309 drm_WARN_ON(crtc->dev, crtc_state->dsb); 310 311 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 312 intel_crtc_free_hw_state(crtc_state); 313 kfree(crtc_state); 314 } 315 316 static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state, 317 int num_scalers_need, struct intel_crtc *intel_crtc, 318 const char *name, int idx, 319 struct intel_plane_state *plane_state, 320 int *scaler_id) 321 { 322 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); 323 int j; 324 u32 mode; 325 326 if (*scaler_id < 0) { 327 /* find a free scaler */ 328 for (j = 0; j < intel_crtc->num_scalers; j++) { 329 if (scaler_state->scalers[j].in_use) 330 continue; 331 332 *scaler_id = j; 333 scaler_state->scalers[*scaler_id].in_use = 1; 334 break; 335 } 336 } 337 338 if (drm_WARN(&dev_priv->drm, *scaler_id < 0, 339 "Cannot find scaler for %s:%d\n", name, idx)) 340 return; 341 342 /* set scaler mode */ 343 if (plane_state && plane_state->hw.fb && 344 plane_state->hw.fb->format->is_yuv && 345 plane_state->hw.fb->format->num_planes > 1) { 346 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 347 if (DISPLAY_VER(dev_priv) == 9) { 348 mode = SKL_PS_SCALER_MODE_NV12; 349 } else if (icl_is_hdr_plane(dev_priv, plane->id)) { 350 /* 351 * On gen11+'s HDR planes we only use the scaler for 352 * scaling. They have a dedicated chroma upsampler, so 353 * we don't need the scaler to upsample the UV plane. 354 */ 355 mode = PS_SCALER_MODE_NORMAL; 356 } else { 357 struct intel_plane *linked = 358 plane_state->planar_linked_plane; 359 360 mode = PS_SCALER_MODE_PLANAR; 361 362 if (linked) 363 mode |= PS_PLANE_Y_SEL(linked->id); 364 } 365 } else if (DISPLAY_VER(dev_priv) >= 10) { 366 mode = PS_SCALER_MODE_NORMAL; 367 } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) { 368 /* 369 * when only 1 scaler is in use on a pipe with 2 scalers 370 * scaler 0 operates in high quality (HQ) mode. 371 * In this case use scaler 0 to take advantage of HQ mode 372 */ 373 scaler_state->scalers[*scaler_id].in_use = 0; 374 *scaler_id = 0; 375 scaler_state->scalers[0].in_use = 1; 376 mode = SKL_PS_SCALER_MODE_HQ; 377 } else { 378 mode = SKL_PS_SCALER_MODE_DYN; 379 } 380 381 drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n", 382 intel_crtc->pipe, *scaler_id, name, idx); 383 scaler_state->scalers[*scaler_id].mode = mode; 384 } 385 386 /** 387 * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests 388 * @dev_priv: i915 device 389 * @intel_crtc: intel crtc 390 * @crtc_state: incoming crtc_state to validate and setup scalers 391 * 392 * This function sets up scalers based on staged scaling requests for 393 * a @crtc and its planes. It is called from crtc level check path. If request 394 * is a supportable request, it attaches scalers to requested planes and crtc. 395 * 396 * This function takes into account the current scaler(s) in use by any planes 397 * not being part of this atomic state 398 * 399 * Returns: 400 * 0 - scalers were setup succesfully 401 * error code - otherwise 402 */ 403 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, 404 struct intel_crtc *intel_crtc, 405 struct intel_crtc_state *crtc_state) 406 { 407 struct drm_plane *plane = NULL; 408 struct intel_plane *intel_plane; 409 struct intel_plane_state *plane_state = NULL; 410 struct intel_crtc_scaler_state *scaler_state = 411 &crtc_state->scaler_state; 412 struct drm_atomic_state *drm_state = crtc_state->uapi.state; 413 struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state); 414 int num_scalers_need; 415 int i; 416 417 num_scalers_need = hweight32(scaler_state->scaler_users); 418 419 /* 420 * High level flow: 421 * - staged scaler requests are already in scaler_state->scaler_users 422 * - check whether staged scaling requests can be supported 423 * - add planes using scalers that aren't in current transaction 424 * - assign scalers to requested users 425 * - as part of plane commit, scalers will be committed 426 * (i.e., either attached or detached) to respective planes in hw 427 * - as part of crtc_commit, scaler will be either attached or detached 428 * to crtc in hw 429 */ 430 431 /* fail if required scalers > available scalers */ 432 if (num_scalers_need > intel_crtc->num_scalers){ 433 drm_dbg_kms(&dev_priv->drm, 434 "Too many scaling requests %d > %d\n", 435 num_scalers_need, intel_crtc->num_scalers); 436 return -EINVAL; 437 } 438 439 /* walkthrough scaler_users bits and start assigning scalers */ 440 for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) { 441 int *scaler_id; 442 const char *name; 443 int idx; 444 445 /* skip if scaler not required */ 446 if (!(scaler_state->scaler_users & (1 << i))) 447 continue; 448 449 if (i == SKL_CRTC_INDEX) { 450 name = "CRTC"; 451 idx = intel_crtc->base.base.id; 452 453 /* panel fitter case: assign as a crtc scaler */ 454 scaler_id = &scaler_state->scaler_id; 455 } else { 456 name = "PLANE"; 457 458 /* plane scaler case: assign as a plane scaler */ 459 /* find the plane that set the bit as scaler_user */ 460 plane = drm_state->planes[i].ptr; 461 462 /* 463 * to enable/disable hq mode, add planes that are using scaler 464 * into this transaction 465 */ 466 if (!plane) { 467 struct drm_plane_state *state; 468 469 /* 470 * GLK+ scalers don't have a HQ mode so it 471 * isn't necessary to change between HQ and dyn mode 472 * on those platforms. 473 */ 474 if (DISPLAY_VER(dev_priv) >= 10) 475 continue; 476 477 plane = drm_plane_from_index(&dev_priv->drm, i); 478 state = drm_atomic_get_plane_state(drm_state, plane); 479 if (IS_ERR(state)) { 480 drm_dbg_kms(&dev_priv->drm, 481 "Failed to add [PLANE:%d] to drm_state\n", 482 plane->base.id); 483 return PTR_ERR(state); 484 } 485 } 486 487 intel_plane = to_intel_plane(plane); 488 idx = plane->base.id; 489 490 /* plane on different crtc cannot be a scaler user of this crtc */ 491 if (drm_WARN_ON(&dev_priv->drm, 492 intel_plane->pipe != intel_crtc->pipe)) 493 continue; 494 495 plane_state = intel_atomic_get_new_plane_state(intel_state, 496 intel_plane); 497 scaler_id = &plane_state->scaler_id; 498 } 499 500 intel_atomic_setup_scaler(scaler_state, num_scalers_need, 501 intel_crtc, name, idx, 502 plane_state, scaler_id); 503 } 504 505 return 0; 506 } 507 508 struct drm_atomic_state * 509 intel_atomic_state_alloc(struct drm_device *dev) 510 { 511 struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 512 513 if (!state || drm_atomic_state_init(dev, &state->base) < 0) { 514 kfree(state); 515 return NULL; 516 } 517 518 return &state->base; 519 } 520 521 void intel_atomic_state_free(struct drm_atomic_state *_state) 522 { 523 struct intel_atomic_state *state = to_intel_atomic_state(_state); 524 525 drm_atomic_state_default_release(&state->base); 526 kfree(state->global_objs); 527 528 i915_sw_fence_fini(&state->commit_ready); 529 530 kfree(state); 531 } 532 533 void intel_atomic_state_clear(struct drm_atomic_state *s) 534 { 535 struct intel_atomic_state *state = to_intel_atomic_state(s); 536 537 drm_atomic_state_default_clear(&state->base); 538 intel_atomic_clear_global_state(state); 539 540 state->dpll_set = state->modeset = false; 541 } 542 543 struct intel_crtc_state * 544 intel_atomic_get_crtc_state(struct drm_atomic_state *state, 545 struct intel_crtc *crtc) 546 { 547 struct drm_crtc_state *crtc_state; 548 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); 549 if (IS_ERR(crtc_state)) 550 return ERR_CAST(crtc_state); 551 552 return to_intel_crtc_state(crtc_state); 553 } 554