1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_mipi_dsi.h> 30 31 #include "intel_atomic.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_crtc.h" 35 #include "intel_ddi.h" 36 #include "intel_de.h" 37 #include "intel_dsi.h" 38 #include "intel_panel.h" 39 #include "intel_vdsc.h" 40 #include "skl_scaler.h" 41 #include "skl_universal_plane.h" 42 43 static int header_credits_available(struct drm_i915_private *dev_priv, 44 enum transcoder dsi_trans) 45 { 46 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 47 >> FREE_HEADER_CREDIT_SHIFT; 48 } 49 50 static int payload_credits_available(struct drm_i915_private *dev_priv, 51 enum transcoder dsi_trans) 52 { 53 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 54 >> FREE_PLOAD_CREDIT_SHIFT; 55 } 56 57 static void wait_for_header_credits(struct drm_i915_private *dev_priv, 58 enum transcoder dsi_trans) 59 { 60 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= 61 MAX_HEADER_CREDIT, 100)) 62 drm_err(&dev_priv->drm, "DSI header credits not released\n"); 63 } 64 65 static void wait_for_payload_credits(struct drm_i915_private *dev_priv, 66 enum transcoder dsi_trans) 67 { 68 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= 69 MAX_PLOAD_CREDIT, 100)) 70 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); 71 } 72 73 static enum transcoder dsi_port_to_transcoder(enum port port) 74 { 75 if (port == PORT_A) 76 return TRANSCODER_DSI_0; 77 else 78 return TRANSCODER_DSI_1; 79 } 80 81 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 82 { 83 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 84 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 85 struct mipi_dsi_device *dsi; 86 enum port port; 87 enum transcoder dsi_trans; 88 int ret; 89 90 /* wait for header/payload credits to be released */ 91 for_each_dsi_port(port, intel_dsi->ports) { 92 dsi_trans = dsi_port_to_transcoder(port); 93 wait_for_header_credits(dev_priv, dsi_trans); 94 wait_for_payload_credits(dev_priv, dsi_trans); 95 } 96 97 /* send nop DCS command */ 98 for_each_dsi_port(port, intel_dsi->ports) { 99 dsi = intel_dsi->dsi_hosts[port]->device; 100 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 101 dsi->channel = 0; 102 ret = mipi_dsi_dcs_nop(dsi); 103 if (ret < 0) 104 drm_err(&dev_priv->drm, 105 "error sending DCS NOP command\n"); 106 } 107 108 /* wait for header credits to be released */ 109 for_each_dsi_port(port, intel_dsi->ports) { 110 dsi_trans = dsi_port_to_transcoder(port); 111 wait_for_header_credits(dev_priv, dsi_trans); 112 } 113 114 /* wait for LP TX in progress bit to be cleared */ 115 for_each_dsi_port(port, intel_dsi->ports) { 116 dsi_trans = dsi_port_to_transcoder(port); 117 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 118 LPTX_IN_PROGRESS), 20)) 119 drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); 120 } 121 } 122 123 static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data, 124 u32 len) 125 { 126 struct intel_dsi *intel_dsi = host->intel_dsi; 127 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 128 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 129 int free_credits; 130 int i, j; 131 132 for (i = 0; i < len; i += 4) { 133 u32 tmp = 0; 134 135 free_credits = payload_credits_available(dev_priv, dsi_trans); 136 if (free_credits < 1) { 137 drm_err(&dev_priv->drm, 138 "Payload credit not available\n"); 139 return false; 140 } 141 142 for (j = 0; j < min_t(u32, len - i, 4); j++) 143 tmp |= *data++ << 8 * j; 144 145 intel_de_write(dev_priv, DSI_CMD_TXPYLD(dsi_trans), tmp); 146 } 147 148 return true; 149 } 150 151 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 152 struct mipi_dsi_packet pkt, bool enable_lpdt) 153 { 154 struct intel_dsi *intel_dsi = host->intel_dsi; 155 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 156 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 157 u32 tmp; 158 int free_credits; 159 160 /* check if header credit available */ 161 free_credits = header_credits_available(dev_priv, dsi_trans); 162 if (free_credits < 1) { 163 drm_err(&dev_priv->drm, 164 "send pkt header failed, not enough hdr credits\n"); 165 return -1; 166 } 167 168 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); 169 170 if (pkt.payload) 171 tmp |= PAYLOAD_PRESENT; 172 else 173 tmp &= ~PAYLOAD_PRESENT; 174 175 tmp &= ~VBLANK_FENCE; 176 177 if (enable_lpdt) 178 tmp |= LP_DATA_TRANSFER; 179 180 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 181 tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT); 182 tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT); 183 tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT); 184 tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT); 185 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); 186 187 return 0; 188 } 189 190 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 191 struct mipi_dsi_packet pkt) 192 { 193 struct intel_dsi *intel_dsi = host->intel_dsi; 194 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 195 196 /* payload queue can accept *256 bytes*, check limit */ 197 if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) { 198 drm_err(&i915->drm, "payload size exceeds max queue limit\n"); 199 return -1; 200 } 201 202 /* load data into command payload queue */ 203 if (!add_payld_to_queue(host, pkt.payload, 204 pkt.payload_length)) { 205 drm_err(&i915->drm, "adding payload to queue failed\n"); 206 return -1; 207 } 208 209 return 0; 210 } 211 212 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 213 { 214 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 215 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 216 u32 tmp, mode_flags; 217 enum port port; 218 219 mode_flags = crtc_state->mode_flags; 220 221 /* 222 * case 1 also covers dual link 223 * In case of dual link, frame update should be set on 224 * DSI_0 225 */ 226 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 227 port = PORT_A; 228 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 229 port = PORT_B; 230 else 231 return; 232 233 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 234 tmp |= DSI_FRAME_UPDATE_REQUEST; 235 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 236 } 237 238 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 239 { 240 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 241 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 242 enum phy phy; 243 u32 tmp; 244 int lane; 245 246 for_each_dsi_phy(phy, intel_dsi->phys) { 247 /* 248 * Program voltage swing and pre-emphasis level values as per 249 * table in BSPEC under DDI buffer programing 250 */ 251 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 252 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 253 tmp |= SCALING_MODE_SEL(0x2); 254 tmp |= TAP2_DISABLE | TAP3_DISABLE; 255 tmp |= RTERM_SELECT(0x6); 256 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 257 258 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 259 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 260 tmp |= SCALING_MODE_SEL(0x2); 261 tmp |= TAP2_DISABLE | TAP3_DISABLE; 262 tmp |= RTERM_SELECT(0x6); 263 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 264 265 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 266 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 267 RCOMP_SCALAR_MASK); 268 tmp |= SWING_SEL_UPPER(0x2); 269 tmp |= SWING_SEL_LOWER(0x2); 270 tmp |= RCOMP_SCALAR(0x98); 271 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 272 273 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 274 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 275 RCOMP_SCALAR_MASK); 276 tmp |= SWING_SEL_UPPER(0x2); 277 tmp |= SWING_SEL_LOWER(0x2); 278 tmp |= RCOMP_SCALAR(0x98); 279 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 280 281 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 282 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 283 CURSOR_COEFF_MASK); 284 tmp |= POST_CURSOR_1(0x0); 285 tmp |= POST_CURSOR_2(0x0); 286 tmp |= CURSOR_COEFF(0x3f); 287 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 288 289 for (lane = 0; lane <= 3; lane++) { 290 /* Bspec: must not use GRP register for write */ 291 tmp = intel_de_read(dev_priv, 292 ICL_PORT_TX_DW4_LN(lane, phy)); 293 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 294 CURSOR_COEFF_MASK); 295 tmp |= POST_CURSOR_1(0x0); 296 tmp |= POST_CURSOR_2(0x0); 297 tmp |= CURSOR_COEFF(0x3f); 298 intel_de_write(dev_priv, 299 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 300 } 301 } 302 } 303 304 static void configure_dual_link_mode(struct intel_encoder *encoder, 305 const struct intel_crtc_state *pipe_config) 306 { 307 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 308 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 309 u32 dss_ctl1; 310 311 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); 312 dss_ctl1 |= SPLITTER_ENABLE; 313 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 314 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 315 316 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 317 const struct drm_display_mode *adjusted_mode = 318 &pipe_config->hw.adjusted_mode; 319 u32 dss_ctl2; 320 u16 hactive = adjusted_mode->crtc_hdisplay; 321 u16 dl_buffer_depth; 322 323 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 324 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 325 326 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 327 drm_err(&dev_priv->drm, 328 "DL buffer depth exceed max value\n"); 329 330 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 331 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 332 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); 333 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; 334 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 335 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); 336 } else { 337 /* Interleave */ 338 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 339 } 340 341 intel_de_write(dev_priv, DSS_CTL1, dss_ctl1); 342 } 343 344 /* aka DSI 8X clock */ 345 static int afe_clk(struct intel_encoder *encoder, 346 const struct intel_crtc_state *crtc_state) 347 { 348 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 349 int bpp; 350 351 if (crtc_state->dsc.compression_enable) 352 bpp = crtc_state->dsc.compressed_bpp; 353 else 354 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 355 356 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 357 } 358 359 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 360 const struct intel_crtc_state *crtc_state) 361 { 362 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 363 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 364 enum port port; 365 int afe_clk_khz; 366 u32 esc_clk_div_m; 367 368 afe_clk_khz = afe_clk(encoder, crtc_state); 369 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 370 371 for_each_dsi_port(port, intel_dsi->ports) { 372 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), 373 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 374 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); 375 } 376 377 for_each_dsi_port(port, intel_dsi->ports) { 378 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port), 379 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 380 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); 381 } 382 } 383 384 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, 385 struct intel_dsi *intel_dsi) 386 { 387 enum port port; 388 389 for_each_dsi_port(port, intel_dsi->ports) { 390 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); 391 intel_dsi->io_wakeref[port] = 392 intel_display_power_get(dev_priv, 393 port == PORT_A ? 394 POWER_DOMAIN_PORT_DDI_A_IO : 395 POWER_DOMAIN_PORT_DDI_B_IO); 396 } 397 } 398 399 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 400 { 401 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 402 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 403 enum port port; 404 u32 tmp; 405 406 for_each_dsi_port(port, intel_dsi->ports) { 407 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 408 tmp |= COMBO_PHY_MODE_DSI; 409 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 410 } 411 412 get_dsi_io_power_domains(dev_priv, intel_dsi); 413 } 414 415 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 416 { 417 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 418 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 419 enum phy phy; 420 421 for_each_dsi_phy(phy, intel_dsi->phys) 422 intel_combo_phy_power_up_lanes(dev_priv, phy, true, 423 intel_dsi->lane_count, false); 424 } 425 426 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 427 { 428 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 429 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 430 enum phy phy; 431 u32 tmp; 432 int lane; 433 434 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 435 for_each_dsi_phy(phy, intel_dsi->phys) { 436 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 437 tmp &= ~LOADGEN_SELECT; 438 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 439 for (lane = 0; lane <= 3; lane++) { 440 tmp = intel_de_read(dev_priv, 441 ICL_PORT_TX_DW4_LN(lane, phy)); 442 tmp &= ~LOADGEN_SELECT; 443 if (lane != 2) 444 tmp |= LOADGEN_SELECT; 445 intel_de_write(dev_priv, 446 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 447 } 448 } 449 450 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 451 for_each_dsi_phy(phy, intel_dsi->phys) { 452 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 453 tmp &= ~FRC_LATENCY_OPTIM_MASK; 454 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 455 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 456 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 457 tmp &= ~FRC_LATENCY_OPTIM_MASK; 458 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 459 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 460 461 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 462 if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) { 463 tmp = intel_de_read(dev_priv, 464 ICL_PORT_PCS_DW1_AUX(phy)); 465 tmp &= ~LATENCY_OPTIM_MASK; 466 tmp |= LATENCY_OPTIM_VAL(0); 467 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), 468 tmp); 469 470 tmp = intel_de_read(dev_priv, 471 ICL_PORT_PCS_DW1_LN0(phy)); 472 tmp &= ~LATENCY_OPTIM_MASK; 473 tmp |= LATENCY_OPTIM_VAL(0x1); 474 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), 475 tmp); 476 } 477 } 478 479 } 480 481 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 482 { 483 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 484 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 485 u32 tmp; 486 enum phy phy; 487 488 /* clear common keeper enable bit */ 489 for_each_dsi_phy(phy, intel_dsi->phys) { 490 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 491 tmp &= ~COMMON_KEEPER_EN; 492 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp); 493 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy)); 494 tmp &= ~COMMON_KEEPER_EN; 495 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp); 496 } 497 498 /* 499 * Set SUS Clock Config bitfield to 11b 500 * Note: loadgen select program is done 501 * as part of lane phy sequence configuration 502 */ 503 for_each_dsi_phy(phy, intel_dsi->phys) { 504 tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 505 tmp |= SUS_CLOCK_CONFIG; 506 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp); 507 } 508 509 /* Clear training enable to change swing values */ 510 for_each_dsi_phy(phy, intel_dsi->phys) { 511 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 512 tmp &= ~TX_TRAINING_EN; 513 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 514 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 515 tmp &= ~TX_TRAINING_EN; 516 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 517 } 518 519 /* Program swing and de-emphasis */ 520 dsi_program_swing_and_deemphasis(encoder); 521 522 /* Set training enable to trigger update */ 523 for_each_dsi_phy(phy, intel_dsi->phys) { 524 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 525 tmp |= TX_TRAINING_EN; 526 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 527 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 528 tmp |= TX_TRAINING_EN; 529 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 530 } 531 } 532 533 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 534 { 535 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 536 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 537 u32 tmp; 538 enum port port; 539 540 for_each_dsi_port(port, intel_dsi->ports) { 541 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 542 tmp |= DDI_BUF_CTL_ENABLE; 543 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 544 545 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 546 DDI_BUF_IS_IDLE), 547 500)) 548 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", 549 port_name(port)); 550 } 551 } 552 553 static void 554 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 555 const struct intel_crtc_state *crtc_state) 556 { 557 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 558 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 559 u32 tmp; 560 enum port port; 561 enum phy phy; 562 563 /* Program T-INIT master registers */ 564 for_each_dsi_port(port, intel_dsi->ports) { 565 tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port)); 566 tmp &= ~MASTER_INIT_TIMER_MASK; 567 tmp |= intel_dsi->init_count; 568 intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp); 569 } 570 571 /* Program DPHY clock lanes timings */ 572 for_each_dsi_port(port, intel_dsi->ports) { 573 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port), 574 intel_dsi->dphy_reg); 575 576 /* shadow register inside display core */ 577 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port), 578 intel_dsi->dphy_reg); 579 } 580 581 /* Program DPHY data lanes timings */ 582 for_each_dsi_port(port, intel_dsi->ports) { 583 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port), 584 intel_dsi->dphy_data_lane_reg); 585 586 /* shadow register inside display core */ 587 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port), 588 intel_dsi->dphy_data_lane_reg); 589 } 590 591 /* 592 * If DSI link operating at or below an 800 MHz, 593 * TA_SURE should be override and programmed to 594 * a value '0' inside TA_PARAM_REGISTERS otherwise 595 * leave all fields at HW default values. 596 */ 597 if (DISPLAY_VER(dev_priv) == 11) { 598 if (afe_clk(encoder, crtc_state) <= 800000) { 599 for_each_dsi_port(port, intel_dsi->ports) { 600 tmp = intel_de_read(dev_priv, 601 DPHY_TA_TIMING_PARAM(port)); 602 tmp &= ~TA_SURE_MASK; 603 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 604 intel_de_write(dev_priv, 605 DPHY_TA_TIMING_PARAM(port), 606 tmp); 607 608 /* shadow register inside display core */ 609 tmp = intel_de_read(dev_priv, 610 DSI_TA_TIMING_PARAM(port)); 611 tmp &= ~TA_SURE_MASK; 612 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 613 intel_de_write(dev_priv, 614 DSI_TA_TIMING_PARAM(port), tmp); 615 } 616 } 617 } 618 619 if (IS_JSL_EHL(dev_priv)) { 620 for_each_dsi_phy(phy, intel_dsi->phys) { 621 tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy)); 622 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; 623 intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp); 624 } 625 } 626 } 627 628 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 629 { 630 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 631 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 632 u32 tmp; 633 enum phy phy; 634 635 mutex_lock(&dev_priv->dpll.lock); 636 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 637 for_each_dsi_phy(phy, intel_dsi->phys) 638 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 639 640 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 641 mutex_unlock(&dev_priv->dpll.lock); 642 } 643 644 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 645 { 646 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 647 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 648 u32 tmp; 649 enum phy phy; 650 651 mutex_lock(&dev_priv->dpll.lock); 652 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 653 for_each_dsi_phy(phy, intel_dsi->phys) 654 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 655 656 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 657 mutex_unlock(&dev_priv->dpll.lock); 658 } 659 660 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 661 { 662 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 663 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 664 bool clock_enabled = false; 665 enum phy phy; 666 u32 tmp; 667 668 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 669 670 for_each_dsi_phy(phy, intel_dsi->phys) { 671 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 672 clock_enabled = true; 673 } 674 675 return clock_enabled; 676 } 677 678 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 679 const struct intel_crtc_state *crtc_state) 680 { 681 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 682 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 683 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 684 enum phy phy; 685 u32 val; 686 687 mutex_lock(&dev_priv->dpll.lock); 688 689 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 690 for_each_dsi_phy(phy, intel_dsi->phys) { 691 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 692 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 693 } 694 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 695 696 for_each_dsi_phy(phy, intel_dsi->phys) { 697 if (DISPLAY_VER(dev_priv) >= 12) 698 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 699 else 700 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 701 } 702 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 703 704 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 705 706 mutex_unlock(&dev_priv->dpll.lock); 707 } 708 709 static void 710 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 711 const struct intel_crtc_state *pipe_config) 712 { 713 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 714 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 715 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 716 enum pipe pipe = intel_crtc->pipe; 717 u32 tmp; 718 enum port port; 719 enum transcoder dsi_trans; 720 721 for_each_dsi_port(port, intel_dsi->ports) { 722 dsi_trans = dsi_port_to_transcoder(port); 723 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 724 725 if (intel_dsi->eotp_pkt) 726 tmp &= ~EOTP_DISABLED; 727 else 728 tmp |= EOTP_DISABLED; 729 730 /* enable link calibration if freq > 1.5Gbps */ 731 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 732 tmp &= ~LINK_CALIBRATION_MASK; 733 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 734 } 735 736 /* configure continuous clock */ 737 tmp &= ~CONTINUOUS_CLK_MASK; 738 if (intel_dsi->clock_stop) 739 tmp |= CLK_ENTER_LP_AFTER_DATA; 740 else 741 tmp |= CLK_HS_CONTINUOUS; 742 743 /* configure buffer threshold limit to minimum */ 744 tmp &= ~PIX_BUF_THRESHOLD_MASK; 745 tmp |= PIX_BUF_THRESHOLD_1_4; 746 747 /* set virtual channel to '0' */ 748 tmp &= ~PIX_VIRT_CHAN_MASK; 749 tmp |= PIX_VIRT_CHAN(0); 750 751 /* program BGR transmission */ 752 if (intel_dsi->bgr_enabled) 753 tmp |= BGR_TRANSMISSION; 754 755 /* select pixel format */ 756 tmp &= ~PIX_FMT_MASK; 757 if (pipe_config->dsc.compression_enable) { 758 tmp |= PIX_FMT_COMPRESSED; 759 } else { 760 switch (intel_dsi->pixel_format) { 761 default: 762 MISSING_CASE(intel_dsi->pixel_format); 763 fallthrough; 764 case MIPI_DSI_FMT_RGB565: 765 tmp |= PIX_FMT_RGB565; 766 break; 767 case MIPI_DSI_FMT_RGB666_PACKED: 768 tmp |= PIX_FMT_RGB666_PACKED; 769 break; 770 case MIPI_DSI_FMT_RGB666: 771 tmp |= PIX_FMT_RGB666_LOOSE; 772 break; 773 case MIPI_DSI_FMT_RGB888: 774 tmp |= PIX_FMT_RGB888; 775 break; 776 } 777 } 778 779 if (DISPLAY_VER(dev_priv) >= 12) { 780 if (is_vid_mode(intel_dsi)) 781 tmp |= BLANKING_PACKET_ENABLE; 782 } 783 784 /* program DSI operation mode */ 785 if (is_vid_mode(intel_dsi)) { 786 tmp &= ~OP_MODE_MASK; 787 switch (intel_dsi->video_mode_format) { 788 default: 789 MISSING_CASE(intel_dsi->video_mode_format); 790 fallthrough; 791 case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS: 792 tmp |= VIDEO_MODE_SYNC_EVENT; 793 break; 794 case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE: 795 tmp |= VIDEO_MODE_SYNC_PULSE; 796 break; 797 } 798 } else { 799 /* 800 * FIXME: Retrieve this info from VBT. 801 * As per the spec when dsi transcoder is operating 802 * in TE GATE mode, TE comes from GPIO 803 * which is UTIL PIN for DSI 0. 804 * Also this GPIO would not be used for other 805 * purposes is an assumption. 806 */ 807 tmp &= ~OP_MODE_MASK; 808 tmp |= CMD_MODE_TE_GATE; 809 tmp |= TE_SOURCE_GPIO; 810 } 811 812 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 813 } 814 815 /* enable port sync mode if dual link */ 816 if (intel_dsi->dual_link) { 817 for_each_dsi_port(port, intel_dsi->ports) { 818 dsi_trans = dsi_port_to_transcoder(port); 819 tmp = intel_de_read(dev_priv, 820 TRANS_DDI_FUNC_CTL2(dsi_trans)); 821 tmp |= PORT_SYNC_MODE_ENABLE; 822 intel_de_write(dev_priv, 823 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 824 } 825 826 /* configure stream splitting */ 827 configure_dual_link_mode(encoder, pipe_config); 828 } 829 830 for_each_dsi_port(port, intel_dsi->ports) { 831 dsi_trans = dsi_port_to_transcoder(port); 832 833 /* select data lane width */ 834 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 835 tmp &= ~DDI_PORT_WIDTH_MASK; 836 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); 837 838 /* select input pipe */ 839 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 840 switch (pipe) { 841 default: 842 MISSING_CASE(pipe); 843 fallthrough; 844 case PIPE_A: 845 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 846 break; 847 case PIPE_B: 848 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 849 break; 850 case PIPE_C: 851 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 852 break; 853 case PIPE_D: 854 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 855 break; 856 } 857 858 /* enable DDI buffer */ 859 tmp |= TRANS_DDI_FUNC_ENABLE; 860 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 861 } 862 863 /* wait for link ready */ 864 for_each_dsi_port(port, intel_dsi->ports) { 865 dsi_trans = dsi_port_to_transcoder(port); 866 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) & 867 LINK_READY), 2500)) 868 drm_err(&dev_priv->drm, "DSI link not ready\n"); 869 } 870 } 871 872 static void 873 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 874 const struct intel_crtc_state *crtc_state) 875 { 876 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 877 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 878 const struct drm_display_mode *adjusted_mode = 879 &crtc_state->hw.adjusted_mode; 880 enum port port; 881 enum transcoder dsi_trans; 882 /* horizontal timings */ 883 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 884 u16 hback_porch; 885 /* vertical timings */ 886 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 887 int mul = 1, div = 1; 888 889 /* 890 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 891 * for slower link speed if DSC is enabled. 892 * 893 * The compression frequency ratio is the ratio between compressed and 894 * non-compressed link speeds, and simplifies down to the ratio between 895 * compressed and non-compressed bpp. 896 */ 897 if (crtc_state->dsc.compression_enable) { 898 mul = crtc_state->dsc.compressed_bpp; 899 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 900 } 901 902 hactive = adjusted_mode->crtc_hdisplay; 903 904 if (is_vid_mode(intel_dsi)) 905 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 906 else 907 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 908 909 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 910 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 911 hsync_size = hsync_end - hsync_start; 912 hback_porch = (adjusted_mode->crtc_htotal - 913 adjusted_mode->crtc_hsync_end); 914 vactive = adjusted_mode->crtc_vdisplay; 915 916 if (is_vid_mode(intel_dsi)) { 917 vtotal = adjusted_mode->crtc_vtotal; 918 } else { 919 int bpp, line_time_us, byte_clk_period_ns; 920 921 if (crtc_state->dsc.compression_enable) 922 bpp = crtc_state->dsc.compressed_bpp; 923 else 924 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 925 926 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 927 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 928 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 929 } 930 vsync_start = adjusted_mode->crtc_vsync_start; 931 vsync_end = adjusted_mode->crtc_vsync_end; 932 vsync_shift = hsync_start - htotal / 2; 933 934 if (intel_dsi->dual_link) { 935 hactive /= 2; 936 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 937 hactive += intel_dsi->pixel_overlap; 938 htotal /= 2; 939 } 940 941 /* minimum hactive as per bspec: 256 pixels */ 942 if (adjusted_mode->crtc_hdisplay < 256) 943 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); 944 945 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 946 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 947 drm_err(&dev_priv->drm, 948 "hactive pixels are not multiple of 4\n"); 949 950 /* program TRANS_HTOTAL register */ 951 for_each_dsi_port(port, intel_dsi->ports) { 952 dsi_trans = dsi_port_to_transcoder(port); 953 intel_de_write(dev_priv, HTOTAL(dsi_trans), 954 (hactive - 1) | ((htotal - 1) << 16)); 955 } 956 957 /* TRANS_HSYNC register to be programmed only for video mode */ 958 if (is_vid_mode(intel_dsi)) { 959 if (intel_dsi->video_mode_format == 960 VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) { 961 /* BSPEC: hsync size should be atleast 16 pixels */ 962 if (hsync_size < 16) 963 drm_err(&dev_priv->drm, 964 "hsync size < 16 pixels\n"); 965 } 966 967 if (hback_porch < 16) 968 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); 969 970 if (intel_dsi->dual_link) { 971 hsync_start /= 2; 972 hsync_end /= 2; 973 } 974 975 for_each_dsi_port(port, intel_dsi->ports) { 976 dsi_trans = dsi_port_to_transcoder(port); 977 intel_de_write(dev_priv, HSYNC(dsi_trans), 978 (hsync_start - 1) | ((hsync_end - 1) << 16)); 979 } 980 } 981 982 /* program TRANS_VTOTAL register */ 983 for_each_dsi_port(port, intel_dsi->ports) { 984 dsi_trans = dsi_port_to_transcoder(port); 985 /* 986 * FIXME: Programing this by assuming progressive mode, since 987 * non-interlaced info from VBT is not saved inside 988 * struct drm_display_mode. 989 * For interlace mode: program required pixel minus 2 990 */ 991 intel_de_write(dev_priv, VTOTAL(dsi_trans), 992 (vactive - 1) | ((vtotal - 1) << 16)); 993 } 994 995 if (vsync_end < vsync_start || vsync_end > vtotal) 996 drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); 997 998 if (vsync_start < vactive) 999 drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); 1000 1001 /* program TRANS_VSYNC register for video mode only */ 1002 if (is_vid_mode(intel_dsi)) { 1003 for_each_dsi_port(port, intel_dsi->ports) { 1004 dsi_trans = dsi_port_to_transcoder(port); 1005 intel_de_write(dev_priv, VSYNC(dsi_trans), 1006 (vsync_start - 1) | ((vsync_end - 1) << 16)); 1007 } 1008 } 1009 1010 /* 1011 * FIXME: It has to be programmed only for video modes and interlaced 1012 * modes. Put the check condition here once interlaced 1013 * info available as described above. 1014 * program TRANS_VSYNCSHIFT register 1015 */ 1016 if (is_vid_mode(intel_dsi)) { 1017 for_each_dsi_port(port, intel_dsi->ports) { 1018 dsi_trans = dsi_port_to_transcoder(port); 1019 intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans), 1020 vsync_shift); 1021 } 1022 } 1023 1024 /* program TRANS_VBLANK register, should be same as vtotal programmed */ 1025 if (DISPLAY_VER(dev_priv) >= 12) { 1026 for_each_dsi_port(port, intel_dsi->ports) { 1027 dsi_trans = dsi_port_to_transcoder(port); 1028 intel_de_write(dev_priv, VBLANK(dsi_trans), 1029 (vactive - 1) | ((vtotal - 1) << 16)); 1030 } 1031 } 1032 } 1033 1034 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1035 { 1036 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1037 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1038 enum port port; 1039 enum transcoder dsi_trans; 1040 u32 tmp; 1041 1042 for_each_dsi_port(port, intel_dsi->ports) { 1043 dsi_trans = dsi_port_to_transcoder(port); 1044 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1045 tmp |= PIPECONF_ENABLE; 1046 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1047 1048 /* wait for transcoder to be enabled */ 1049 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), 1050 I965_PIPECONF_ACTIVE, 10)) 1051 drm_err(&dev_priv->drm, 1052 "DSI transcoder not enabled\n"); 1053 } 1054 } 1055 1056 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1057 const struct intel_crtc_state *crtc_state) 1058 { 1059 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1060 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1061 enum port port; 1062 enum transcoder dsi_trans; 1063 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1064 1065 /* 1066 * escape clock count calculation: 1067 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1068 * UI (nsec) = (10^6)/Bitrate 1069 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1070 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1071 */ 1072 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1073 mul = 8 * 1000000; 1074 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1075 divisor); 1076 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1077 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1078 1079 for_each_dsi_port(port, intel_dsi->ports) { 1080 dsi_trans = dsi_port_to_transcoder(port); 1081 1082 /* program hst_tx_timeout */ 1083 tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans)); 1084 tmp &= ~HSTX_TIMEOUT_VALUE_MASK; 1085 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout); 1086 intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp); 1087 1088 /* FIXME: DSI_CALIB_TO */ 1089 1090 /* program lp_rx_host timeout */ 1091 tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans)); 1092 tmp &= ~LPRX_TIMEOUT_VALUE_MASK; 1093 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout); 1094 intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp); 1095 1096 /* FIXME: DSI_PWAIT_TO */ 1097 1098 /* program turn around timeout */ 1099 tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans)); 1100 tmp &= ~TA_TIMEOUT_VALUE_MASK; 1101 tmp |= TA_TIMEOUT_VALUE(ta_timeout); 1102 intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp); 1103 } 1104 } 1105 1106 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1107 bool enable) 1108 { 1109 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1110 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1111 u32 tmp; 1112 1113 /* 1114 * used as TE i/p for DSI0, 1115 * for dual link/DSI1 TE is from slave DSI1 1116 * through GPIO. 1117 */ 1118 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1119 return; 1120 1121 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL); 1122 1123 if (enable) { 1124 tmp |= UTIL_PIN_DIRECTION_INPUT; 1125 tmp |= UTIL_PIN_ENABLE; 1126 } else { 1127 tmp &= ~UTIL_PIN_ENABLE; 1128 } 1129 intel_de_write(dev_priv, UTIL_PIN_CTL, tmp); 1130 } 1131 1132 static void 1133 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1134 const struct intel_crtc_state *crtc_state) 1135 { 1136 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1137 1138 /* step 4a: power up all lanes of the DDI used by DSI */ 1139 gen11_dsi_power_up_lanes(encoder); 1140 1141 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1142 gen11_dsi_config_phy_lanes_sequence(encoder); 1143 1144 /* step 4c: configure voltage swing and skew */ 1145 gen11_dsi_voltage_swing_program_seq(encoder); 1146 1147 /* enable DDI buffer */ 1148 gen11_dsi_enable_ddi_buffer(encoder); 1149 1150 /* setup D-PHY timings */ 1151 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1152 1153 /* Since transcoder is configured to take events from GPIO */ 1154 gen11_dsi_config_util_pin(encoder, true); 1155 1156 /* step 4h: setup DSI protocol timeouts */ 1157 gen11_dsi_setup_timeouts(encoder, crtc_state); 1158 1159 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1160 gen11_dsi_configure_transcoder(encoder, crtc_state); 1161 1162 /* Step 4l: Gate DDI clocks */ 1163 if (DISPLAY_VER(dev_priv) == 11) 1164 gen11_dsi_gate_clocks(encoder); 1165 } 1166 1167 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1168 { 1169 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1170 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1171 struct mipi_dsi_device *dsi; 1172 enum port port; 1173 enum transcoder dsi_trans; 1174 u32 tmp; 1175 int ret; 1176 1177 /* set maximum return packet size */ 1178 for_each_dsi_port(port, intel_dsi->ports) { 1179 dsi_trans = dsi_port_to_transcoder(port); 1180 1181 /* 1182 * FIXME: This uses the number of DW's currently in the payload 1183 * receive queue. This is probably not what we want here. 1184 */ 1185 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans)); 1186 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1187 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1188 tmp = tmp * 4; 1189 dsi = intel_dsi->dsi_hosts[port]->device; 1190 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1191 if (ret < 0) 1192 drm_err(&dev_priv->drm, 1193 "error setting max return pkt size%d\n", tmp); 1194 } 1195 1196 /* panel power on related mipi dsi vbt sequences */ 1197 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1198 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 1199 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1200 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1201 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1202 1203 /* ensure all panel commands dispatched before enabling transcoder */ 1204 wait_for_cmds_dispatched_to_panel(encoder); 1205 } 1206 1207 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1208 struct intel_encoder *encoder, 1209 const struct intel_crtc_state *crtc_state, 1210 const struct drm_connector_state *conn_state) 1211 { 1212 /* step2: enable IO power */ 1213 gen11_dsi_enable_io_power(encoder); 1214 1215 /* step3: enable DSI PLL */ 1216 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1217 } 1218 1219 static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1220 struct intel_encoder *encoder, 1221 const struct intel_crtc_state *pipe_config, 1222 const struct drm_connector_state *conn_state) 1223 { 1224 /* step3b */ 1225 gen11_dsi_map_pll(encoder, pipe_config); 1226 1227 /* step4: enable DSI port and DPHY */ 1228 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1229 1230 /* step5: program and powerup panel */ 1231 gen11_dsi_powerup_panel(encoder); 1232 1233 intel_dsc_enable(encoder, pipe_config); 1234 1235 /* step6c: configure transcoder timings */ 1236 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1237 } 1238 1239 static void gen11_dsi_enable(struct intel_atomic_state *state, 1240 struct intel_encoder *encoder, 1241 const struct intel_crtc_state *crtc_state, 1242 const struct drm_connector_state *conn_state) 1243 { 1244 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1245 1246 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 1247 1248 /* step6d: enable dsi transcoder */ 1249 gen11_dsi_enable_transcoder(encoder); 1250 1251 /* step7: enable backlight */ 1252 intel_panel_enable_backlight(crtc_state, conn_state); 1253 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1254 1255 intel_crtc_vblank_on(crtc_state); 1256 } 1257 1258 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1259 { 1260 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1261 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1262 enum port port; 1263 enum transcoder dsi_trans; 1264 u32 tmp; 1265 1266 for_each_dsi_port(port, intel_dsi->ports) { 1267 dsi_trans = dsi_port_to_transcoder(port); 1268 1269 /* disable transcoder */ 1270 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1271 tmp &= ~PIPECONF_ENABLE; 1272 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1273 1274 /* wait for transcoder to be disabled */ 1275 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), 1276 I965_PIPECONF_ACTIVE, 50)) 1277 drm_err(&dev_priv->drm, 1278 "DSI trancoder not disabled\n"); 1279 } 1280 } 1281 1282 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1283 { 1284 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1285 1286 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1287 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1288 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1289 1290 /* ensure cmds dispatched to panel */ 1291 wait_for_cmds_dispatched_to_panel(encoder); 1292 } 1293 1294 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1295 { 1296 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1297 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1298 enum port port; 1299 enum transcoder dsi_trans; 1300 u32 tmp; 1301 1302 /* disable periodic update mode */ 1303 if (is_cmd_mode(intel_dsi)) { 1304 for_each_dsi_port(port, intel_dsi->ports) { 1305 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 1306 tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE; 1307 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 1308 } 1309 } 1310 1311 /* put dsi link in ULPS */ 1312 for_each_dsi_port(port, intel_dsi->ports) { 1313 dsi_trans = dsi_port_to_transcoder(port); 1314 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)); 1315 tmp |= LINK_ENTER_ULPS; 1316 tmp &= ~LINK_ULPS_TYPE_LP11; 1317 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp); 1318 1319 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 1320 LINK_IN_ULPS), 1321 10)) 1322 drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); 1323 } 1324 1325 /* disable ddi function */ 1326 for_each_dsi_port(port, intel_dsi->ports) { 1327 dsi_trans = dsi_port_to_transcoder(port); 1328 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1329 tmp &= ~TRANS_DDI_FUNC_ENABLE; 1330 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 1331 } 1332 1333 /* disable port sync mode if dual link */ 1334 if (intel_dsi->dual_link) { 1335 for_each_dsi_port(port, intel_dsi->ports) { 1336 dsi_trans = dsi_port_to_transcoder(port); 1337 tmp = intel_de_read(dev_priv, 1338 TRANS_DDI_FUNC_CTL2(dsi_trans)); 1339 tmp &= ~PORT_SYNC_MODE_ENABLE; 1340 intel_de_write(dev_priv, 1341 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 1342 } 1343 } 1344 } 1345 1346 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1347 { 1348 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1349 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1350 u32 tmp; 1351 enum port port; 1352 1353 gen11_dsi_ungate_clocks(encoder); 1354 for_each_dsi_port(port, intel_dsi->ports) { 1355 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1356 tmp &= ~DDI_BUF_CTL_ENABLE; 1357 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 1358 1359 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1360 DDI_BUF_IS_IDLE), 1361 8)) 1362 drm_err(&dev_priv->drm, 1363 "DDI port:%c buffer not idle\n", 1364 port_name(port)); 1365 } 1366 gen11_dsi_gate_clocks(encoder); 1367 } 1368 1369 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1370 { 1371 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1372 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1373 enum port port; 1374 u32 tmp; 1375 1376 for_each_dsi_port(port, intel_dsi->ports) { 1377 intel_wakeref_t wakeref; 1378 1379 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1380 intel_display_power_put(dev_priv, 1381 port == PORT_A ? 1382 POWER_DOMAIN_PORT_DDI_A_IO : 1383 POWER_DOMAIN_PORT_DDI_B_IO, 1384 wakeref); 1385 } 1386 1387 /* set mode to DDI */ 1388 for_each_dsi_port(port, intel_dsi->ports) { 1389 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 1390 tmp &= ~COMBO_PHY_MODE_DSI; 1391 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 1392 } 1393 } 1394 1395 static void gen11_dsi_disable(struct intel_atomic_state *state, 1396 struct intel_encoder *encoder, 1397 const struct intel_crtc_state *old_crtc_state, 1398 const struct drm_connector_state *old_conn_state) 1399 { 1400 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1401 1402 /* step1: turn off backlight */ 1403 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1404 intel_panel_disable_backlight(old_conn_state); 1405 1406 /* step2d,e: disable transcoder and wait */ 1407 gen11_dsi_disable_transcoder(encoder); 1408 1409 /* step2f,g: powerdown panel */ 1410 gen11_dsi_powerdown_panel(encoder); 1411 1412 /* step2h,i,j: deconfig trancoder */ 1413 gen11_dsi_deconfigure_trancoder(encoder); 1414 1415 /* step3: disable port */ 1416 gen11_dsi_disable_port(encoder); 1417 1418 gen11_dsi_config_util_pin(encoder, false); 1419 1420 /* step4: disable IO power */ 1421 gen11_dsi_disable_io_power(encoder); 1422 } 1423 1424 static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1425 struct intel_encoder *encoder, 1426 const struct intel_crtc_state *old_crtc_state, 1427 const struct drm_connector_state *old_conn_state) 1428 { 1429 intel_crtc_vblank_off(old_crtc_state); 1430 1431 intel_dsc_disable(old_crtc_state); 1432 1433 skl_scaler_disable(old_crtc_state); 1434 } 1435 1436 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1437 struct drm_display_mode *mode) 1438 { 1439 /* FIXME: DSC? */ 1440 return intel_dsi_mode_valid(connector, mode); 1441 } 1442 1443 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1444 struct intel_crtc_state *pipe_config) 1445 { 1446 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1447 struct drm_display_mode *adjusted_mode = 1448 &pipe_config->hw.adjusted_mode; 1449 1450 if (pipe_config->dsc.compressed_bpp) { 1451 int div = pipe_config->dsc.compressed_bpp; 1452 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1453 1454 adjusted_mode->crtc_htotal = 1455 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1456 adjusted_mode->crtc_hsync_start = 1457 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1458 adjusted_mode->crtc_hsync_end = 1459 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1460 } 1461 1462 if (intel_dsi->dual_link) { 1463 adjusted_mode->crtc_hdisplay *= 2; 1464 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1465 adjusted_mode->crtc_hdisplay -= 1466 intel_dsi->pixel_overlap; 1467 adjusted_mode->crtc_htotal *= 2; 1468 } 1469 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1470 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1471 1472 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1473 if (intel_dsi->dual_link) { 1474 adjusted_mode->crtc_hsync_start *= 2; 1475 adjusted_mode->crtc_hsync_end *= 2; 1476 } 1477 } 1478 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1479 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1480 } 1481 1482 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1483 { 1484 struct drm_device *dev = intel_dsi->base.base.dev; 1485 struct drm_i915_private *dev_priv = to_i915(dev); 1486 enum transcoder dsi_trans; 1487 u32 val; 1488 1489 if (intel_dsi->ports == BIT(PORT_B)) 1490 dsi_trans = TRANSCODER_DSI_1; 1491 else 1492 dsi_trans = TRANSCODER_DSI_0; 1493 1494 val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 1495 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1496 } 1497 1498 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1499 struct intel_crtc_state *pipe_config) 1500 { 1501 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1502 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1503 I915_MODE_FLAG_DSI_USE_TE0; 1504 else if (intel_dsi->ports == BIT(PORT_B)) 1505 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1506 else 1507 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1508 } 1509 1510 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1511 struct intel_crtc_state *pipe_config) 1512 { 1513 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1514 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1515 1516 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1517 1518 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1519 if (intel_dsi->dual_link) 1520 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1521 1522 gen11_dsi_get_timings(encoder, pipe_config); 1523 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1524 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1525 1526 /* Get the details on which TE should be enabled */ 1527 if (is_cmd_mode(intel_dsi)) 1528 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1529 1530 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1531 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1532 } 1533 1534 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1535 struct intel_crtc_state *crtc_state) 1536 { 1537 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1538 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1539 int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10; 1540 bool use_dsc; 1541 int ret; 1542 1543 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1544 if (!use_dsc) 1545 return 0; 1546 1547 if (crtc_state->pipe_bpp < 8 * 3) 1548 return -EINVAL; 1549 1550 /* FIXME: split only when necessary */ 1551 if (crtc_state->dsc.slice_count > 1) 1552 crtc_state->dsc.dsc_split = true; 1553 1554 vdsc_cfg->convert_rgb = true; 1555 1556 /* FIXME: initialize from VBT */ 1557 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1558 1559 ret = intel_dsc_compute_params(encoder, crtc_state); 1560 if (ret) 1561 return ret; 1562 1563 /* DSI specific sanity checks on the common code */ 1564 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); 1565 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); 1566 drm_WARN_ON(&dev_priv->drm, 1567 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1568 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); 1569 drm_WARN_ON(&dev_priv->drm, 1570 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1571 1572 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1573 if (ret) 1574 return ret; 1575 1576 crtc_state->dsc.compression_enable = true; 1577 1578 return 0; 1579 } 1580 1581 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1582 struct intel_crtc_state *pipe_config, 1583 struct drm_connector_state *conn_state) 1584 { 1585 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1586 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 1587 base); 1588 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1589 const struct drm_display_mode *fixed_mode = 1590 intel_connector->panel.fixed_mode; 1591 struct drm_display_mode *adjusted_mode = 1592 &pipe_config->hw.adjusted_mode; 1593 int ret; 1594 1595 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1596 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 1597 1598 ret = intel_pch_panel_fitting(pipe_config, conn_state); 1599 if (ret) 1600 return ret; 1601 1602 adjusted_mode->flags = 0; 1603 1604 /* Dual link goes to trancoder DSI'0' */ 1605 if (intel_dsi->ports == BIT(PORT_B)) 1606 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1607 else 1608 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1609 1610 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1611 pipe_config->pipe_bpp = 24; 1612 else 1613 pipe_config->pipe_bpp = 18; 1614 1615 pipe_config->clock_set = true; 1616 1617 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1618 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n"); 1619 1620 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1621 1622 /* 1623 * In case of TE GATE cmd mode, we 1624 * receive TE from the slave if 1625 * dual link is enabled 1626 */ 1627 if (is_cmd_mode(intel_dsi)) 1628 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1629 1630 return 0; 1631 } 1632 1633 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1634 struct intel_crtc_state *crtc_state) 1635 { 1636 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1637 1638 get_dsi_io_power_domains(i915, 1639 enc_to_intel_dsi(encoder)); 1640 } 1641 1642 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1643 enum pipe *pipe) 1644 { 1645 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1646 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1647 enum transcoder dsi_trans; 1648 intel_wakeref_t wakeref; 1649 enum port port; 1650 bool ret = false; 1651 u32 tmp; 1652 1653 wakeref = intel_display_power_get_if_enabled(dev_priv, 1654 encoder->power_domain); 1655 if (!wakeref) 1656 return false; 1657 1658 for_each_dsi_port(port, intel_dsi->ports) { 1659 dsi_trans = dsi_port_to_transcoder(port); 1660 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1661 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1662 case TRANS_DDI_EDP_INPUT_A_ON: 1663 *pipe = PIPE_A; 1664 break; 1665 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1666 *pipe = PIPE_B; 1667 break; 1668 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1669 *pipe = PIPE_C; 1670 break; 1671 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1672 *pipe = PIPE_D; 1673 break; 1674 default: 1675 drm_err(&dev_priv->drm, "Invalid PIPE input\n"); 1676 goto out; 1677 } 1678 1679 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1680 ret = tmp & PIPECONF_ENABLE; 1681 } 1682 out: 1683 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1684 return ret; 1685 } 1686 1687 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1688 struct intel_crtc_state *crtc_state) 1689 { 1690 if (crtc_state->dsc.compression_enable) { 1691 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1692 crtc_state->uapi.mode_changed = true; 1693 1694 return false; 1695 } 1696 1697 return true; 1698 } 1699 1700 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1701 { 1702 intel_encoder_destroy(encoder); 1703 } 1704 1705 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1706 .destroy = gen11_dsi_encoder_destroy, 1707 }; 1708 1709 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1710 .detect = intel_panel_detect, 1711 .late_register = intel_connector_register, 1712 .early_unregister = intel_connector_unregister, 1713 .destroy = intel_connector_destroy, 1714 .fill_modes = drm_helper_probe_single_connector_modes, 1715 .atomic_get_property = intel_digital_connector_atomic_get_property, 1716 .atomic_set_property = intel_digital_connector_atomic_set_property, 1717 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1718 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1719 }; 1720 1721 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1722 .get_modes = intel_dsi_get_modes, 1723 .mode_valid = gen11_dsi_mode_valid, 1724 .atomic_check = intel_digital_connector_atomic_check, 1725 }; 1726 1727 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1728 struct mipi_dsi_device *dsi) 1729 { 1730 return 0; 1731 } 1732 1733 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1734 struct mipi_dsi_device *dsi) 1735 { 1736 return 0; 1737 } 1738 1739 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1740 const struct mipi_dsi_msg *msg) 1741 { 1742 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1743 struct mipi_dsi_packet dsi_pkt; 1744 ssize_t ret; 1745 bool enable_lpdt = false; 1746 1747 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1748 if (ret < 0) 1749 return ret; 1750 1751 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1752 enable_lpdt = true; 1753 1754 /* send packet header */ 1755 ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt); 1756 if (ret < 0) 1757 return ret; 1758 1759 /* only long packet contains payload */ 1760 if (mipi_dsi_packet_format_is_long(msg->type)) { 1761 ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt); 1762 if (ret < 0) 1763 return ret; 1764 } 1765 1766 //TODO: add payload receive code if needed 1767 1768 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1769 1770 return ret; 1771 } 1772 1773 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1774 .attach = gen11_dsi_host_attach, 1775 .detach = gen11_dsi_host_detach, 1776 .transfer = gen11_dsi_host_transfer, 1777 }; 1778 1779 #define ICL_PREPARE_CNT_MAX 0x7 1780 #define ICL_CLK_ZERO_CNT_MAX 0xf 1781 #define ICL_TRAIL_CNT_MAX 0x7 1782 #define ICL_TCLK_PRE_CNT_MAX 0x3 1783 #define ICL_TCLK_POST_CNT_MAX 0x7 1784 #define ICL_HS_ZERO_CNT_MAX 0xf 1785 #define ICL_EXIT_ZERO_CNT_MAX 0x7 1786 1787 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1788 { 1789 struct drm_device *dev = intel_dsi->base.base.dev; 1790 struct drm_i915_private *dev_priv = to_i915(dev); 1791 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 1792 u32 tlpx_ns; 1793 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1794 u32 ths_prepare_ns, tclk_trail_ns; 1795 u32 hs_zero_cnt; 1796 u32 tclk_pre_cnt, tclk_post_cnt; 1797 1798 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1799 1800 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1801 ths_prepare_ns = max(mipi_config->ths_prepare, 1802 mipi_config->tclk_prepare); 1803 1804 /* 1805 * prepare cnt in escape clocks 1806 * this field represents a hexadecimal value with a precision 1807 * of 1.2 – i.e. the most significant bit is the integer 1808 * and the least significant 2 bits are fraction bits. 1809 * so, the field can represent a range of 0.25 to 1.75 1810 */ 1811 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1812 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1813 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", 1814 prepare_cnt); 1815 prepare_cnt = ICL_PREPARE_CNT_MAX; 1816 } 1817 1818 /* clk zero count in escape clocks */ 1819 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1820 ths_prepare_ns, tlpx_ns); 1821 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1822 drm_dbg_kms(&dev_priv->drm, 1823 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1824 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1825 } 1826 1827 /* trail cnt in escape clocks*/ 1828 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1829 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1830 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", 1831 trail_cnt); 1832 trail_cnt = ICL_TRAIL_CNT_MAX; 1833 } 1834 1835 /* tclk pre count in escape clocks */ 1836 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1837 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1838 drm_dbg_kms(&dev_priv->drm, 1839 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1840 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1841 } 1842 1843 /* tclk post count in escape clocks */ 1844 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); 1845 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { 1846 drm_dbg_kms(&dev_priv->drm, 1847 "tclk_post_cnt out of range (%d)\n", 1848 tclk_post_cnt); 1849 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; 1850 } 1851 1852 /* hs zero cnt in escape clocks */ 1853 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1854 ths_prepare_ns, tlpx_ns); 1855 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1856 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", 1857 hs_zero_cnt); 1858 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1859 } 1860 1861 /* hs exit zero cnt in escape clocks */ 1862 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1863 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1864 drm_dbg_kms(&dev_priv->drm, 1865 "exit_zero_cnt out of range (%d)\n", 1866 exit_zero_cnt); 1867 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1868 } 1869 1870 /* clock lane dphy timings */ 1871 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1872 CLK_PREPARE(prepare_cnt) | 1873 CLK_ZERO_OVERRIDE | 1874 CLK_ZERO(clk_zero_cnt) | 1875 CLK_PRE_OVERRIDE | 1876 CLK_PRE(tclk_pre_cnt) | 1877 CLK_POST_OVERRIDE | 1878 CLK_POST(tclk_post_cnt) | 1879 CLK_TRAIL_OVERRIDE | 1880 CLK_TRAIL(trail_cnt)); 1881 1882 /* data lanes dphy timings */ 1883 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1884 HS_PREPARE(prepare_cnt) | 1885 HS_ZERO_OVERRIDE | 1886 HS_ZERO(hs_zero_cnt) | 1887 HS_TRAIL_OVERRIDE | 1888 HS_TRAIL(trail_cnt) | 1889 HS_EXIT_OVERRIDE | 1890 HS_EXIT(exit_zero_cnt)); 1891 1892 intel_dsi_log_params(intel_dsi); 1893 } 1894 1895 static void icl_dsi_add_properties(struct intel_connector *connector) 1896 { 1897 u32 allowed_scalers; 1898 1899 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | 1900 BIT(DRM_MODE_SCALE_FULLSCREEN) | 1901 BIT(DRM_MODE_SCALE_CENTER); 1902 1903 drm_connector_attach_scaling_mode_property(&connector->base, 1904 allowed_scalers); 1905 1906 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1907 1908 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1909 intel_dsi_get_panel_orientation(connector), 1910 connector->panel.fixed_mode->hdisplay, 1911 connector->panel.fixed_mode->vdisplay); 1912 } 1913 1914 void icl_dsi_init(struct drm_i915_private *dev_priv) 1915 { 1916 struct drm_device *dev = &dev_priv->drm; 1917 struct intel_dsi *intel_dsi; 1918 struct intel_encoder *encoder; 1919 struct intel_connector *intel_connector; 1920 struct drm_connector *connector; 1921 struct drm_display_mode *fixed_mode; 1922 enum port port; 1923 1924 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1925 return; 1926 1927 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1928 if (!intel_dsi) 1929 return; 1930 1931 intel_connector = intel_connector_alloc(); 1932 if (!intel_connector) { 1933 kfree(intel_dsi); 1934 return; 1935 } 1936 1937 encoder = &intel_dsi->base; 1938 intel_dsi->attached_connector = intel_connector; 1939 connector = &intel_connector->base; 1940 1941 /* register DSI encoder with DRM subsystem */ 1942 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs, 1943 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 1944 1945 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 1946 encoder->pre_enable = gen11_dsi_pre_enable; 1947 encoder->enable = gen11_dsi_enable; 1948 encoder->disable = gen11_dsi_disable; 1949 encoder->post_disable = gen11_dsi_post_disable; 1950 encoder->port = port; 1951 encoder->get_config = gen11_dsi_get_config; 1952 encoder->update_pipe = intel_panel_update_backlight; 1953 encoder->compute_config = gen11_dsi_compute_config; 1954 encoder->get_hw_state = gen11_dsi_get_hw_state; 1955 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 1956 encoder->type = INTEL_OUTPUT_DSI; 1957 encoder->cloneable = 0; 1958 encoder->pipe_mask = ~0; 1959 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1960 encoder->get_power_domains = gen11_dsi_get_power_domains; 1961 encoder->disable_clock = gen11_dsi_gate_clocks; 1962 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 1963 1964 /* register DSI connector with DRM subsystem */ 1965 drm_connector_init(dev, connector, &gen11_dsi_connector_funcs, 1966 DRM_MODE_CONNECTOR_DSI); 1967 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 1968 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1969 connector->interlace_allowed = false; 1970 connector->doublescan_allowed = false; 1971 intel_connector->get_hw_state = intel_connector_get_hw_state; 1972 1973 /* attach connector to encoder */ 1974 intel_connector_attach_encoder(intel_connector, encoder); 1975 1976 mutex_lock(&dev->mode_config.mutex); 1977 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 1978 mutex_unlock(&dev->mode_config.mutex); 1979 1980 if (!fixed_mode) { 1981 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); 1982 goto err; 1983 } 1984 1985 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 1986 intel_panel_setup_backlight(connector, INVALID_PIPE); 1987 1988 if (dev_priv->vbt.dsi.config->dual_link) 1989 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 1990 else 1991 intel_dsi->ports = BIT(port); 1992 1993 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; 1994 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; 1995 1996 for_each_dsi_port(port, intel_dsi->ports) { 1997 struct intel_dsi_host *host; 1998 1999 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2000 if (!host) 2001 goto err; 2002 2003 intel_dsi->dsi_hosts[port] = host; 2004 } 2005 2006 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2007 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 2008 goto err; 2009 } 2010 2011 icl_dphy_param_init(intel_dsi); 2012 2013 icl_dsi_add_properties(intel_connector); 2014 return; 2015 2016 err: 2017 drm_connector_cleanup(connector); 2018 drm_encoder_cleanup(&encoder->base); 2019 kfree(intel_dsi); 2020 kfree(intel_connector); 2021 } 2022