1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_mipi_dsi.h> 30 31 #include "intel_atomic.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_crtc.h" 35 #include "intel_ddi.h" 36 #include "intel_de.h" 37 #include "intel_dsi.h" 38 #include "intel_panel.h" 39 #include "intel_vdsc.h" 40 #include "skl_scaler.h" 41 #include "skl_universal_plane.h" 42 43 static int header_credits_available(struct drm_i915_private *dev_priv, 44 enum transcoder dsi_trans) 45 { 46 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 47 >> FREE_HEADER_CREDIT_SHIFT; 48 } 49 50 static int payload_credits_available(struct drm_i915_private *dev_priv, 51 enum transcoder dsi_trans) 52 { 53 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 54 >> FREE_PLOAD_CREDIT_SHIFT; 55 } 56 57 static void wait_for_header_credits(struct drm_i915_private *dev_priv, 58 enum transcoder dsi_trans) 59 { 60 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= 61 MAX_HEADER_CREDIT, 100)) 62 drm_err(&dev_priv->drm, "DSI header credits not released\n"); 63 } 64 65 static void wait_for_payload_credits(struct drm_i915_private *dev_priv, 66 enum transcoder dsi_trans) 67 { 68 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= 69 MAX_PLOAD_CREDIT, 100)) 70 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); 71 } 72 73 static enum transcoder dsi_port_to_transcoder(enum port port) 74 { 75 if (port == PORT_A) 76 return TRANSCODER_DSI_0; 77 else 78 return TRANSCODER_DSI_1; 79 } 80 81 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 82 { 83 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 84 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 85 struct mipi_dsi_device *dsi; 86 enum port port; 87 enum transcoder dsi_trans; 88 int ret; 89 90 /* wait for header/payload credits to be released */ 91 for_each_dsi_port(port, intel_dsi->ports) { 92 dsi_trans = dsi_port_to_transcoder(port); 93 wait_for_header_credits(dev_priv, dsi_trans); 94 wait_for_payload_credits(dev_priv, dsi_trans); 95 } 96 97 /* send nop DCS command */ 98 for_each_dsi_port(port, intel_dsi->ports) { 99 dsi = intel_dsi->dsi_hosts[port]->device; 100 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 101 dsi->channel = 0; 102 ret = mipi_dsi_dcs_nop(dsi); 103 if (ret < 0) 104 drm_err(&dev_priv->drm, 105 "error sending DCS NOP command\n"); 106 } 107 108 /* wait for header credits to be released */ 109 for_each_dsi_port(port, intel_dsi->ports) { 110 dsi_trans = dsi_port_to_transcoder(port); 111 wait_for_header_credits(dev_priv, dsi_trans); 112 } 113 114 /* wait for LP TX in progress bit to be cleared */ 115 for_each_dsi_port(port, intel_dsi->ports) { 116 dsi_trans = dsi_port_to_transcoder(port); 117 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 118 LPTX_IN_PROGRESS), 20)) 119 drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); 120 } 121 } 122 123 static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data, 124 u32 len) 125 { 126 struct intel_dsi *intel_dsi = host->intel_dsi; 127 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 128 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 129 int free_credits; 130 int i, j; 131 132 for (i = 0; i < len; i += 4) { 133 u32 tmp = 0; 134 135 free_credits = payload_credits_available(dev_priv, dsi_trans); 136 if (free_credits < 1) { 137 drm_err(&dev_priv->drm, 138 "Payload credit not available\n"); 139 return false; 140 } 141 142 for (j = 0; j < min_t(u32, len - i, 4); j++) 143 tmp |= *data++ << 8 * j; 144 145 intel_de_write(dev_priv, DSI_CMD_TXPYLD(dsi_trans), tmp); 146 } 147 148 return true; 149 } 150 151 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 152 struct mipi_dsi_packet pkt, bool enable_lpdt) 153 { 154 struct intel_dsi *intel_dsi = host->intel_dsi; 155 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 156 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 157 u32 tmp; 158 int free_credits; 159 160 /* check if header credit available */ 161 free_credits = header_credits_available(dev_priv, dsi_trans); 162 if (free_credits < 1) { 163 drm_err(&dev_priv->drm, 164 "send pkt header failed, not enough hdr credits\n"); 165 return -1; 166 } 167 168 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); 169 170 if (pkt.payload) 171 tmp |= PAYLOAD_PRESENT; 172 else 173 tmp &= ~PAYLOAD_PRESENT; 174 175 tmp &= ~VBLANK_FENCE; 176 177 if (enable_lpdt) 178 tmp |= LP_DATA_TRANSFER; 179 180 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 181 tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT); 182 tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT); 183 tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT); 184 tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT); 185 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); 186 187 return 0; 188 } 189 190 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 191 struct mipi_dsi_packet pkt) 192 { 193 struct intel_dsi *intel_dsi = host->intel_dsi; 194 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 195 196 /* payload queue can accept *256 bytes*, check limit */ 197 if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) { 198 drm_err(&i915->drm, "payload size exceeds max queue limit\n"); 199 return -1; 200 } 201 202 /* load data into command payload queue */ 203 if (!add_payld_to_queue(host, pkt.payload, 204 pkt.payload_length)) { 205 drm_err(&i915->drm, "adding payload to queue failed\n"); 206 return -1; 207 } 208 209 return 0; 210 } 211 212 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 213 { 214 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 215 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 216 u32 tmp, mode_flags; 217 enum port port; 218 219 mode_flags = crtc_state->mode_flags; 220 221 /* 222 * case 1 also covers dual link 223 * In case of dual link, frame update should be set on 224 * DSI_0 225 */ 226 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 227 port = PORT_A; 228 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 229 port = PORT_B; 230 else 231 return; 232 233 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 234 tmp |= DSI_FRAME_UPDATE_REQUEST; 235 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 236 } 237 238 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 239 { 240 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 241 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 242 enum phy phy; 243 u32 tmp; 244 int lane; 245 246 for_each_dsi_phy(phy, intel_dsi->phys) { 247 /* 248 * Program voltage swing and pre-emphasis level values as per 249 * table in BSPEC under DDI buffer programing 250 */ 251 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 252 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 253 tmp |= SCALING_MODE_SEL(0x2); 254 tmp |= TAP2_DISABLE | TAP3_DISABLE; 255 tmp |= RTERM_SELECT(0x6); 256 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 257 258 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 259 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 260 tmp |= SCALING_MODE_SEL(0x2); 261 tmp |= TAP2_DISABLE | TAP3_DISABLE; 262 tmp |= RTERM_SELECT(0x6); 263 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 264 265 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 266 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 267 RCOMP_SCALAR_MASK); 268 tmp |= SWING_SEL_UPPER(0x2); 269 tmp |= SWING_SEL_LOWER(0x2); 270 tmp |= RCOMP_SCALAR(0x98); 271 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 272 273 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 274 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 275 RCOMP_SCALAR_MASK); 276 tmp |= SWING_SEL_UPPER(0x2); 277 tmp |= SWING_SEL_LOWER(0x2); 278 tmp |= RCOMP_SCALAR(0x98); 279 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 280 281 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 282 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 283 CURSOR_COEFF_MASK); 284 tmp |= POST_CURSOR_1(0x0); 285 tmp |= POST_CURSOR_2(0x0); 286 tmp |= CURSOR_COEFF(0x3f); 287 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 288 289 for (lane = 0; lane <= 3; lane++) { 290 /* Bspec: must not use GRP register for write */ 291 tmp = intel_de_read(dev_priv, 292 ICL_PORT_TX_DW4_LN(lane, phy)); 293 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 294 CURSOR_COEFF_MASK); 295 tmp |= POST_CURSOR_1(0x0); 296 tmp |= POST_CURSOR_2(0x0); 297 tmp |= CURSOR_COEFF(0x3f); 298 intel_de_write(dev_priv, 299 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 300 } 301 } 302 } 303 304 static void configure_dual_link_mode(struct intel_encoder *encoder, 305 const struct intel_crtc_state *pipe_config) 306 { 307 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 308 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 309 u32 dss_ctl1; 310 311 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); 312 dss_ctl1 |= SPLITTER_ENABLE; 313 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 314 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 315 316 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 317 const struct drm_display_mode *adjusted_mode = 318 &pipe_config->hw.adjusted_mode; 319 u32 dss_ctl2; 320 u16 hactive = adjusted_mode->crtc_hdisplay; 321 u16 dl_buffer_depth; 322 323 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 324 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 325 326 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 327 drm_err(&dev_priv->drm, 328 "DL buffer depth exceed max value\n"); 329 330 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 331 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 332 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); 333 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; 334 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 335 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); 336 } else { 337 /* Interleave */ 338 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 339 } 340 341 intel_de_write(dev_priv, DSS_CTL1, dss_ctl1); 342 } 343 344 /* aka DSI 8X clock */ 345 static int afe_clk(struct intel_encoder *encoder, 346 const struct intel_crtc_state *crtc_state) 347 { 348 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 349 int bpp; 350 351 if (crtc_state->dsc.compression_enable) 352 bpp = crtc_state->dsc.compressed_bpp; 353 else 354 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 355 356 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 357 } 358 359 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 360 const struct intel_crtc_state *crtc_state) 361 { 362 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 363 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 364 enum port port; 365 int afe_clk_khz; 366 int theo_word_clk, act_word_clk; 367 u32 esc_clk_div_m, esc_clk_div_m_phy; 368 369 afe_clk_khz = afe_clk(encoder, crtc_state); 370 371 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 372 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 373 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 374 esc_clk_div_m = act_word_clk * 8; 375 esc_clk_div_m_phy = (act_word_clk - 1) / 2; 376 } else { 377 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 378 } 379 380 for_each_dsi_port(port, intel_dsi->ports) { 381 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), 382 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 383 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); 384 } 385 386 for_each_dsi_port(port, intel_dsi->ports) { 387 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port), 388 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 389 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); 390 } 391 392 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 393 for_each_dsi_port(port, intel_dsi->ports) { 394 intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8), 395 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); 396 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8)); 397 } 398 } 399 } 400 401 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, 402 struct intel_dsi *intel_dsi) 403 { 404 enum port port; 405 406 for_each_dsi_port(port, intel_dsi->ports) { 407 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); 408 intel_dsi->io_wakeref[port] = 409 intel_display_power_get(dev_priv, 410 port == PORT_A ? 411 POWER_DOMAIN_PORT_DDI_A_IO : 412 POWER_DOMAIN_PORT_DDI_B_IO); 413 } 414 } 415 416 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 417 { 418 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 419 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 420 enum port port; 421 u32 tmp; 422 423 for_each_dsi_port(port, intel_dsi->ports) { 424 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 425 tmp |= COMBO_PHY_MODE_DSI; 426 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 427 } 428 429 get_dsi_io_power_domains(dev_priv, intel_dsi); 430 } 431 432 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 433 { 434 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 435 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 436 enum phy phy; 437 438 for_each_dsi_phy(phy, intel_dsi->phys) 439 intel_combo_phy_power_up_lanes(dev_priv, phy, true, 440 intel_dsi->lane_count, false); 441 } 442 443 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 444 { 445 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 446 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 447 enum phy phy; 448 u32 tmp; 449 int lane; 450 451 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 452 for_each_dsi_phy(phy, intel_dsi->phys) { 453 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 454 tmp &= ~LOADGEN_SELECT; 455 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 456 for (lane = 0; lane <= 3; lane++) { 457 tmp = intel_de_read(dev_priv, 458 ICL_PORT_TX_DW4_LN(lane, phy)); 459 tmp &= ~LOADGEN_SELECT; 460 if (lane != 2) 461 tmp |= LOADGEN_SELECT; 462 intel_de_write(dev_priv, 463 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 464 } 465 } 466 467 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 468 for_each_dsi_phy(phy, intel_dsi->phys) { 469 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 470 tmp &= ~FRC_LATENCY_OPTIM_MASK; 471 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 472 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 473 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 474 tmp &= ~FRC_LATENCY_OPTIM_MASK; 475 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 476 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 477 478 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 479 if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) { 480 tmp = intel_de_read(dev_priv, 481 ICL_PORT_PCS_DW1_AUX(phy)); 482 tmp &= ~LATENCY_OPTIM_MASK; 483 tmp |= LATENCY_OPTIM_VAL(0); 484 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), 485 tmp); 486 487 tmp = intel_de_read(dev_priv, 488 ICL_PORT_PCS_DW1_LN0(phy)); 489 tmp &= ~LATENCY_OPTIM_MASK; 490 tmp |= LATENCY_OPTIM_VAL(0x1); 491 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), 492 tmp); 493 } 494 } 495 496 } 497 498 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 499 { 500 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 501 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 502 u32 tmp; 503 enum phy phy; 504 505 /* clear common keeper enable bit */ 506 for_each_dsi_phy(phy, intel_dsi->phys) { 507 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 508 tmp &= ~COMMON_KEEPER_EN; 509 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp); 510 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy)); 511 tmp &= ~COMMON_KEEPER_EN; 512 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp); 513 } 514 515 /* 516 * Set SUS Clock Config bitfield to 11b 517 * Note: loadgen select program is done 518 * as part of lane phy sequence configuration 519 */ 520 for_each_dsi_phy(phy, intel_dsi->phys) { 521 tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 522 tmp |= SUS_CLOCK_CONFIG; 523 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp); 524 } 525 526 /* Clear training enable to change swing values */ 527 for_each_dsi_phy(phy, intel_dsi->phys) { 528 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 529 tmp &= ~TX_TRAINING_EN; 530 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 531 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 532 tmp &= ~TX_TRAINING_EN; 533 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 534 } 535 536 /* Program swing and de-emphasis */ 537 dsi_program_swing_and_deemphasis(encoder); 538 539 /* Set training enable to trigger update */ 540 for_each_dsi_phy(phy, intel_dsi->phys) { 541 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 542 tmp |= TX_TRAINING_EN; 543 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 544 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 545 tmp |= TX_TRAINING_EN; 546 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 547 } 548 } 549 550 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 551 { 552 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 553 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 554 u32 tmp; 555 enum port port; 556 557 for_each_dsi_port(port, intel_dsi->ports) { 558 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 559 tmp |= DDI_BUF_CTL_ENABLE; 560 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 561 562 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 563 DDI_BUF_IS_IDLE), 564 500)) 565 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", 566 port_name(port)); 567 } 568 } 569 570 static void 571 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 572 const struct intel_crtc_state *crtc_state) 573 { 574 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 575 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 576 u32 tmp; 577 enum port port; 578 enum phy phy; 579 580 /* Program T-INIT master registers */ 581 for_each_dsi_port(port, intel_dsi->ports) { 582 tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port)); 583 tmp &= ~MASTER_INIT_TIMER_MASK; 584 tmp |= intel_dsi->init_count; 585 intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp); 586 } 587 588 /* Program DPHY clock lanes timings */ 589 for_each_dsi_port(port, intel_dsi->ports) { 590 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port), 591 intel_dsi->dphy_reg); 592 593 /* shadow register inside display core */ 594 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port), 595 intel_dsi->dphy_reg); 596 } 597 598 /* Program DPHY data lanes timings */ 599 for_each_dsi_port(port, intel_dsi->ports) { 600 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port), 601 intel_dsi->dphy_data_lane_reg); 602 603 /* shadow register inside display core */ 604 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port), 605 intel_dsi->dphy_data_lane_reg); 606 } 607 608 /* 609 * If DSI link operating at or below an 800 MHz, 610 * TA_SURE should be override and programmed to 611 * a value '0' inside TA_PARAM_REGISTERS otherwise 612 * leave all fields at HW default values. 613 */ 614 if (DISPLAY_VER(dev_priv) == 11) { 615 if (afe_clk(encoder, crtc_state) <= 800000) { 616 for_each_dsi_port(port, intel_dsi->ports) { 617 tmp = intel_de_read(dev_priv, 618 DPHY_TA_TIMING_PARAM(port)); 619 tmp &= ~TA_SURE_MASK; 620 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 621 intel_de_write(dev_priv, 622 DPHY_TA_TIMING_PARAM(port), 623 tmp); 624 625 /* shadow register inside display core */ 626 tmp = intel_de_read(dev_priv, 627 DSI_TA_TIMING_PARAM(port)); 628 tmp &= ~TA_SURE_MASK; 629 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 630 intel_de_write(dev_priv, 631 DSI_TA_TIMING_PARAM(port), tmp); 632 } 633 } 634 } 635 636 if (IS_JSL_EHL(dev_priv)) { 637 for_each_dsi_phy(phy, intel_dsi->phys) { 638 tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy)); 639 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; 640 intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp); 641 } 642 } 643 } 644 645 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 646 { 647 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 648 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 649 u32 tmp; 650 enum phy phy; 651 652 mutex_lock(&dev_priv->dpll.lock); 653 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 654 for_each_dsi_phy(phy, intel_dsi->phys) 655 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 656 657 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 658 mutex_unlock(&dev_priv->dpll.lock); 659 } 660 661 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 662 { 663 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 664 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 665 u32 tmp; 666 enum phy phy; 667 668 mutex_lock(&dev_priv->dpll.lock); 669 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 670 for_each_dsi_phy(phy, intel_dsi->phys) 671 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 672 673 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 674 mutex_unlock(&dev_priv->dpll.lock); 675 } 676 677 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 678 { 679 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 680 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 681 bool clock_enabled = false; 682 enum phy phy; 683 u32 tmp; 684 685 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 686 687 for_each_dsi_phy(phy, intel_dsi->phys) { 688 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 689 clock_enabled = true; 690 } 691 692 return clock_enabled; 693 } 694 695 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 696 const struct intel_crtc_state *crtc_state) 697 { 698 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 699 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 700 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 701 enum phy phy; 702 u32 val; 703 704 mutex_lock(&dev_priv->dpll.lock); 705 706 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 707 for_each_dsi_phy(phy, intel_dsi->phys) { 708 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 709 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 710 } 711 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 712 713 for_each_dsi_phy(phy, intel_dsi->phys) { 714 if (DISPLAY_VER(dev_priv) >= 12) 715 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 716 else 717 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 718 } 719 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 720 721 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 722 723 mutex_unlock(&dev_priv->dpll.lock); 724 } 725 726 static void 727 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 728 const struct intel_crtc_state *pipe_config) 729 { 730 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 731 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 732 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 733 enum pipe pipe = intel_crtc->pipe; 734 u32 tmp; 735 enum port port; 736 enum transcoder dsi_trans; 737 738 for_each_dsi_port(port, intel_dsi->ports) { 739 dsi_trans = dsi_port_to_transcoder(port); 740 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 741 742 if (intel_dsi->eotp_pkt) 743 tmp &= ~EOTP_DISABLED; 744 else 745 tmp |= EOTP_DISABLED; 746 747 /* enable link calibration if freq > 1.5Gbps */ 748 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 749 tmp &= ~LINK_CALIBRATION_MASK; 750 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 751 } 752 753 /* configure continuous clock */ 754 tmp &= ~CONTINUOUS_CLK_MASK; 755 if (intel_dsi->clock_stop) 756 tmp |= CLK_ENTER_LP_AFTER_DATA; 757 else 758 tmp |= CLK_HS_CONTINUOUS; 759 760 /* configure buffer threshold limit to minimum */ 761 tmp &= ~PIX_BUF_THRESHOLD_MASK; 762 tmp |= PIX_BUF_THRESHOLD_1_4; 763 764 /* set virtual channel to '0' */ 765 tmp &= ~PIX_VIRT_CHAN_MASK; 766 tmp |= PIX_VIRT_CHAN(0); 767 768 /* program BGR transmission */ 769 if (intel_dsi->bgr_enabled) 770 tmp |= BGR_TRANSMISSION; 771 772 /* select pixel format */ 773 tmp &= ~PIX_FMT_MASK; 774 if (pipe_config->dsc.compression_enable) { 775 tmp |= PIX_FMT_COMPRESSED; 776 } else { 777 switch (intel_dsi->pixel_format) { 778 default: 779 MISSING_CASE(intel_dsi->pixel_format); 780 fallthrough; 781 case MIPI_DSI_FMT_RGB565: 782 tmp |= PIX_FMT_RGB565; 783 break; 784 case MIPI_DSI_FMT_RGB666_PACKED: 785 tmp |= PIX_FMT_RGB666_PACKED; 786 break; 787 case MIPI_DSI_FMT_RGB666: 788 tmp |= PIX_FMT_RGB666_LOOSE; 789 break; 790 case MIPI_DSI_FMT_RGB888: 791 tmp |= PIX_FMT_RGB888; 792 break; 793 } 794 } 795 796 if (DISPLAY_VER(dev_priv) >= 12) { 797 if (is_vid_mode(intel_dsi)) 798 tmp |= BLANKING_PACKET_ENABLE; 799 } 800 801 /* program DSI operation mode */ 802 if (is_vid_mode(intel_dsi)) { 803 tmp &= ~OP_MODE_MASK; 804 switch (intel_dsi->video_mode_format) { 805 default: 806 MISSING_CASE(intel_dsi->video_mode_format); 807 fallthrough; 808 case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS: 809 tmp |= VIDEO_MODE_SYNC_EVENT; 810 break; 811 case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE: 812 tmp |= VIDEO_MODE_SYNC_PULSE; 813 break; 814 } 815 } else { 816 /* 817 * FIXME: Retrieve this info from VBT. 818 * As per the spec when dsi transcoder is operating 819 * in TE GATE mode, TE comes from GPIO 820 * which is UTIL PIN for DSI 0. 821 * Also this GPIO would not be used for other 822 * purposes is an assumption. 823 */ 824 tmp &= ~OP_MODE_MASK; 825 tmp |= CMD_MODE_TE_GATE; 826 tmp |= TE_SOURCE_GPIO; 827 } 828 829 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 830 } 831 832 /* enable port sync mode if dual link */ 833 if (intel_dsi->dual_link) { 834 for_each_dsi_port(port, intel_dsi->ports) { 835 dsi_trans = dsi_port_to_transcoder(port); 836 tmp = intel_de_read(dev_priv, 837 TRANS_DDI_FUNC_CTL2(dsi_trans)); 838 tmp |= PORT_SYNC_MODE_ENABLE; 839 intel_de_write(dev_priv, 840 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 841 } 842 843 /* configure stream splitting */ 844 configure_dual_link_mode(encoder, pipe_config); 845 } 846 847 for_each_dsi_port(port, intel_dsi->ports) { 848 dsi_trans = dsi_port_to_transcoder(port); 849 850 /* select data lane width */ 851 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 852 tmp &= ~DDI_PORT_WIDTH_MASK; 853 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); 854 855 /* select input pipe */ 856 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 857 switch (pipe) { 858 default: 859 MISSING_CASE(pipe); 860 fallthrough; 861 case PIPE_A: 862 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 863 break; 864 case PIPE_B: 865 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 866 break; 867 case PIPE_C: 868 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 869 break; 870 case PIPE_D: 871 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 872 break; 873 } 874 875 /* enable DDI buffer */ 876 tmp |= TRANS_DDI_FUNC_ENABLE; 877 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 878 } 879 880 /* wait for link ready */ 881 for_each_dsi_port(port, intel_dsi->ports) { 882 dsi_trans = dsi_port_to_transcoder(port); 883 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) & 884 LINK_READY), 2500)) 885 drm_err(&dev_priv->drm, "DSI link not ready\n"); 886 } 887 } 888 889 static void 890 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 891 const struct intel_crtc_state *crtc_state) 892 { 893 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 894 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 895 const struct drm_display_mode *adjusted_mode = 896 &crtc_state->hw.adjusted_mode; 897 enum port port; 898 enum transcoder dsi_trans; 899 /* horizontal timings */ 900 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 901 u16 hback_porch; 902 /* vertical timings */ 903 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 904 int mul = 1, div = 1; 905 906 /* 907 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 908 * for slower link speed if DSC is enabled. 909 * 910 * The compression frequency ratio is the ratio between compressed and 911 * non-compressed link speeds, and simplifies down to the ratio between 912 * compressed and non-compressed bpp. 913 */ 914 if (crtc_state->dsc.compression_enable) { 915 mul = crtc_state->dsc.compressed_bpp; 916 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 917 } 918 919 hactive = adjusted_mode->crtc_hdisplay; 920 921 if (is_vid_mode(intel_dsi)) 922 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 923 else 924 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 925 926 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 927 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 928 hsync_size = hsync_end - hsync_start; 929 hback_porch = (adjusted_mode->crtc_htotal - 930 adjusted_mode->crtc_hsync_end); 931 vactive = adjusted_mode->crtc_vdisplay; 932 933 if (is_vid_mode(intel_dsi)) { 934 vtotal = adjusted_mode->crtc_vtotal; 935 } else { 936 int bpp, line_time_us, byte_clk_period_ns; 937 938 if (crtc_state->dsc.compression_enable) 939 bpp = crtc_state->dsc.compressed_bpp; 940 else 941 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 942 943 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 944 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 945 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 946 } 947 vsync_start = adjusted_mode->crtc_vsync_start; 948 vsync_end = adjusted_mode->crtc_vsync_end; 949 vsync_shift = hsync_start - htotal / 2; 950 951 if (intel_dsi->dual_link) { 952 hactive /= 2; 953 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 954 hactive += intel_dsi->pixel_overlap; 955 htotal /= 2; 956 } 957 958 /* minimum hactive as per bspec: 256 pixels */ 959 if (adjusted_mode->crtc_hdisplay < 256) 960 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); 961 962 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 963 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 964 drm_err(&dev_priv->drm, 965 "hactive pixels are not multiple of 4\n"); 966 967 /* program TRANS_HTOTAL register */ 968 for_each_dsi_port(port, intel_dsi->ports) { 969 dsi_trans = dsi_port_to_transcoder(port); 970 intel_de_write(dev_priv, HTOTAL(dsi_trans), 971 (hactive - 1) | ((htotal - 1) << 16)); 972 } 973 974 /* TRANS_HSYNC register to be programmed only for video mode */ 975 if (is_vid_mode(intel_dsi)) { 976 if (intel_dsi->video_mode_format == 977 VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) { 978 /* BSPEC: hsync size should be atleast 16 pixels */ 979 if (hsync_size < 16) 980 drm_err(&dev_priv->drm, 981 "hsync size < 16 pixels\n"); 982 } 983 984 if (hback_porch < 16) 985 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); 986 987 if (intel_dsi->dual_link) { 988 hsync_start /= 2; 989 hsync_end /= 2; 990 } 991 992 for_each_dsi_port(port, intel_dsi->ports) { 993 dsi_trans = dsi_port_to_transcoder(port); 994 intel_de_write(dev_priv, HSYNC(dsi_trans), 995 (hsync_start - 1) | ((hsync_end - 1) << 16)); 996 } 997 } 998 999 /* program TRANS_VTOTAL register */ 1000 for_each_dsi_port(port, intel_dsi->ports) { 1001 dsi_trans = dsi_port_to_transcoder(port); 1002 /* 1003 * FIXME: Programing this by assuming progressive mode, since 1004 * non-interlaced info from VBT is not saved inside 1005 * struct drm_display_mode. 1006 * For interlace mode: program required pixel minus 2 1007 */ 1008 intel_de_write(dev_priv, VTOTAL(dsi_trans), 1009 (vactive - 1) | ((vtotal - 1) << 16)); 1010 } 1011 1012 if (vsync_end < vsync_start || vsync_end > vtotal) 1013 drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); 1014 1015 if (vsync_start < vactive) 1016 drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); 1017 1018 /* program TRANS_VSYNC register for video mode only */ 1019 if (is_vid_mode(intel_dsi)) { 1020 for_each_dsi_port(port, intel_dsi->ports) { 1021 dsi_trans = dsi_port_to_transcoder(port); 1022 intel_de_write(dev_priv, VSYNC(dsi_trans), 1023 (vsync_start - 1) | ((vsync_end - 1) << 16)); 1024 } 1025 } 1026 1027 /* 1028 * FIXME: It has to be programmed only for video modes and interlaced 1029 * modes. Put the check condition here once interlaced 1030 * info available as described above. 1031 * program TRANS_VSYNCSHIFT register 1032 */ 1033 if (is_vid_mode(intel_dsi)) { 1034 for_each_dsi_port(port, intel_dsi->ports) { 1035 dsi_trans = dsi_port_to_transcoder(port); 1036 intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans), 1037 vsync_shift); 1038 } 1039 } 1040 1041 /* program TRANS_VBLANK register, should be same as vtotal programmed */ 1042 if (DISPLAY_VER(dev_priv) >= 12) { 1043 for_each_dsi_port(port, intel_dsi->ports) { 1044 dsi_trans = dsi_port_to_transcoder(port); 1045 intel_de_write(dev_priv, VBLANK(dsi_trans), 1046 (vactive - 1) | ((vtotal - 1) << 16)); 1047 } 1048 } 1049 } 1050 1051 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1052 { 1053 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1054 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1055 enum port port; 1056 enum transcoder dsi_trans; 1057 u32 tmp; 1058 1059 for_each_dsi_port(port, intel_dsi->ports) { 1060 dsi_trans = dsi_port_to_transcoder(port); 1061 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1062 tmp |= PIPECONF_ENABLE; 1063 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1064 1065 /* wait for transcoder to be enabled */ 1066 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), 1067 I965_PIPECONF_ACTIVE, 10)) 1068 drm_err(&dev_priv->drm, 1069 "DSI transcoder not enabled\n"); 1070 } 1071 } 1072 1073 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1074 const struct intel_crtc_state *crtc_state) 1075 { 1076 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1077 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1078 enum port port; 1079 enum transcoder dsi_trans; 1080 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1081 1082 /* 1083 * escape clock count calculation: 1084 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1085 * UI (nsec) = (10^6)/Bitrate 1086 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1087 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1088 */ 1089 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1090 mul = 8 * 1000000; 1091 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1092 divisor); 1093 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1094 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1095 1096 for_each_dsi_port(port, intel_dsi->ports) { 1097 dsi_trans = dsi_port_to_transcoder(port); 1098 1099 /* program hst_tx_timeout */ 1100 tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans)); 1101 tmp &= ~HSTX_TIMEOUT_VALUE_MASK; 1102 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout); 1103 intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp); 1104 1105 /* FIXME: DSI_CALIB_TO */ 1106 1107 /* program lp_rx_host timeout */ 1108 tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans)); 1109 tmp &= ~LPRX_TIMEOUT_VALUE_MASK; 1110 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout); 1111 intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp); 1112 1113 /* FIXME: DSI_PWAIT_TO */ 1114 1115 /* program turn around timeout */ 1116 tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans)); 1117 tmp &= ~TA_TIMEOUT_VALUE_MASK; 1118 tmp |= TA_TIMEOUT_VALUE(ta_timeout); 1119 intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp); 1120 } 1121 } 1122 1123 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1124 bool enable) 1125 { 1126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1127 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1128 u32 tmp; 1129 1130 /* 1131 * used as TE i/p for DSI0, 1132 * for dual link/DSI1 TE is from slave DSI1 1133 * through GPIO. 1134 */ 1135 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1136 return; 1137 1138 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL); 1139 1140 if (enable) { 1141 tmp |= UTIL_PIN_DIRECTION_INPUT; 1142 tmp |= UTIL_PIN_ENABLE; 1143 } else { 1144 tmp &= ~UTIL_PIN_ENABLE; 1145 } 1146 intel_de_write(dev_priv, UTIL_PIN_CTL, tmp); 1147 } 1148 1149 static void 1150 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1151 const struct intel_crtc_state *crtc_state) 1152 { 1153 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1154 1155 /* step 4a: power up all lanes of the DDI used by DSI */ 1156 gen11_dsi_power_up_lanes(encoder); 1157 1158 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1159 gen11_dsi_config_phy_lanes_sequence(encoder); 1160 1161 /* step 4c: configure voltage swing and skew */ 1162 gen11_dsi_voltage_swing_program_seq(encoder); 1163 1164 /* enable DDI buffer */ 1165 gen11_dsi_enable_ddi_buffer(encoder); 1166 1167 /* setup D-PHY timings */ 1168 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1169 1170 /* Since transcoder is configured to take events from GPIO */ 1171 gen11_dsi_config_util_pin(encoder, true); 1172 1173 /* step 4h: setup DSI protocol timeouts */ 1174 gen11_dsi_setup_timeouts(encoder, crtc_state); 1175 1176 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1177 gen11_dsi_configure_transcoder(encoder, crtc_state); 1178 1179 /* Step 4l: Gate DDI clocks */ 1180 if (DISPLAY_VER(dev_priv) == 11) 1181 gen11_dsi_gate_clocks(encoder); 1182 } 1183 1184 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1185 { 1186 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1187 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1188 struct mipi_dsi_device *dsi; 1189 enum port port; 1190 enum transcoder dsi_trans; 1191 u32 tmp; 1192 int ret; 1193 1194 /* set maximum return packet size */ 1195 for_each_dsi_port(port, intel_dsi->ports) { 1196 dsi_trans = dsi_port_to_transcoder(port); 1197 1198 /* 1199 * FIXME: This uses the number of DW's currently in the payload 1200 * receive queue. This is probably not what we want here. 1201 */ 1202 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans)); 1203 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1204 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1205 tmp = tmp * 4; 1206 dsi = intel_dsi->dsi_hosts[port]->device; 1207 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1208 if (ret < 0) 1209 drm_err(&dev_priv->drm, 1210 "error setting max return pkt size%d\n", tmp); 1211 } 1212 1213 /* panel power on related mipi dsi vbt sequences */ 1214 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1215 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 1216 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1217 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1218 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1219 1220 /* ensure all panel commands dispatched before enabling transcoder */ 1221 wait_for_cmds_dispatched_to_panel(encoder); 1222 } 1223 1224 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1225 struct intel_encoder *encoder, 1226 const struct intel_crtc_state *crtc_state, 1227 const struct drm_connector_state *conn_state) 1228 { 1229 /* step2: enable IO power */ 1230 gen11_dsi_enable_io_power(encoder); 1231 1232 /* step3: enable DSI PLL */ 1233 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1234 } 1235 1236 static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1237 struct intel_encoder *encoder, 1238 const struct intel_crtc_state *pipe_config, 1239 const struct drm_connector_state *conn_state) 1240 { 1241 /* step3b */ 1242 gen11_dsi_map_pll(encoder, pipe_config); 1243 1244 /* step4: enable DSI port and DPHY */ 1245 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1246 1247 /* step5: program and powerup panel */ 1248 gen11_dsi_powerup_panel(encoder); 1249 1250 intel_dsc_enable(encoder, pipe_config); 1251 1252 /* step6c: configure transcoder timings */ 1253 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1254 } 1255 1256 static void gen11_dsi_enable(struct intel_atomic_state *state, 1257 struct intel_encoder *encoder, 1258 const struct intel_crtc_state *crtc_state, 1259 const struct drm_connector_state *conn_state) 1260 { 1261 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1262 1263 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 1264 1265 /* step6d: enable dsi transcoder */ 1266 gen11_dsi_enable_transcoder(encoder); 1267 1268 /* step7: enable backlight */ 1269 intel_panel_enable_backlight(crtc_state, conn_state); 1270 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1271 1272 intel_crtc_vblank_on(crtc_state); 1273 } 1274 1275 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1276 { 1277 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1278 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1279 enum port port; 1280 enum transcoder dsi_trans; 1281 u32 tmp; 1282 1283 for_each_dsi_port(port, intel_dsi->ports) { 1284 dsi_trans = dsi_port_to_transcoder(port); 1285 1286 /* disable transcoder */ 1287 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1288 tmp &= ~PIPECONF_ENABLE; 1289 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1290 1291 /* wait for transcoder to be disabled */ 1292 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), 1293 I965_PIPECONF_ACTIVE, 50)) 1294 drm_err(&dev_priv->drm, 1295 "DSI trancoder not disabled\n"); 1296 } 1297 } 1298 1299 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1300 { 1301 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1302 1303 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1304 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1305 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1306 1307 /* ensure cmds dispatched to panel */ 1308 wait_for_cmds_dispatched_to_panel(encoder); 1309 } 1310 1311 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1312 { 1313 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1314 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1315 enum port port; 1316 enum transcoder dsi_trans; 1317 u32 tmp; 1318 1319 /* disable periodic update mode */ 1320 if (is_cmd_mode(intel_dsi)) { 1321 for_each_dsi_port(port, intel_dsi->ports) { 1322 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 1323 tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE; 1324 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 1325 } 1326 } 1327 1328 /* put dsi link in ULPS */ 1329 for_each_dsi_port(port, intel_dsi->ports) { 1330 dsi_trans = dsi_port_to_transcoder(port); 1331 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)); 1332 tmp |= LINK_ENTER_ULPS; 1333 tmp &= ~LINK_ULPS_TYPE_LP11; 1334 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp); 1335 1336 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 1337 LINK_IN_ULPS), 1338 10)) 1339 drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); 1340 } 1341 1342 /* disable ddi function */ 1343 for_each_dsi_port(port, intel_dsi->ports) { 1344 dsi_trans = dsi_port_to_transcoder(port); 1345 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1346 tmp &= ~TRANS_DDI_FUNC_ENABLE; 1347 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 1348 } 1349 1350 /* disable port sync mode if dual link */ 1351 if (intel_dsi->dual_link) { 1352 for_each_dsi_port(port, intel_dsi->ports) { 1353 dsi_trans = dsi_port_to_transcoder(port); 1354 tmp = intel_de_read(dev_priv, 1355 TRANS_DDI_FUNC_CTL2(dsi_trans)); 1356 tmp &= ~PORT_SYNC_MODE_ENABLE; 1357 intel_de_write(dev_priv, 1358 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 1359 } 1360 } 1361 } 1362 1363 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1364 { 1365 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1366 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1367 u32 tmp; 1368 enum port port; 1369 1370 gen11_dsi_ungate_clocks(encoder); 1371 for_each_dsi_port(port, intel_dsi->ports) { 1372 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1373 tmp &= ~DDI_BUF_CTL_ENABLE; 1374 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 1375 1376 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1377 DDI_BUF_IS_IDLE), 1378 8)) 1379 drm_err(&dev_priv->drm, 1380 "DDI port:%c buffer not idle\n", 1381 port_name(port)); 1382 } 1383 gen11_dsi_gate_clocks(encoder); 1384 } 1385 1386 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1387 { 1388 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1389 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1390 enum port port; 1391 u32 tmp; 1392 1393 for_each_dsi_port(port, intel_dsi->ports) { 1394 intel_wakeref_t wakeref; 1395 1396 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1397 intel_display_power_put(dev_priv, 1398 port == PORT_A ? 1399 POWER_DOMAIN_PORT_DDI_A_IO : 1400 POWER_DOMAIN_PORT_DDI_B_IO, 1401 wakeref); 1402 } 1403 1404 /* set mode to DDI */ 1405 for_each_dsi_port(port, intel_dsi->ports) { 1406 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 1407 tmp &= ~COMBO_PHY_MODE_DSI; 1408 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 1409 } 1410 } 1411 1412 static void gen11_dsi_disable(struct intel_atomic_state *state, 1413 struct intel_encoder *encoder, 1414 const struct intel_crtc_state *old_crtc_state, 1415 const struct drm_connector_state *old_conn_state) 1416 { 1417 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1418 1419 /* step1: turn off backlight */ 1420 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1421 intel_panel_disable_backlight(old_conn_state); 1422 1423 /* step2d,e: disable transcoder and wait */ 1424 gen11_dsi_disable_transcoder(encoder); 1425 1426 /* step2f,g: powerdown panel */ 1427 gen11_dsi_powerdown_panel(encoder); 1428 1429 /* step2h,i,j: deconfig trancoder */ 1430 gen11_dsi_deconfigure_trancoder(encoder); 1431 1432 /* step3: disable port */ 1433 gen11_dsi_disable_port(encoder); 1434 1435 gen11_dsi_config_util_pin(encoder, false); 1436 1437 /* step4: disable IO power */ 1438 gen11_dsi_disable_io_power(encoder); 1439 } 1440 1441 static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1442 struct intel_encoder *encoder, 1443 const struct intel_crtc_state *old_crtc_state, 1444 const struct drm_connector_state *old_conn_state) 1445 { 1446 intel_crtc_vblank_off(old_crtc_state); 1447 1448 intel_dsc_disable(old_crtc_state); 1449 1450 skl_scaler_disable(old_crtc_state); 1451 } 1452 1453 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1454 struct drm_display_mode *mode) 1455 { 1456 /* FIXME: DSC? */ 1457 return intel_dsi_mode_valid(connector, mode); 1458 } 1459 1460 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1461 struct intel_crtc_state *pipe_config) 1462 { 1463 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1464 struct drm_display_mode *adjusted_mode = 1465 &pipe_config->hw.adjusted_mode; 1466 1467 if (pipe_config->dsc.compressed_bpp) { 1468 int div = pipe_config->dsc.compressed_bpp; 1469 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1470 1471 adjusted_mode->crtc_htotal = 1472 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1473 adjusted_mode->crtc_hsync_start = 1474 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1475 adjusted_mode->crtc_hsync_end = 1476 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1477 } 1478 1479 if (intel_dsi->dual_link) { 1480 adjusted_mode->crtc_hdisplay *= 2; 1481 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1482 adjusted_mode->crtc_hdisplay -= 1483 intel_dsi->pixel_overlap; 1484 adjusted_mode->crtc_htotal *= 2; 1485 } 1486 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1487 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1488 1489 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1490 if (intel_dsi->dual_link) { 1491 adjusted_mode->crtc_hsync_start *= 2; 1492 adjusted_mode->crtc_hsync_end *= 2; 1493 } 1494 } 1495 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1496 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1497 } 1498 1499 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1500 { 1501 struct drm_device *dev = intel_dsi->base.base.dev; 1502 struct drm_i915_private *dev_priv = to_i915(dev); 1503 enum transcoder dsi_trans; 1504 u32 val; 1505 1506 if (intel_dsi->ports == BIT(PORT_B)) 1507 dsi_trans = TRANSCODER_DSI_1; 1508 else 1509 dsi_trans = TRANSCODER_DSI_0; 1510 1511 val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 1512 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1513 } 1514 1515 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1516 struct intel_crtc_state *pipe_config) 1517 { 1518 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1519 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1520 I915_MODE_FLAG_DSI_USE_TE0; 1521 else if (intel_dsi->ports == BIT(PORT_B)) 1522 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1523 else 1524 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1525 } 1526 1527 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1528 struct intel_crtc_state *pipe_config) 1529 { 1530 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1531 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1532 1533 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1534 1535 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1536 if (intel_dsi->dual_link) 1537 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1538 1539 gen11_dsi_get_timings(encoder, pipe_config); 1540 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1541 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1542 1543 /* Get the details on which TE should be enabled */ 1544 if (is_cmd_mode(intel_dsi)) 1545 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1546 1547 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1548 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1549 } 1550 1551 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1552 struct intel_crtc_state *crtc_state) 1553 { 1554 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1555 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1556 int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10; 1557 bool use_dsc; 1558 int ret; 1559 1560 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1561 if (!use_dsc) 1562 return 0; 1563 1564 if (crtc_state->pipe_bpp < 8 * 3) 1565 return -EINVAL; 1566 1567 /* FIXME: split only when necessary */ 1568 if (crtc_state->dsc.slice_count > 1) 1569 crtc_state->dsc.dsc_split = true; 1570 1571 vdsc_cfg->convert_rgb = true; 1572 1573 /* FIXME: initialize from VBT */ 1574 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1575 1576 ret = intel_dsc_compute_params(encoder, crtc_state); 1577 if (ret) 1578 return ret; 1579 1580 /* DSI specific sanity checks on the common code */ 1581 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); 1582 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); 1583 drm_WARN_ON(&dev_priv->drm, 1584 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1585 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); 1586 drm_WARN_ON(&dev_priv->drm, 1587 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1588 1589 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1590 if (ret) 1591 return ret; 1592 1593 crtc_state->dsc.compression_enable = true; 1594 1595 return 0; 1596 } 1597 1598 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1599 struct intel_crtc_state *pipe_config, 1600 struct drm_connector_state *conn_state) 1601 { 1602 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1603 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 1604 base); 1605 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1606 const struct drm_display_mode *fixed_mode = 1607 intel_connector->panel.fixed_mode; 1608 struct drm_display_mode *adjusted_mode = 1609 &pipe_config->hw.adjusted_mode; 1610 int ret; 1611 1612 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1613 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 1614 1615 ret = intel_pch_panel_fitting(pipe_config, conn_state); 1616 if (ret) 1617 return ret; 1618 1619 adjusted_mode->flags = 0; 1620 1621 /* Dual link goes to trancoder DSI'0' */ 1622 if (intel_dsi->ports == BIT(PORT_B)) 1623 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1624 else 1625 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1626 1627 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1628 pipe_config->pipe_bpp = 24; 1629 else 1630 pipe_config->pipe_bpp = 18; 1631 1632 pipe_config->clock_set = true; 1633 1634 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1635 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n"); 1636 1637 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1638 1639 /* 1640 * In case of TE GATE cmd mode, we 1641 * receive TE from the slave if 1642 * dual link is enabled 1643 */ 1644 if (is_cmd_mode(intel_dsi)) 1645 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1646 1647 return 0; 1648 } 1649 1650 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1651 struct intel_crtc_state *crtc_state) 1652 { 1653 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1654 1655 get_dsi_io_power_domains(i915, 1656 enc_to_intel_dsi(encoder)); 1657 } 1658 1659 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1660 enum pipe *pipe) 1661 { 1662 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1663 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1664 enum transcoder dsi_trans; 1665 intel_wakeref_t wakeref; 1666 enum port port; 1667 bool ret = false; 1668 u32 tmp; 1669 1670 wakeref = intel_display_power_get_if_enabled(dev_priv, 1671 encoder->power_domain); 1672 if (!wakeref) 1673 return false; 1674 1675 for_each_dsi_port(port, intel_dsi->ports) { 1676 dsi_trans = dsi_port_to_transcoder(port); 1677 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1678 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1679 case TRANS_DDI_EDP_INPUT_A_ON: 1680 *pipe = PIPE_A; 1681 break; 1682 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1683 *pipe = PIPE_B; 1684 break; 1685 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1686 *pipe = PIPE_C; 1687 break; 1688 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1689 *pipe = PIPE_D; 1690 break; 1691 default: 1692 drm_err(&dev_priv->drm, "Invalid PIPE input\n"); 1693 goto out; 1694 } 1695 1696 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1697 ret = tmp & PIPECONF_ENABLE; 1698 } 1699 out: 1700 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1701 return ret; 1702 } 1703 1704 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1705 struct intel_crtc_state *crtc_state) 1706 { 1707 if (crtc_state->dsc.compression_enable) { 1708 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1709 crtc_state->uapi.mode_changed = true; 1710 1711 return false; 1712 } 1713 1714 return true; 1715 } 1716 1717 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1718 { 1719 intel_encoder_destroy(encoder); 1720 } 1721 1722 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1723 .destroy = gen11_dsi_encoder_destroy, 1724 }; 1725 1726 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1727 .detect = intel_panel_detect, 1728 .late_register = intel_connector_register, 1729 .early_unregister = intel_connector_unregister, 1730 .destroy = intel_connector_destroy, 1731 .fill_modes = drm_helper_probe_single_connector_modes, 1732 .atomic_get_property = intel_digital_connector_atomic_get_property, 1733 .atomic_set_property = intel_digital_connector_atomic_set_property, 1734 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1735 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1736 }; 1737 1738 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1739 .get_modes = intel_dsi_get_modes, 1740 .mode_valid = gen11_dsi_mode_valid, 1741 .atomic_check = intel_digital_connector_atomic_check, 1742 }; 1743 1744 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1745 struct mipi_dsi_device *dsi) 1746 { 1747 return 0; 1748 } 1749 1750 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1751 struct mipi_dsi_device *dsi) 1752 { 1753 return 0; 1754 } 1755 1756 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1757 const struct mipi_dsi_msg *msg) 1758 { 1759 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1760 struct mipi_dsi_packet dsi_pkt; 1761 ssize_t ret; 1762 bool enable_lpdt = false; 1763 1764 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1765 if (ret < 0) 1766 return ret; 1767 1768 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1769 enable_lpdt = true; 1770 1771 /* send packet header */ 1772 ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt); 1773 if (ret < 0) 1774 return ret; 1775 1776 /* only long packet contains payload */ 1777 if (mipi_dsi_packet_format_is_long(msg->type)) { 1778 ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt); 1779 if (ret < 0) 1780 return ret; 1781 } 1782 1783 //TODO: add payload receive code if needed 1784 1785 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1786 1787 return ret; 1788 } 1789 1790 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1791 .attach = gen11_dsi_host_attach, 1792 .detach = gen11_dsi_host_detach, 1793 .transfer = gen11_dsi_host_transfer, 1794 }; 1795 1796 #define ICL_PREPARE_CNT_MAX 0x7 1797 #define ICL_CLK_ZERO_CNT_MAX 0xf 1798 #define ICL_TRAIL_CNT_MAX 0x7 1799 #define ICL_TCLK_PRE_CNT_MAX 0x3 1800 #define ICL_TCLK_POST_CNT_MAX 0x7 1801 #define ICL_HS_ZERO_CNT_MAX 0xf 1802 #define ICL_EXIT_ZERO_CNT_MAX 0x7 1803 1804 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1805 { 1806 struct drm_device *dev = intel_dsi->base.base.dev; 1807 struct drm_i915_private *dev_priv = to_i915(dev); 1808 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 1809 u32 tlpx_ns; 1810 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1811 u32 ths_prepare_ns, tclk_trail_ns; 1812 u32 hs_zero_cnt; 1813 u32 tclk_pre_cnt, tclk_post_cnt; 1814 1815 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1816 1817 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1818 ths_prepare_ns = max(mipi_config->ths_prepare, 1819 mipi_config->tclk_prepare); 1820 1821 /* 1822 * prepare cnt in escape clocks 1823 * this field represents a hexadecimal value with a precision 1824 * of 1.2 – i.e. the most significant bit is the integer 1825 * and the least significant 2 bits are fraction bits. 1826 * so, the field can represent a range of 0.25 to 1.75 1827 */ 1828 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1829 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1830 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", 1831 prepare_cnt); 1832 prepare_cnt = ICL_PREPARE_CNT_MAX; 1833 } 1834 1835 /* clk zero count in escape clocks */ 1836 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1837 ths_prepare_ns, tlpx_ns); 1838 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1839 drm_dbg_kms(&dev_priv->drm, 1840 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1841 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1842 } 1843 1844 /* trail cnt in escape clocks*/ 1845 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1846 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1847 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", 1848 trail_cnt); 1849 trail_cnt = ICL_TRAIL_CNT_MAX; 1850 } 1851 1852 /* tclk pre count in escape clocks */ 1853 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1854 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1855 drm_dbg_kms(&dev_priv->drm, 1856 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1857 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1858 } 1859 1860 /* tclk post count in escape clocks */ 1861 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); 1862 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { 1863 drm_dbg_kms(&dev_priv->drm, 1864 "tclk_post_cnt out of range (%d)\n", 1865 tclk_post_cnt); 1866 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; 1867 } 1868 1869 /* hs zero cnt in escape clocks */ 1870 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1871 ths_prepare_ns, tlpx_ns); 1872 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1873 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", 1874 hs_zero_cnt); 1875 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1876 } 1877 1878 /* hs exit zero cnt in escape clocks */ 1879 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1880 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1881 drm_dbg_kms(&dev_priv->drm, 1882 "exit_zero_cnt out of range (%d)\n", 1883 exit_zero_cnt); 1884 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1885 } 1886 1887 /* clock lane dphy timings */ 1888 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1889 CLK_PREPARE(prepare_cnt) | 1890 CLK_ZERO_OVERRIDE | 1891 CLK_ZERO(clk_zero_cnt) | 1892 CLK_PRE_OVERRIDE | 1893 CLK_PRE(tclk_pre_cnt) | 1894 CLK_POST_OVERRIDE | 1895 CLK_POST(tclk_post_cnt) | 1896 CLK_TRAIL_OVERRIDE | 1897 CLK_TRAIL(trail_cnt)); 1898 1899 /* data lanes dphy timings */ 1900 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1901 HS_PREPARE(prepare_cnt) | 1902 HS_ZERO_OVERRIDE | 1903 HS_ZERO(hs_zero_cnt) | 1904 HS_TRAIL_OVERRIDE | 1905 HS_TRAIL(trail_cnt) | 1906 HS_EXIT_OVERRIDE | 1907 HS_EXIT(exit_zero_cnt)); 1908 1909 intel_dsi_log_params(intel_dsi); 1910 } 1911 1912 static void icl_dsi_add_properties(struct intel_connector *connector) 1913 { 1914 u32 allowed_scalers; 1915 1916 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | 1917 BIT(DRM_MODE_SCALE_FULLSCREEN) | 1918 BIT(DRM_MODE_SCALE_CENTER); 1919 1920 drm_connector_attach_scaling_mode_property(&connector->base, 1921 allowed_scalers); 1922 1923 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1924 1925 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1926 intel_dsi_get_panel_orientation(connector), 1927 connector->panel.fixed_mode->hdisplay, 1928 connector->panel.fixed_mode->vdisplay); 1929 } 1930 1931 void icl_dsi_init(struct drm_i915_private *dev_priv) 1932 { 1933 struct drm_device *dev = &dev_priv->drm; 1934 struct intel_dsi *intel_dsi; 1935 struct intel_encoder *encoder; 1936 struct intel_connector *intel_connector; 1937 struct drm_connector *connector; 1938 struct drm_display_mode *fixed_mode; 1939 enum port port; 1940 1941 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1942 return; 1943 1944 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1945 if (!intel_dsi) 1946 return; 1947 1948 intel_connector = intel_connector_alloc(); 1949 if (!intel_connector) { 1950 kfree(intel_dsi); 1951 return; 1952 } 1953 1954 encoder = &intel_dsi->base; 1955 intel_dsi->attached_connector = intel_connector; 1956 connector = &intel_connector->base; 1957 1958 /* register DSI encoder with DRM subsystem */ 1959 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs, 1960 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 1961 1962 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 1963 encoder->pre_enable = gen11_dsi_pre_enable; 1964 encoder->enable = gen11_dsi_enable; 1965 encoder->disable = gen11_dsi_disable; 1966 encoder->post_disable = gen11_dsi_post_disable; 1967 encoder->port = port; 1968 encoder->get_config = gen11_dsi_get_config; 1969 encoder->update_pipe = intel_panel_update_backlight; 1970 encoder->compute_config = gen11_dsi_compute_config; 1971 encoder->get_hw_state = gen11_dsi_get_hw_state; 1972 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 1973 encoder->type = INTEL_OUTPUT_DSI; 1974 encoder->cloneable = 0; 1975 encoder->pipe_mask = ~0; 1976 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1977 encoder->get_power_domains = gen11_dsi_get_power_domains; 1978 encoder->disable_clock = gen11_dsi_gate_clocks; 1979 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 1980 1981 /* register DSI connector with DRM subsystem */ 1982 drm_connector_init(dev, connector, &gen11_dsi_connector_funcs, 1983 DRM_MODE_CONNECTOR_DSI); 1984 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 1985 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1986 connector->interlace_allowed = false; 1987 connector->doublescan_allowed = false; 1988 intel_connector->get_hw_state = intel_connector_get_hw_state; 1989 1990 /* attach connector to encoder */ 1991 intel_connector_attach_encoder(intel_connector, encoder); 1992 1993 mutex_lock(&dev->mode_config.mutex); 1994 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 1995 mutex_unlock(&dev->mode_config.mutex); 1996 1997 if (!fixed_mode) { 1998 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); 1999 goto err; 2000 } 2001 2002 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 2003 intel_panel_setup_backlight(connector, INVALID_PIPE); 2004 2005 if (dev_priv->vbt.dsi.config->dual_link) 2006 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 2007 else 2008 intel_dsi->ports = BIT(port); 2009 2010 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; 2011 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; 2012 2013 for_each_dsi_port(port, intel_dsi->ports) { 2014 struct intel_dsi_host *host; 2015 2016 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2017 if (!host) 2018 goto err; 2019 2020 intel_dsi->dsi_hosts[port] = host; 2021 } 2022 2023 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2024 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 2025 goto err; 2026 } 2027 2028 icl_dphy_param_init(intel_dsi); 2029 2030 icl_dsi_add_properties(intel_connector); 2031 return; 2032 2033 err: 2034 drm_connector_cleanup(connector); 2035 drm_encoder_cleanup(&encoder->base); 2036 kfree(intel_dsi); 2037 kfree(intel_connector); 2038 } 2039