1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_mipi_dsi.h> 30 31 #include "intel_atomic.h" 32 #include "intel_backlight.h" 33 #include "intel_combo_phy.h" 34 #include "intel_connector.h" 35 #include "intel_crtc.h" 36 #include "intel_ddi.h" 37 #include "intel_de.h" 38 #include "intel_dsi.h" 39 #include "intel_panel.h" 40 #include "intel_vdsc.h" 41 #include "skl_scaler.h" 42 #include "skl_universal_plane.h" 43 44 static int header_credits_available(struct drm_i915_private *dev_priv, 45 enum transcoder dsi_trans) 46 { 47 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 48 >> FREE_HEADER_CREDIT_SHIFT; 49 } 50 51 static int payload_credits_available(struct drm_i915_private *dev_priv, 52 enum transcoder dsi_trans) 53 { 54 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 55 >> FREE_PLOAD_CREDIT_SHIFT; 56 } 57 58 static bool wait_for_header_credits(struct drm_i915_private *dev_priv, 59 enum transcoder dsi_trans, int hdr_credit) 60 { 61 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= 62 hdr_credit, 100)) { 63 drm_err(&dev_priv->drm, "DSI header credits not released\n"); 64 return false; 65 } 66 67 return true; 68 } 69 70 static bool wait_for_payload_credits(struct drm_i915_private *dev_priv, 71 enum transcoder dsi_trans, int payld_credit) 72 { 73 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= 74 payld_credit, 100)) { 75 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); 76 return false; 77 } 78 79 return true; 80 } 81 82 static enum transcoder dsi_port_to_transcoder(enum port port) 83 { 84 if (port == PORT_A) 85 return TRANSCODER_DSI_0; 86 else 87 return TRANSCODER_DSI_1; 88 } 89 90 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 91 { 92 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 93 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 94 struct mipi_dsi_device *dsi; 95 enum port port; 96 enum transcoder dsi_trans; 97 int ret; 98 99 /* wait for header/payload credits to be released */ 100 for_each_dsi_port(port, intel_dsi->ports) { 101 dsi_trans = dsi_port_to_transcoder(port); 102 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 103 wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT); 104 } 105 106 /* send nop DCS command */ 107 for_each_dsi_port(port, intel_dsi->ports) { 108 dsi = intel_dsi->dsi_hosts[port]->device; 109 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 110 dsi->channel = 0; 111 ret = mipi_dsi_dcs_nop(dsi); 112 if (ret < 0) 113 drm_err(&dev_priv->drm, 114 "error sending DCS NOP command\n"); 115 } 116 117 /* wait for header credits to be released */ 118 for_each_dsi_port(port, intel_dsi->ports) { 119 dsi_trans = dsi_port_to_transcoder(port); 120 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 121 } 122 123 /* wait for LP TX in progress bit to be cleared */ 124 for_each_dsi_port(port, intel_dsi->ports) { 125 dsi_trans = dsi_port_to_transcoder(port); 126 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 127 LPTX_IN_PROGRESS), 20)) 128 drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); 129 } 130 } 131 132 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 133 const struct mipi_dsi_packet *packet) 134 { 135 struct intel_dsi *intel_dsi = host->intel_dsi; 136 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 137 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 138 const u8 *data = packet->payload; 139 u32 len = packet->payload_length; 140 int i, j; 141 142 /* payload queue can accept *256 bytes*, check limit */ 143 if (len > MAX_PLOAD_CREDIT * 4) { 144 drm_err(&i915->drm, "payload size exceeds max queue limit\n"); 145 return -EINVAL; 146 } 147 148 for (i = 0; i < len; i += 4) { 149 u32 tmp = 0; 150 151 if (!wait_for_payload_credits(i915, dsi_trans, 1)) 152 return -EBUSY; 153 154 for (j = 0; j < min_t(u32, len - i, 4); j++) 155 tmp |= *data++ << 8 * j; 156 157 intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp); 158 } 159 160 return 0; 161 } 162 163 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 164 const struct mipi_dsi_packet *packet, 165 bool enable_lpdt) 166 { 167 struct intel_dsi *intel_dsi = host->intel_dsi; 168 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 169 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 170 u32 tmp; 171 172 if (!wait_for_header_credits(dev_priv, dsi_trans, 1)) 173 return -EBUSY; 174 175 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); 176 177 if (packet->payload) 178 tmp |= PAYLOAD_PRESENT; 179 else 180 tmp &= ~PAYLOAD_PRESENT; 181 182 tmp &= ~VBLANK_FENCE; 183 184 if (enable_lpdt) 185 tmp |= LP_DATA_TRANSFER; 186 187 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 188 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); 189 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); 190 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); 191 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); 192 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); 193 194 return 0; 195 } 196 197 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 198 { 199 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 200 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 201 u32 tmp, mode_flags; 202 enum port port; 203 204 mode_flags = crtc_state->mode_flags; 205 206 /* 207 * case 1 also covers dual link 208 * In case of dual link, frame update should be set on 209 * DSI_0 210 */ 211 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 212 port = PORT_A; 213 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 214 port = PORT_B; 215 else 216 return; 217 218 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 219 tmp |= DSI_FRAME_UPDATE_REQUEST; 220 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 221 } 222 223 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 224 { 225 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 226 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 227 enum phy phy; 228 u32 tmp; 229 int lane; 230 231 for_each_dsi_phy(phy, intel_dsi->phys) { 232 /* 233 * Program voltage swing and pre-emphasis level values as per 234 * table in BSPEC under DDI buffer programing 235 */ 236 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 237 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 238 tmp |= SCALING_MODE_SEL(0x2); 239 tmp |= TAP2_DISABLE | TAP3_DISABLE; 240 tmp |= RTERM_SELECT(0x6); 241 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 242 243 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 244 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 245 tmp |= SCALING_MODE_SEL(0x2); 246 tmp |= TAP2_DISABLE | TAP3_DISABLE; 247 tmp |= RTERM_SELECT(0x6); 248 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 249 250 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 251 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 252 RCOMP_SCALAR_MASK); 253 tmp |= SWING_SEL_UPPER(0x2); 254 tmp |= SWING_SEL_LOWER(0x2); 255 tmp |= RCOMP_SCALAR(0x98); 256 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 257 258 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 259 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 260 RCOMP_SCALAR_MASK); 261 tmp |= SWING_SEL_UPPER(0x2); 262 tmp |= SWING_SEL_LOWER(0x2); 263 tmp |= RCOMP_SCALAR(0x98); 264 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 265 266 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 267 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 268 CURSOR_COEFF_MASK); 269 tmp |= POST_CURSOR_1(0x0); 270 tmp |= POST_CURSOR_2(0x0); 271 tmp |= CURSOR_COEFF(0x3f); 272 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 273 274 for (lane = 0; lane <= 3; lane++) { 275 /* Bspec: must not use GRP register for write */ 276 tmp = intel_de_read(dev_priv, 277 ICL_PORT_TX_DW4_LN(lane, phy)); 278 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 279 CURSOR_COEFF_MASK); 280 tmp |= POST_CURSOR_1(0x0); 281 tmp |= POST_CURSOR_2(0x0); 282 tmp |= CURSOR_COEFF(0x3f); 283 intel_de_write(dev_priv, 284 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 285 } 286 } 287 } 288 289 static void configure_dual_link_mode(struct intel_encoder *encoder, 290 const struct intel_crtc_state *pipe_config) 291 { 292 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 293 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 294 u32 dss_ctl1; 295 296 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); 297 dss_ctl1 |= SPLITTER_ENABLE; 298 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 299 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 300 301 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 302 const struct drm_display_mode *adjusted_mode = 303 &pipe_config->hw.adjusted_mode; 304 u32 dss_ctl2; 305 u16 hactive = adjusted_mode->crtc_hdisplay; 306 u16 dl_buffer_depth; 307 308 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 309 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 310 311 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 312 drm_err(&dev_priv->drm, 313 "DL buffer depth exceed max value\n"); 314 315 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 316 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 317 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); 318 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; 319 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 320 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); 321 } else { 322 /* Interleave */ 323 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 324 } 325 326 intel_de_write(dev_priv, DSS_CTL1, dss_ctl1); 327 } 328 329 /* aka DSI 8X clock */ 330 static int afe_clk(struct intel_encoder *encoder, 331 const struct intel_crtc_state *crtc_state) 332 { 333 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 334 int bpp; 335 336 if (crtc_state->dsc.compression_enable) 337 bpp = crtc_state->dsc.compressed_bpp; 338 else 339 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 340 341 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 342 } 343 344 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 345 const struct intel_crtc_state *crtc_state) 346 { 347 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 348 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 349 enum port port; 350 int afe_clk_khz; 351 int theo_word_clk, act_word_clk; 352 u32 esc_clk_div_m, esc_clk_div_m_phy; 353 354 afe_clk_khz = afe_clk(encoder, crtc_state); 355 356 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 357 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 358 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 359 esc_clk_div_m = act_word_clk * 8; 360 esc_clk_div_m_phy = (act_word_clk - 1) / 2; 361 } else { 362 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 363 } 364 365 for_each_dsi_port(port, intel_dsi->ports) { 366 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), 367 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 368 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); 369 } 370 371 for_each_dsi_port(port, intel_dsi->ports) { 372 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port), 373 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 374 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); 375 } 376 377 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 378 for_each_dsi_port(port, intel_dsi->ports) { 379 intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8), 380 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); 381 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8)); 382 } 383 } 384 } 385 386 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, 387 struct intel_dsi *intel_dsi) 388 { 389 enum port port; 390 391 for_each_dsi_port(port, intel_dsi->ports) { 392 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); 393 intel_dsi->io_wakeref[port] = 394 intel_display_power_get(dev_priv, 395 port == PORT_A ? 396 POWER_DOMAIN_PORT_DDI_A_IO : 397 POWER_DOMAIN_PORT_DDI_B_IO); 398 } 399 } 400 401 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 402 { 403 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 404 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 405 enum port port; 406 u32 tmp; 407 408 for_each_dsi_port(port, intel_dsi->ports) { 409 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 410 tmp |= COMBO_PHY_MODE_DSI; 411 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 412 } 413 414 get_dsi_io_power_domains(dev_priv, intel_dsi); 415 } 416 417 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 418 { 419 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 420 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 421 enum phy phy; 422 423 for_each_dsi_phy(phy, intel_dsi->phys) 424 intel_combo_phy_power_up_lanes(dev_priv, phy, true, 425 intel_dsi->lane_count, false); 426 } 427 428 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 429 { 430 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 431 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 432 enum phy phy; 433 u32 tmp; 434 int lane; 435 436 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 437 for_each_dsi_phy(phy, intel_dsi->phys) { 438 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 439 tmp &= ~LOADGEN_SELECT; 440 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 441 for (lane = 0; lane <= 3; lane++) { 442 tmp = intel_de_read(dev_priv, 443 ICL_PORT_TX_DW4_LN(lane, phy)); 444 tmp &= ~LOADGEN_SELECT; 445 if (lane != 2) 446 tmp |= LOADGEN_SELECT; 447 intel_de_write(dev_priv, 448 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 449 } 450 } 451 452 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 453 for_each_dsi_phy(phy, intel_dsi->phys) { 454 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 455 tmp &= ~FRC_LATENCY_OPTIM_MASK; 456 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 457 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 458 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 459 tmp &= ~FRC_LATENCY_OPTIM_MASK; 460 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 461 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 462 463 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 464 if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) { 465 tmp = intel_de_read(dev_priv, 466 ICL_PORT_PCS_DW1_AUX(phy)); 467 tmp &= ~LATENCY_OPTIM_MASK; 468 tmp |= LATENCY_OPTIM_VAL(0); 469 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), 470 tmp); 471 472 tmp = intel_de_read(dev_priv, 473 ICL_PORT_PCS_DW1_LN(0, phy)); 474 tmp &= ~LATENCY_OPTIM_MASK; 475 tmp |= LATENCY_OPTIM_VAL(0x1); 476 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), 477 tmp); 478 } 479 } 480 481 } 482 483 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 484 { 485 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 486 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 487 u32 tmp; 488 enum phy phy; 489 490 /* clear common keeper enable bit */ 491 for_each_dsi_phy(phy, intel_dsi->phys) { 492 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 493 tmp &= ~COMMON_KEEPER_EN; 494 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp); 495 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy)); 496 tmp &= ~COMMON_KEEPER_EN; 497 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp); 498 } 499 500 /* 501 * Set SUS Clock Config bitfield to 11b 502 * Note: loadgen select program is done 503 * as part of lane phy sequence configuration 504 */ 505 for_each_dsi_phy(phy, intel_dsi->phys) { 506 tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 507 tmp |= SUS_CLOCK_CONFIG; 508 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp); 509 } 510 511 /* Clear training enable to change swing values */ 512 for_each_dsi_phy(phy, intel_dsi->phys) { 513 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 514 tmp &= ~TX_TRAINING_EN; 515 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 516 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 517 tmp &= ~TX_TRAINING_EN; 518 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 519 } 520 521 /* Program swing and de-emphasis */ 522 dsi_program_swing_and_deemphasis(encoder); 523 524 /* Set training enable to trigger update */ 525 for_each_dsi_phy(phy, intel_dsi->phys) { 526 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 527 tmp |= TX_TRAINING_EN; 528 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 529 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 530 tmp |= TX_TRAINING_EN; 531 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 532 } 533 } 534 535 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 536 { 537 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 538 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 539 u32 tmp; 540 enum port port; 541 542 for_each_dsi_port(port, intel_dsi->ports) { 543 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 544 tmp |= DDI_BUF_CTL_ENABLE; 545 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 546 547 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 548 DDI_BUF_IS_IDLE), 549 500)) 550 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", 551 port_name(port)); 552 } 553 } 554 555 static void 556 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 557 const struct intel_crtc_state *crtc_state) 558 { 559 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 560 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 561 u32 tmp; 562 enum port port; 563 enum phy phy; 564 565 /* Program T-INIT master registers */ 566 for_each_dsi_port(port, intel_dsi->ports) { 567 tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port)); 568 tmp &= ~MASTER_INIT_TIMER_MASK; 569 tmp |= intel_dsi->init_count; 570 intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp); 571 } 572 573 /* Program DPHY clock lanes timings */ 574 for_each_dsi_port(port, intel_dsi->ports) { 575 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port), 576 intel_dsi->dphy_reg); 577 578 /* shadow register inside display core */ 579 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port), 580 intel_dsi->dphy_reg); 581 } 582 583 /* Program DPHY data lanes timings */ 584 for_each_dsi_port(port, intel_dsi->ports) { 585 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port), 586 intel_dsi->dphy_data_lane_reg); 587 588 /* shadow register inside display core */ 589 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port), 590 intel_dsi->dphy_data_lane_reg); 591 } 592 593 /* 594 * If DSI link operating at or below an 800 MHz, 595 * TA_SURE should be override and programmed to 596 * a value '0' inside TA_PARAM_REGISTERS otherwise 597 * leave all fields at HW default values. 598 */ 599 if (DISPLAY_VER(dev_priv) == 11) { 600 if (afe_clk(encoder, crtc_state) <= 800000) { 601 for_each_dsi_port(port, intel_dsi->ports) { 602 tmp = intel_de_read(dev_priv, 603 DPHY_TA_TIMING_PARAM(port)); 604 tmp &= ~TA_SURE_MASK; 605 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 606 intel_de_write(dev_priv, 607 DPHY_TA_TIMING_PARAM(port), 608 tmp); 609 610 /* shadow register inside display core */ 611 tmp = intel_de_read(dev_priv, 612 DSI_TA_TIMING_PARAM(port)); 613 tmp &= ~TA_SURE_MASK; 614 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 615 intel_de_write(dev_priv, 616 DSI_TA_TIMING_PARAM(port), tmp); 617 } 618 } 619 } 620 621 if (IS_JSL_EHL(dev_priv)) { 622 for_each_dsi_phy(phy, intel_dsi->phys) { 623 tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy)); 624 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; 625 intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp); 626 } 627 } 628 } 629 630 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 631 { 632 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 633 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 634 u32 tmp; 635 enum phy phy; 636 637 mutex_lock(&dev_priv->dpll.lock); 638 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 639 for_each_dsi_phy(phy, intel_dsi->phys) 640 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 641 642 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 643 mutex_unlock(&dev_priv->dpll.lock); 644 } 645 646 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 647 { 648 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 649 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 650 u32 tmp; 651 enum phy phy; 652 653 mutex_lock(&dev_priv->dpll.lock); 654 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 655 for_each_dsi_phy(phy, intel_dsi->phys) 656 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 657 658 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 659 mutex_unlock(&dev_priv->dpll.lock); 660 } 661 662 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 663 { 664 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 665 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 666 bool clock_enabled = false; 667 enum phy phy; 668 u32 tmp; 669 670 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 671 672 for_each_dsi_phy(phy, intel_dsi->phys) { 673 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 674 clock_enabled = true; 675 } 676 677 return clock_enabled; 678 } 679 680 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 681 const struct intel_crtc_state *crtc_state) 682 { 683 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 684 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 685 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 686 enum phy phy; 687 u32 val; 688 689 mutex_lock(&dev_priv->dpll.lock); 690 691 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 692 for_each_dsi_phy(phy, intel_dsi->phys) { 693 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 694 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 695 } 696 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 697 698 for_each_dsi_phy(phy, intel_dsi->phys) { 699 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 700 } 701 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 702 703 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 704 705 mutex_unlock(&dev_priv->dpll.lock); 706 } 707 708 static void 709 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 710 const struct intel_crtc_state *pipe_config) 711 { 712 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 713 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 714 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 715 enum pipe pipe = crtc->pipe; 716 u32 tmp; 717 enum port port; 718 enum transcoder dsi_trans; 719 720 for_each_dsi_port(port, intel_dsi->ports) { 721 dsi_trans = dsi_port_to_transcoder(port); 722 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 723 724 if (intel_dsi->eotp_pkt) 725 tmp &= ~EOTP_DISABLED; 726 else 727 tmp |= EOTP_DISABLED; 728 729 /* enable link calibration if freq > 1.5Gbps */ 730 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 731 tmp &= ~LINK_CALIBRATION_MASK; 732 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 733 } 734 735 /* configure continuous clock */ 736 tmp &= ~CONTINUOUS_CLK_MASK; 737 if (intel_dsi->clock_stop) 738 tmp |= CLK_ENTER_LP_AFTER_DATA; 739 else 740 tmp |= CLK_HS_CONTINUOUS; 741 742 /* configure buffer threshold limit to minimum */ 743 tmp &= ~PIX_BUF_THRESHOLD_MASK; 744 tmp |= PIX_BUF_THRESHOLD_1_4; 745 746 /* set virtual channel to '0' */ 747 tmp &= ~PIX_VIRT_CHAN_MASK; 748 tmp |= PIX_VIRT_CHAN(0); 749 750 /* program BGR transmission */ 751 if (intel_dsi->bgr_enabled) 752 tmp |= BGR_TRANSMISSION; 753 754 /* select pixel format */ 755 tmp &= ~PIX_FMT_MASK; 756 if (pipe_config->dsc.compression_enable) { 757 tmp |= PIX_FMT_COMPRESSED; 758 } else { 759 switch (intel_dsi->pixel_format) { 760 default: 761 MISSING_CASE(intel_dsi->pixel_format); 762 fallthrough; 763 case MIPI_DSI_FMT_RGB565: 764 tmp |= PIX_FMT_RGB565; 765 break; 766 case MIPI_DSI_FMT_RGB666_PACKED: 767 tmp |= PIX_FMT_RGB666_PACKED; 768 break; 769 case MIPI_DSI_FMT_RGB666: 770 tmp |= PIX_FMT_RGB666_LOOSE; 771 break; 772 case MIPI_DSI_FMT_RGB888: 773 tmp |= PIX_FMT_RGB888; 774 break; 775 } 776 } 777 778 if (DISPLAY_VER(dev_priv) >= 12) { 779 if (is_vid_mode(intel_dsi)) 780 tmp |= BLANKING_PACKET_ENABLE; 781 } 782 783 /* program DSI operation mode */ 784 if (is_vid_mode(intel_dsi)) { 785 tmp &= ~OP_MODE_MASK; 786 switch (intel_dsi->video_mode_format) { 787 default: 788 MISSING_CASE(intel_dsi->video_mode_format); 789 fallthrough; 790 case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS: 791 tmp |= VIDEO_MODE_SYNC_EVENT; 792 break; 793 case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE: 794 tmp |= VIDEO_MODE_SYNC_PULSE; 795 break; 796 } 797 } else { 798 /* 799 * FIXME: Retrieve this info from VBT. 800 * As per the spec when dsi transcoder is operating 801 * in TE GATE mode, TE comes from GPIO 802 * which is UTIL PIN for DSI 0. 803 * Also this GPIO would not be used for other 804 * purposes is an assumption. 805 */ 806 tmp &= ~OP_MODE_MASK; 807 tmp |= CMD_MODE_TE_GATE; 808 tmp |= TE_SOURCE_GPIO; 809 } 810 811 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 812 } 813 814 /* enable port sync mode if dual link */ 815 if (intel_dsi->dual_link) { 816 for_each_dsi_port(port, intel_dsi->ports) { 817 dsi_trans = dsi_port_to_transcoder(port); 818 tmp = intel_de_read(dev_priv, 819 TRANS_DDI_FUNC_CTL2(dsi_trans)); 820 tmp |= PORT_SYNC_MODE_ENABLE; 821 intel_de_write(dev_priv, 822 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 823 } 824 825 /* configure stream splitting */ 826 configure_dual_link_mode(encoder, pipe_config); 827 } 828 829 for_each_dsi_port(port, intel_dsi->ports) { 830 dsi_trans = dsi_port_to_transcoder(port); 831 832 /* select data lane width */ 833 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 834 tmp &= ~DDI_PORT_WIDTH_MASK; 835 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); 836 837 /* select input pipe */ 838 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 839 switch (pipe) { 840 default: 841 MISSING_CASE(pipe); 842 fallthrough; 843 case PIPE_A: 844 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 845 break; 846 case PIPE_B: 847 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 848 break; 849 case PIPE_C: 850 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 851 break; 852 case PIPE_D: 853 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 854 break; 855 } 856 857 /* enable DDI buffer */ 858 tmp |= TRANS_DDI_FUNC_ENABLE; 859 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 860 } 861 862 /* wait for link ready */ 863 for_each_dsi_port(port, intel_dsi->ports) { 864 dsi_trans = dsi_port_to_transcoder(port); 865 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) & 866 LINK_READY), 2500)) 867 drm_err(&dev_priv->drm, "DSI link not ready\n"); 868 } 869 } 870 871 static void 872 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 873 const struct intel_crtc_state *crtc_state) 874 { 875 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 876 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 877 const struct drm_display_mode *adjusted_mode = 878 &crtc_state->hw.adjusted_mode; 879 enum port port; 880 enum transcoder dsi_trans; 881 /* horizontal timings */ 882 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 883 u16 hback_porch; 884 /* vertical timings */ 885 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 886 int mul = 1, div = 1; 887 888 /* 889 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 890 * for slower link speed if DSC is enabled. 891 * 892 * The compression frequency ratio is the ratio between compressed and 893 * non-compressed link speeds, and simplifies down to the ratio between 894 * compressed and non-compressed bpp. 895 */ 896 if (crtc_state->dsc.compression_enable) { 897 mul = crtc_state->dsc.compressed_bpp; 898 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 899 } 900 901 hactive = adjusted_mode->crtc_hdisplay; 902 903 if (is_vid_mode(intel_dsi)) 904 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 905 else 906 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 907 908 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 909 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 910 hsync_size = hsync_end - hsync_start; 911 hback_porch = (adjusted_mode->crtc_htotal - 912 adjusted_mode->crtc_hsync_end); 913 vactive = adjusted_mode->crtc_vdisplay; 914 915 if (is_vid_mode(intel_dsi)) { 916 vtotal = adjusted_mode->crtc_vtotal; 917 } else { 918 int bpp, line_time_us, byte_clk_period_ns; 919 920 if (crtc_state->dsc.compression_enable) 921 bpp = crtc_state->dsc.compressed_bpp; 922 else 923 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 924 925 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 926 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 927 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 928 } 929 vsync_start = adjusted_mode->crtc_vsync_start; 930 vsync_end = adjusted_mode->crtc_vsync_end; 931 vsync_shift = hsync_start - htotal / 2; 932 933 if (intel_dsi->dual_link) { 934 hactive /= 2; 935 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 936 hactive += intel_dsi->pixel_overlap; 937 htotal /= 2; 938 } 939 940 /* minimum hactive as per bspec: 256 pixels */ 941 if (adjusted_mode->crtc_hdisplay < 256) 942 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); 943 944 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 945 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 946 drm_err(&dev_priv->drm, 947 "hactive pixels are not multiple of 4\n"); 948 949 /* program TRANS_HTOTAL register */ 950 for_each_dsi_port(port, intel_dsi->ports) { 951 dsi_trans = dsi_port_to_transcoder(port); 952 intel_de_write(dev_priv, HTOTAL(dsi_trans), 953 (hactive - 1) | ((htotal - 1) << 16)); 954 } 955 956 /* TRANS_HSYNC register to be programmed only for video mode */ 957 if (is_vid_mode(intel_dsi)) { 958 if (intel_dsi->video_mode_format == 959 VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) { 960 /* BSPEC: hsync size should be atleast 16 pixels */ 961 if (hsync_size < 16) 962 drm_err(&dev_priv->drm, 963 "hsync size < 16 pixels\n"); 964 } 965 966 if (hback_porch < 16) 967 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); 968 969 if (intel_dsi->dual_link) { 970 hsync_start /= 2; 971 hsync_end /= 2; 972 } 973 974 for_each_dsi_port(port, intel_dsi->ports) { 975 dsi_trans = dsi_port_to_transcoder(port); 976 intel_de_write(dev_priv, HSYNC(dsi_trans), 977 (hsync_start - 1) | ((hsync_end - 1) << 16)); 978 } 979 } 980 981 /* program TRANS_VTOTAL register */ 982 for_each_dsi_port(port, intel_dsi->ports) { 983 dsi_trans = dsi_port_to_transcoder(port); 984 /* 985 * FIXME: Programing this by assuming progressive mode, since 986 * non-interlaced info from VBT is not saved inside 987 * struct drm_display_mode. 988 * For interlace mode: program required pixel minus 2 989 */ 990 intel_de_write(dev_priv, VTOTAL(dsi_trans), 991 (vactive - 1) | ((vtotal - 1) << 16)); 992 } 993 994 if (vsync_end < vsync_start || vsync_end > vtotal) 995 drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); 996 997 if (vsync_start < vactive) 998 drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); 999 1000 /* program TRANS_VSYNC register for video mode only */ 1001 if (is_vid_mode(intel_dsi)) { 1002 for_each_dsi_port(port, intel_dsi->ports) { 1003 dsi_trans = dsi_port_to_transcoder(port); 1004 intel_de_write(dev_priv, VSYNC(dsi_trans), 1005 (vsync_start - 1) | ((vsync_end - 1) << 16)); 1006 } 1007 } 1008 1009 /* 1010 * FIXME: It has to be programmed only for video modes and interlaced 1011 * modes. Put the check condition here once interlaced 1012 * info available as described above. 1013 * program TRANS_VSYNCSHIFT register 1014 */ 1015 if (is_vid_mode(intel_dsi)) { 1016 for_each_dsi_port(port, intel_dsi->ports) { 1017 dsi_trans = dsi_port_to_transcoder(port); 1018 intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans), 1019 vsync_shift); 1020 } 1021 } 1022 1023 /* program TRANS_VBLANK register, should be same as vtotal programmed */ 1024 if (DISPLAY_VER(dev_priv) >= 12) { 1025 for_each_dsi_port(port, intel_dsi->ports) { 1026 dsi_trans = dsi_port_to_transcoder(port); 1027 intel_de_write(dev_priv, VBLANK(dsi_trans), 1028 (vactive - 1) | ((vtotal - 1) << 16)); 1029 } 1030 } 1031 } 1032 1033 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1034 { 1035 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1036 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1037 enum port port; 1038 enum transcoder dsi_trans; 1039 u32 tmp; 1040 1041 for_each_dsi_port(port, intel_dsi->ports) { 1042 dsi_trans = dsi_port_to_transcoder(port); 1043 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1044 tmp |= PIPECONF_ENABLE; 1045 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1046 1047 /* wait for transcoder to be enabled */ 1048 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), 1049 I965_PIPECONF_ACTIVE, 10)) 1050 drm_err(&dev_priv->drm, 1051 "DSI transcoder not enabled\n"); 1052 } 1053 } 1054 1055 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1056 const struct intel_crtc_state *crtc_state) 1057 { 1058 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1059 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1060 enum port port; 1061 enum transcoder dsi_trans; 1062 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1063 1064 /* 1065 * escape clock count calculation: 1066 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1067 * UI (nsec) = (10^6)/Bitrate 1068 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1069 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1070 */ 1071 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1072 mul = 8 * 1000000; 1073 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1074 divisor); 1075 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1076 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1077 1078 for_each_dsi_port(port, intel_dsi->ports) { 1079 dsi_trans = dsi_port_to_transcoder(port); 1080 1081 /* program hst_tx_timeout */ 1082 tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans)); 1083 tmp &= ~HSTX_TIMEOUT_VALUE_MASK; 1084 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout); 1085 intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp); 1086 1087 /* FIXME: DSI_CALIB_TO */ 1088 1089 /* program lp_rx_host timeout */ 1090 tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans)); 1091 tmp &= ~LPRX_TIMEOUT_VALUE_MASK; 1092 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout); 1093 intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp); 1094 1095 /* FIXME: DSI_PWAIT_TO */ 1096 1097 /* program turn around timeout */ 1098 tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans)); 1099 tmp &= ~TA_TIMEOUT_VALUE_MASK; 1100 tmp |= TA_TIMEOUT_VALUE(ta_timeout); 1101 intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp); 1102 } 1103 } 1104 1105 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1106 bool enable) 1107 { 1108 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1109 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1110 u32 tmp; 1111 1112 /* 1113 * used as TE i/p for DSI0, 1114 * for dual link/DSI1 TE is from slave DSI1 1115 * through GPIO. 1116 */ 1117 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1118 return; 1119 1120 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL); 1121 1122 if (enable) { 1123 tmp |= UTIL_PIN_DIRECTION_INPUT; 1124 tmp |= UTIL_PIN_ENABLE; 1125 } else { 1126 tmp &= ~UTIL_PIN_ENABLE; 1127 } 1128 intel_de_write(dev_priv, UTIL_PIN_CTL, tmp); 1129 } 1130 1131 static void 1132 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1133 const struct intel_crtc_state *crtc_state) 1134 { 1135 /* step 4a: power up all lanes of the DDI used by DSI */ 1136 gen11_dsi_power_up_lanes(encoder); 1137 1138 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1139 gen11_dsi_config_phy_lanes_sequence(encoder); 1140 1141 /* step 4c: configure voltage swing and skew */ 1142 gen11_dsi_voltage_swing_program_seq(encoder); 1143 1144 /* enable DDI buffer */ 1145 gen11_dsi_enable_ddi_buffer(encoder); 1146 1147 /* setup D-PHY timings */ 1148 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1149 1150 /* Since transcoder is configured to take events from GPIO */ 1151 gen11_dsi_config_util_pin(encoder, true); 1152 1153 /* step 4h: setup DSI protocol timeouts */ 1154 gen11_dsi_setup_timeouts(encoder, crtc_state); 1155 1156 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1157 gen11_dsi_configure_transcoder(encoder, crtc_state); 1158 1159 /* Step 4l: Gate DDI clocks */ 1160 gen11_dsi_gate_clocks(encoder); 1161 } 1162 1163 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1164 { 1165 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1166 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1167 struct mipi_dsi_device *dsi; 1168 enum port port; 1169 enum transcoder dsi_trans; 1170 u32 tmp; 1171 int ret; 1172 1173 /* set maximum return packet size */ 1174 for_each_dsi_port(port, intel_dsi->ports) { 1175 dsi_trans = dsi_port_to_transcoder(port); 1176 1177 /* 1178 * FIXME: This uses the number of DW's currently in the payload 1179 * receive queue. This is probably not what we want here. 1180 */ 1181 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans)); 1182 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1183 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1184 tmp = tmp * 4; 1185 dsi = intel_dsi->dsi_hosts[port]->device; 1186 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1187 if (ret < 0) 1188 drm_err(&dev_priv->drm, 1189 "error setting max return pkt size%d\n", tmp); 1190 } 1191 1192 /* panel power on related mipi dsi vbt sequences */ 1193 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1194 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 1195 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1196 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1197 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1198 1199 /* ensure all panel commands dispatched before enabling transcoder */ 1200 wait_for_cmds_dispatched_to_panel(encoder); 1201 } 1202 1203 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1204 struct intel_encoder *encoder, 1205 const struct intel_crtc_state *crtc_state, 1206 const struct drm_connector_state *conn_state) 1207 { 1208 /* step2: enable IO power */ 1209 gen11_dsi_enable_io_power(encoder); 1210 1211 /* step3: enable DSI PLL */ 1212 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1213 } 1214 1215 static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1216 struct intel_encoder *encoder, 1217 const struct intel_crtc_state *pipe_config, 1218 const struct drm_connector_state *conn_state) 1219 { 1220 /* step3b */ 1221 gen11_dsi_map_pll(encoder, pipe_config); 1222 1223 /* step4: enable DSI port and DPHY */ 1224 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1225 1226 /* step5: program and powerup panel */ 1227 gen11_dsi_powerup_panel(encoder); 1228 1229 intel_dsc_enable(encoder, pipe_config); 1230 1231 /* step6c: configure transcoder timings */ 1232 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1233 } 1234 1235 /* 1236 * Wa_1409054076:icl,jsl,ehl 1237 * When pipe A is disabled and MIPI DSI is enabled on pipe B, 1238 * the AMT KVMR feature will incorrectly see pipe A as enabled. 1239 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave 1240 * it set while DSI is enabled on pipe B 1241 */ 1242 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, 1243 enum pipe pipe, bool enable) 1244 { 1245 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1246 1247 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) 1248 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1249 IGNORE_KVMR_PIPE_A, 1250 enable ? IGNORE_KVMR_PIPE_A : 0); 1251 } 1252 1253 /* 1254 * Wa_16012360555:adl-p 1255 * SW will have to program the "LP to HS Wakeup Guardband" 1256 * to account for the repeaters on the HS Request/Ready 1257 * PPI signaling between the Display engine and the DPHY. 1258 */ 1259 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) 1260 { 1261 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1262 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1263 enum port port; 1264 1265 if (DISPLAY_VER(i915) == 13) { 1266 for_each_dsi_port(port, intel_dsi->ports) 1267 intel_de_rmw(i915, TGL_DSI_CHKN_REG(port), 1268 TGL_DSI_CHKN_LSHS_GB_MASK, 1269 TGL_DSI_CHKN_LSHS_GB(4)); 1270 } 1271 } 1272 1273 static void gen11_dsi_enable(struct intel_atomic_state *state, 1274 struct intel_encoder *encoder, 1275 const struct intel_crtc_state *crtc_state, 1276 const struct drm_connector_state *conn_state) 1277 { 1278 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1279 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 1280 1281 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 1282 1283 /* Wa_1409054076:icl,jsl,ehl */ 1284 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); 1285 1286 /* Wa_16012360555:adl-p */ 1287 adlp_set_lp_hs_wakeup_gb(encoder); 1288 1289 /* step6d: enable dsi transcoder */ 1290 gen11_dsi_enable_transcoder(encoder); 1291 1292 /* step7: enable backlight */ 1293 intel_backlight_enable(crtc_state, conn_state); 1294 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1295 1296 intel_crtc_vblank_on(crtc_state); 1297 } 1298 1299 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1300 { 1301 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1302 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1303 enum port port; 1304 enum transcoder dsi_trans; 1305 u32 tmp; 1306 1307 for_each_dsi_port(port, intel_dsi->ports) { 1308 dsi_trans = dsi_port_to_transcoder(port); 1309 1310 /* disable transcoder */ 1311 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1312 tmp &= ~PIPECONF_ENABLE; 1313 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1314 1315 /* wait for transcoder to be disabled */ 1316 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), 1317 I965_PIPECONF_ACTIVE, 50)) 1318 drm_err(&dev_priv->drm, 1319 "DSI trancoder not disabled\n"); 1320 } 1321 } 1322 1323 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1324 { 1325 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1326 1327 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1328 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1329 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1330 1331 /* ensure cmds dispatched to panel */ 1332 wait_for_cmds_dispatched_to_panel(encoder); 1333 } 1334 1335 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1336 { 1337 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1338 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1339 enum port port; 1340 enum transcoder dsi_trans; 1341 u32 tmp; 1342 1343 /* disable periodic update mode */ 1344 if (is_cmd_mode(intel_dsi)) { 1345 for_each_dsi_port(port, intel_dsi->ports) { 1346 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 1347 tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE; 1348 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 1349 } 1350 } 1351 1352 /* put dsi link in ULPS */ 1353 for_each_dsi_port(port, intel_dsi->ports) { 1354 dsi_trans = dsi_port_to_transcoder(port); 1355 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)); 1356 tmp |= LINK_ENTER_ULPS; 1357 tmp &= ~LINK_ULPS_TYPE_LP11; 1358 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp); 1359 1360 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 1361 LINK_IN_ULPS), 1362 10)) 1363 drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); 1364 } 1365 1366 /* disable ddi function */ 1367 for_each_dsi_port(port, intel_dsi->ports) { 1368 dsi_trans = dsi_port_to_transcoder(port); 1369 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1370 tmp &= ~TRANS_DDI_FUNC_ENABLE; 1371 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 1372 } 1373 1374 /* disable port sync mode if dual link */ 1375 if (intel_dsi->dual_link) { 1376 for_each_dsi_port(port, intel_dsi->ports) { 1377 dsi_trans = dsi_port_to_transcoder(port); 1378 tmp = intel_de_read(dev_priv, 1379 TRANS_DDI_FUNC_CTL2(dsi_trans)); 1380 tmp &= ~PORT_SYNC_MODE_ENABLE; 1381 intel_de_write(dev_priv, 1382 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 1383 } 1384 } 1385 } 1386 1387 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1388 { 1389 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1390 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1391 u32 tmp; 1392 enum port port; 1393 1394 gen11_dsi_ungate_clocks(encoder); 1395 for_each_dsi_port(port, intel_dsi->ports) { 1396 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1397 tmp &= ~DDI_BUF_CTL_ENABLE; 1398 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 1399 1400 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1401 DDI_BUF_IS_IDLE), 1402 8)) 1403 drm_err(&dev_priv->drm, 1404 "DDI port:%c buffer not idle\n", 1405 port_name(port)); 1406 } 1407 gen11_dsi_gate_clocks(encoder); 1408 } 1409 1410 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1411 { 1412 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1413 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1414 enum port port; 1415 u32 tmp; 1416 1417 for_each_dsi_port(port, intel_dsi->ports) { 1418 intel_wakeref_t wakeref; 1419 1420 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1421 intel_display_power_put(dev_priv, 1422 port == PORT_A ? 1423 POWER_DOMAIN_PORT_DDI_A_IO : 1424 POWER_DOMAIN_PORT_DDI_B_IO, 1425 wakeref); 1426 } 1427 1428 /* set mode to DDI */ 1429 for_each_dsi_port(port, intel_dsi->ports) { 1430 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 1431 tmp &= ~COMBO_PHY_MODE_DSI; 1432 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 1433 } 1434 } 1435 1436 static void gen11_dsi_disable(struct intel_atomic_state *state, 1437 struct intel_encoder *encoder, 1438 const struct intel_crtc_state *old_crtc_state, 1439 const struct drm_connector_state *old_conn_state) 1440 { 1441 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1442 struct intel_crtc *crtc = to_intel_crtc(old_conn_state->crtc); 1443 1444 /* step1: turn off backlight */ 1445 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1446 intel_backlight_disable(old_conn_state); 1447 1448 /* step2d,e: disable transcoder and wait */ 1449 gen11_dsi_disable_transcoder(encoder); 1450 1451 /* Wa_1409054076:icl,jsl,ehl */ 1452 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); 1453 1454 /* step2f,g: powerdown panel */ 1455 gen11_dsi_powerdown_panel(encoder); 1456 1457 /* step2h,i,j: deconfig trancoder */ 1458 gen11_dsi_deconfigure_trancoder(encoder); 1459 1460 /* step3: disable port */ 1461 gen11_dsi_disable_port(encoder); 1462 1463 gen11_dsi_config_util_pin(encoder, false); 1464 1465 /* step4: disable IO power */ 1466 gen11_dsi_disable_io_power(encoder); 1467 } 1468 1469 static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1470 struct intel_encoder *encoder, 1471 const struct intel_crtc_state *old_crtc_state, 1472 const struct drm_connector_state *old_conn_state) 1473 { 1474 intel_crtc_vblank_off(old_crtc_state); 1475 1476 intel_dsc_disable(old_crtc_state); 1477 1478 skl_scaler_disable(old_crtc_state); 1479 } 1480 1481 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1482 struct drm_display_mode *mode) 1483 { 1484 /* FIXME: DSC? */ 1485 return intel_dsi_mode_valid(connector, mode); 1486 } 1487 1488 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1489 struct intel_crtc_state *pipe_config) 1490 { 1491 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1492 struct drm_display_mode *adjusted_mode = 1493 &pipe_config->hw.adjusted_mode; 1494 1495 if (pipe_config->dsc.compressed_bpp) { 1496 int div = pipe_config->dsc.compressed_bpp; 1497 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1498 1499 adjusted_mode->crtc_htotal = 1500 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1501 adjusted_mode->crtc_hsync_start = 1502 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1503 adjusted_mode->crtc_hsync_end = 1504 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1505 } 1506 1507 if (intel_dsi->dual_link) { 1508 adjusted_mode->crtc_hdisplay *= 2; 1509 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1510 adjusted_mode->crtc_hdisplay -= 1511 intel_dsi->pixel_overlap; 1512 adjusted_mode->crtc_htotal *= 2; 1513 } 1514 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1515 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1516 1517 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1518 if (intel_dsi->dual_link) { 1519 adjusted_mode->crtc_hsync_start *= 2; 1520 adjusted_mode->crtc_hsync_end *= 2; 1521 } 1522 } 1523 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1524 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1525 } 1526 1527 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1528 { 1529 struct drm_device *dev = intel_dsi->base.base.dev; 1530 struct drm_i915_private *dev_priv = to_i915(dev); 1531 enum transcoder dsi_trans; 1532 u32 val; 1533 1534 if (intel_dsi->ports == BIT(PORT_B)) 1535 dsi_trans = TRANSCODER_DSI_1; 1536 else 1537 dsi_trans = TRANSCODER_DSI_0; 1538 1539 val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 1540 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1541 } 1542 1543 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1544 struct intel_crtc_state *pipe_config) 1545 { 1546 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1547 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1548 I915_MODE_FLAG_DSI_USE_TE0; 1549 else if (intel_dsi->ports == BIT(PORT_B)) 1550 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1551 else 1552 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1553 } 1554 1555 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1556 struct intel_crtc_state *pipe_config) 1557 { 1558 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1559 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1560 1561 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1562 1563 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1564 if (intel_dsi->dual_link) 1565 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1566 1567 gen11_dsi_get_timings(encoder, pipe_config); 1568 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1569 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1570 1571 /* Get the details on which TE should be enabled */ 1572 if (is_cmd_mode(intel_dsi)) 1573 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1574 1575 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1576 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1577 } 1578 1579 static void gen11_dsi_sync_state(struct intel_encoder *encoder, 1580 const struct intel_crtc_state *crtc_state) 1581 { 1582 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1583 struct intel_crtc *intel_crtc; 1584 enum pipe pipe; 1585 1586 if (!crtc_state) 1587 return; 1588 1589 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1590 pipe = intel_crtc->pipe; 1591 1592 /* wa verify 1409054076:icl,jsl,ehl */ 1593 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && 1594 !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A)) 1595 drm_dbg_kms(&dev_priv->drm, 1596 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n", 1597 encoder->base.base.id, 1598 encoder->base.name); 1599 } 1600 1601 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1602 struct intel_crtc_state *crtc_state) 1603 { 1604 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1605 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1606 int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10; 1607 bool use_dsc; 1608 int ret; 1609 1610 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1611 if (!use_dsc) 1612 return 0; 1613 1614 if (crtc_state->pipe_bpp < 8 * 3) 1615 return -EINVAL; 1616 1617 /* FIXME: split only when necessary */ 1618 if (crtc_state->dsc.slice_count > 1) 1619 crtc_state->dsc.dsc_split = true; 1620 1621 vdsc_cfg->convert_rgb = true; 1622 1623 /* FIXME: initialize from VBT */ 1624 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1625 1626 ret = intel_dsc_compute_params(encoder, crtc_state); 1627 if (ret) 1628 return ret; 1629 1630 /* DSI specific sanity checks on the common code */ 1631 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); 1632 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); 1633 drm_WARN_ON(&dev_priv->drm, 1634 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1635 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); 1636 drm_WARN_ON(&dev_priv->drm, 1637 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1638 1639 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1640 if (ret) 1641 return ret; 1642 1643 crtc_state->dsc.compression_enable = true; 1644 1645 return 0; 1646 } 1647 1648 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1649 struct intel_crtc_state *pipe_config, 1650 struct drm_connector_state *conn_state) 1651 { 1652 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1653 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 1654 base); 1655 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1656 struct drm_display_mode *adjusted_mode = 1657 &pipe_config->hw.adjusted_mode; 1658 int ret; 1659 1660 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1661 1662 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 1663 if (ret) 1664 return ret; 1665 1666 ret = intel_panel_fitting(pipe_config, conn_state); 1667 if (ret) 1668 return ret; 1669 1670 adjusted_mode->flags = 0; 1671 1672 /* Dual link goes to trancoder DSI'0' */ 1673 if (intel_dsi->ports == BIT(PORT_B)) 1674 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1675 else 1676 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1677 1678 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1679 pipe_config->pipe_bpp = 24; 1680 else 1681 pipe_config->pipe_bpp = 18; 1682 1683 pipe_config->clock_set = true; 1684 1685 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1686 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n"); 1687 1688 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1689 1690 /* 1691 * In case of TE GATE cmd mode, we 1692 * receive TE from the slave if 1693 * dual link is enabled 1694 */ 1695 if (is_cmd_mode(intel_dsi)) 1696 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1697 1698 return 0; 1699 } 1700 1701 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1702 struct intel_crtc_state *crtc_state) 1703 { 1704 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1705 1706 get_dsi_io_power_domains(i915, 1707 enc_to_intel_dsi(encoder)); 1708 } 1709 1710 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1711 enum pipe *pipe) 1712 { 1713 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1714 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1715 enum transcoder dsi_trans; 1716 intel_wakeref_t wakeref; 1717 enum port port; 1718 bool ret = false; 1719 u32 tmp; 1720 1721 wakeref = intel_display_power_get_if_enabled(dev_priv, 1722 encoder->power_domain); 1723 if (!wakeref) 1724 return false; 1725 1726 for_each_dsi_port(port, intel_dsi->ports) { 1727 dsi_trans = dsi_port_to_transcoder(port); 1728 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1729 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1730 case TRANS_DDI_EDP_INPUT_A_ON: 1731 *pipe = PIPE_A; 1732 break; 1733 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1734 *pipe = PIPE_B; 1735 break; 1736 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1737 *pipe = PIPE_C; 1738 break; 1739 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1740 *pipe = PIPE_D; 1741 break; 1742 default: 1743 drm_err(&dev_priv->drm, "Invalid PIPE input\n"); 1744 goto out; 1745 } 1746 1747 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1748 ret = tmp & PIPECONF_ENABLE; 1749 } 1750 out: 1751 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1752 return ret; 1753 } 1754 1755 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1756 struct intel_crtc_state *crtc_state) 1757 { 1758 if (crtc_state->dsc.compression_enable) { 1759 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1760 crtc_state->uapi.mode_changed = true; 1761 1762 return false; 1763 } 1764 1765 return true; 1766 } 1767 1768 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1769 { 1770 intel_encoder_destroy(encoder); 1771 } 1772 1773 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1774 .destroy = gen11_dsi_encoder_destroy, 1775 }; 1776 1777 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1778 .detect = intel_panel_detect, 1779 .late_register = intel_connector_register, 1780 .early_unregister = intel_connector_unregister, 1781 .destroy = intel_connector_destroy, 1782 .fill_modes = drm_helper_probe_single_connector_modes, 1783 .atomic_get_property = intel_digital_connector_atomic_get_property, 1784 .atomic_set_property = intel_digital_connector_atomic_set_property, 1785 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1786 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1787 }; 1788 1789 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1790 .get_modes = intel_dsi_get_modes, 1791 .mode_valid = gen11_dsi_mode_valid, 1792 .atomic_check = intel_digital_connector_atomic_check, 1793 }; 1794 1795 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1796 struct mipi_dsi_device *dsi) 1797 { 1798 return 0; 1799 } 1800 1801 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1802 struct mipi_dsi_device *dsi) 1803 { 1804 return 0; 1805 } 1806 1807 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1808 const struct mipi_dsi_msg *msg) 1809 { 1810 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1811 struct mipi_dsi_packet dsi_pkt; 1812 ssize_t ret; 1813 bool enable_lpdt = false; 1814 1815 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1816 if (ret < 0) 1817 return ret; 1818 1819 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1820 enable_lpdt = true; 1821 1822 /* only long packet contains payload */ 1823 if (mipi_dsi_packet_format_is_long(msg->type)) { 1824 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt); 1825 if (ret < 0) 1826 return ret; 1827 } 1828 1829 /* send packet header */ 1830 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt); 1831 if (ret < 0) 1832 return ret; 1833 1834 //TODO: add payload receive code if needed 1835 1836 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1837 1838 return ret; 1839 } 1840 1841 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1842 .attach = gen11_dsi_host_attach, 1843 .detach = gen11_dsi_host_detach, 1844 .transfer = gen11_dsi_host_transfer, 1845 }; 1846 1847 #define ICL_PREPARE_CNT_MAX 0x7 1848 #define ICL_CLK_ZERO_CNT_MAX 0xf 1849 #define ICL_TRAIL_CNT_MAX 0x7 1850 #define ICL_TCLK_PRE_CNT_MAX 0x3 1851 #define ICL_TCLK_POST_CNT_MAX 0x7 1852 #define ICL_HS_ZERO_CNT_MAX 0xf 1853 #define ICL_EXIT_ZERO_CNT_MAX 0x7 1854 1855 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1856 { 1857 struct drm_device *dev = intel_dsi->base.base.dev; 1858 struct drm_i915_private *dev_priv = to_i915(dev); 1859 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 1860 u32 tlpx_ns; 1861 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1862 u32 ths_prepare_ns, tclk_trail_ns; 1863 u32 hs_zero_cnt; 1864 u32 tclk_pre_cnt, tclk_post_cnt; 1865 1866 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1867 1868 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1869 ths_prepare_ns = max(mipi_config->ths_prepare, 1870 mipi_config->tclk_prepare); 1871 1872 /* 1873 * prepare cnt in escape clocks 1874 * this field represents a hexadecimal value with a precision 1875 * of 1.2 – i.e. the most significant bit is the integer 1876 * and the least significant 2 bits are fraction bits. 1877 * so, the field can represent a range of 0.25 to 1.75 1878 */ 1879 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1880 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1881 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", 1882 prepare_cnt); 1883 prepare_cnt = ICL_PREPARE_CNT_MAX; 1884 } 1885 1886 /* clk zero count in escape clocks */ 1887 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1888 ths_prepare_ns, tlpx_ns); 1889 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1890 drm_dbg_kms(&dev_priv->drm, 1891 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1892 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1893 } 1894 1895 /* trail cnt in escape clocks*/ 1896 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1897 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1898 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", 1899 trail_cnt); 1900 trail_cnt = ICL_TRAIL_CNT_MAX; 1901 } 1902 1903 /* tclk pre count in escape clocks */ 1904 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1905 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1906 drm_dbg_kms(&dev_priv->drm, 1907 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1908 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1909 } 1910 1911 /* tclk post count in escape clocks */ 1912 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); 1913 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { 1914 drm_dbg_kms(&dev_priv->drm, 1915 "tclk_post_cnt out of range (%d)\n", 1916 tclk_post_cnt); 1917 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; 1918 } 1919 1920 /* hs zero cnt in escape clocks */ 1921 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1922 ths_prepare_ns, tlpx_ns); 1923 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1924 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", 1925 hs_zero_cnt); 1926 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1927 } 1928 1929 /* hs exit zero cnt in escape clocks */ 1930 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1931 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1932 drm_dbg_kms(&dev_priv->drm, 1933 "exit_zero_cnt out of range (%d)\n", 1934 exit_zero_cnt); 1935 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1936 } 1937 1938 /* clock lane dphy timings */ 1939 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1940 CLK_PREPARE(prepare_cnt) | 1941 CLK_ZERO_OVERRIDE | 1942 CLK_ZERO(clk_zero_cnt) | 1943 CLK_PRE_OVERRIDE | 1944 CLK_PRE(tclk_pre_cnt) | 1945 CLK_POST_OVERRIDE | 1946 CLK_POST(tclk_post_cnt) | 1947 CLK_TRAIL_OVERRIDE | 1948 CLK_TRAIL(trail_cnt)); 1949 1950 /* data lanes dphy timings */ 1951 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1952 HS_PREPARE(prepare_cnt) | 1953 HS_ZERO_OVERRIDE | 1954 HS_ZERO(hs_zero_cnt) | 1955 HS_TRAIL_OVERRIDE | 1956 HS_TRAIL(trail_cnt) | 1957 HS_EXIT_OVERRIDE | 1958 HS_EXIT(exit_zero_cnt)); 1959 1960 intel_dsi_log_params(intel_dsi); 1961 } 1962 1963 static void icl_dsi_add_properties(struct intel_connector *connector) 1964 { 1965 u32 allowed_scalers; 1966 1967 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | 1968 BIT(DRM_MODE_SCALE_FULLSCREEN) | 1969 BIT(DRM_MODE_SCALE_CENTER); 1970 1971 drm_connector_attach_scaling_mode_property(&connector->base, 1972 allowed_scalers); 1973 1974 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1975 1976 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1977 intel_dsi_get_panel_orientation(connector), 1978 connector->panel.fixed_mode->hdisplay, 1979 connector->panel.fixed_mode->vdisplay); 1980 } 1981 1982 void icl_dsi_init(struct drm_i915_private *dev_priv) 1983 { 1984 struct drm_device *dev = &dev_priv->drm; 1985 struct intel_dsi *intel_dsi; 1986 struct intel_encoder *encoder; 1987 struct intel_connector *intel_connector; 1988 struct drm_connector *connector; 1989 struct drm_display_mode *fixed_mode; 1990 enum port port; 1991 1992 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1993 return; 1994 1995 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1996 if (!intel_dsi) 1997 return; 1998 1999 intel_connector = intel_connector_alloc(); 2000 if (!intel_connector) { 2001 kfree(intel_dsi); 2002 return; 2003 } 2004 2005 encoder = &intel_dsi->base; 2006 intel_dsi->attached_connector = intel_connector; 2007 connector = &intel_connector->base; 2008 2009 /* register DSI encoder with DRM subsystem */ 2010 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs, 2011 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 2012 2013 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 2014 encoder->pre_enable = gen11_dsi_pre_enable; 2015 encoder->enable = gen11_dsi_enable; 2016 encoder->disable = gen11_dsi_disable; 2017 encoder->post_disable = gen11_dsi_post_disable; 2018 encoder->port = port; 2019 encoder->get_config = gen11_dsi_get_config; 2020 encoder->sync_state = gen11_dsi_sync_state; 2021 encoder->update_pipe = intel_backlight_update; 2022 encoder->compute_config = gen11_dsi_compute_config; 2023 encoder->get_hw_state = gen11_dsi_get_hw_state; 2024 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 2025 encoder->type = INTEL_OUTPUT_DSI; 2026 encoder->cloneable = 0; 2027 encoder->pipe_mask = ~0; 2028 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 2029 encoder->get_power_domains = gen11_dsi_get_power_domains; 2030 encoder->disable_clock = gen11_dsi_gate_clocks; 2031 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 2032 2033 /* register DSI connector with DRM subsystem */ 2034 drm_connector_init(dev, connector, &gen11_dsi_connector_funcs, 2035 DRM_MODE_CONNECTOR_DSI); 2036 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 2037 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 2038 connector->interlace_allowed = false; 2039 connector->doublescan_allowed = false; 2040 intel_connector->get_hw_state = intel_connector_get_hw_state; 2041 2042 /* attach connector to encoder */ 2043 intel_connector_attach_encoder(intel_connector, encoder); 2044 2045 mutex_lock(&dev->mode_config.mutex); 2046 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 2047 mutex_unlock(&dev->mode_config.mutex); 2048 2049 if (!fixed_mode) { 2050 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); 2051 goto err; 2052 } 2053 2054 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 2055 intel_backlight_setup(intel_connector, INVALID_PIPE); 2056 2057 if (dev_priv->vbt.dsi.config->dual_link) 2058 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 2059 else 2060 intel_dsi->ports = BIT(port); 2061 2062 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; 2063 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; 2064 2065 for_each_dsi_port(port, intel_dsi->ports) { 2066 struct intel_dsi_host *host; 2067 2068 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2069 if (!host) 2070 goto err; 2071 2072 intel_dsi->dsi_hosts[port] = host; 2073 } 2074 2075 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2076 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 2077 goto err; 2078 } 2079 2080 icl_dphy_param_init(intel_dsi); 2081 2082 icl_dsi_add_properties(intel_connector); 2083 return; 2084 2085 err: 2086 drm_connector_cleanup(connector); 2087 drm_encoder_cleanup(&encoder->base); 2088 kfree(intel_dsi); 2089 kfree(intel_connector); 2090 } 2091