1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_mipi_dsi.h> 30 31 #include "intel_atomic.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_ddi.h" 35 #include "intel_dsi.h" 36 #include "intel_panel.h" 37 38 static inline int header_credits_available(struct drm_i915_private *dev_priv, 39 enum transcoder dsi_trans) 40 { 41 return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 42 >> FREE_HEADER_CREDIT_SHIFT; 43 } 44 45 static inline int payload_credits_available(struct drm_i915_private *dev_priv, 46 enum transcoder dsi_trans) 47 { 48 return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 49 >> FREE_PLOAD_CREDIT_SHIFT; 50 } 51 52 static void wait_for_header_credits(struct drm_i915_private *dev_priv, 53 enum transcoder dsi_trans) 54 { 55 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= 56 MAX_HEADER_CREDIT, 100)) 57 DRM_ERROR("DSI header credits not released\n"); 58 } 59 60 static void wait_for_payload_credits(struct drm_i915_private *dev_priv, 61 enum transcoder dsi_trans) 62 { 63 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= 64 MAX_PLOAD_CREDIT, 100)) 65 DRM_ERROR("DSI payload credits not released\n"); 66 } 67 68 static enum transcoder dsi_port_to_transcoder(enum port port) 69 { 70 if (port == PORT_A) 71 return TRANSCODER_DSI_0; 72 else 73 return TRANSCODER_DSI_1; 74 } 75 76 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 77 { 78 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 79 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 80 struct mipi_dsi_device *dsi; 81 enum port port; 82 enum transcoder dsi_trans; 83 int ret; 84 85 /* wait for header/payload credits to be released */ 86 for_each_dsi_port(port, intel_dsi->ports) { 87 dsi_trans = dsi_port_to_transcoder(port); 88 wait_for_header_credits(dev_priv, dsi_trans); 89 wait_for_payload_credits(dev_priv, dsi_trans); 90 } 91 92 /* send nop DCS command */ 93 for_each_dsi_port(port, intel_dsi->ports) { 94 dsi = intel_dsi->dsi_hosts[port]->device; 95 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 96 dsi->channel = 0; 97 ret = mipi_dsi_dcs_nop(dsi); 98 if (ret < 0) 99 DRM_ERROR("error sending DCS NOP command\n"); 100 } 101 102 /* wait for header credits to be released */ 103 for_each_dsi_port(port, intel_dsi->ports) { 104 dsi_trans = dsi_port_to_transcoder(port); 105 wait_for_header_credits(dev_priv, dsi_trans); 106 } 107 108 /* wait for LP TX in progress bit to be cleared */ 109 for_each_dsi_port(port, intel_dsi->ports) { 110 dsi_trans = dsi_port_to_transcoder(port); 111 if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) & 112 LPTX_IN_PROGRESS), 20)) 113 DRM_ERROR("LPTX bit not cleared\n"); 114 } 115 } 116 117 static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data, 118 u32 len) 119 { 120 struct intel_dsi *intel_dsi = host->intel_dsi; 121 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 122 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 123 int free_credits; 124 int i, j; 125 126 for (i = 0; i < len; i += 4) { 127 u32 tmp = 0; 128 129 free_credits = payload_credits_available(dev_priv, dsi_trans); 130 if (free_credits < 1) { 131 DRM_ERROR("Payload credit not available\n"); 132 return false; 133 } 134 135 for (j = 0; j < min_t(u32, len - i, 4); j++) 136 tmp |= *data++ << 8 * j; 137 138 I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp); 139 } 140 141 return true; 142 } 143 144 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 145 struct mipi_dsi_packet pkt, bool enable_lpdt) 146 { 147 struct intel_dsi *intel_dsi = host->intel_dsi; 148 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 149 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 150 u32 tmp; 151 int free_credits; 152 153 /* check if header credit available */ 154 free_credits = header_credits_available(dev_priv, dsi_trans); 155 if (free_credits < 1) { 156 DRM_ERROR("send pkt header failed, not enough hdr credits\n"); 157 return -1; 158 } 159 160 tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans)); 161 162 if (pkt.payload) 163 tmp |= PAYLOAD_PRESENT; 164 else 165 tmp &= ~PAYLOAD_PRESENT; 166 167 tmp &= ~VBLANK_FENCE; 168 169 if (enable_lpdt) 170 tmp |= LP_DATA_TRANSFER; 171 172 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 173 tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT); 174 tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT); 175 tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT); 176 tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT); 177 I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp); 178 179 return 0; 180 } 181 182 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 183 struct mipi_dsi_packet pkt) 184 { 185 /* payload queue can accept *256 bytes*, check limit */ 186 if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) { 187 DRM_ERROR("payload size exceeds max queue limit\n"); 188 return -1; 189 } 190 191 /* load data into command payload queue */ 192 if (!add_payld_to_queue(host, pkt.payload, 193 pkt.payload_length)) { 194 DRM_ERROR("adding payload to queue failed\n"); 195 return -1; 196 } 197 198 return 0; 199 } 200 201 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 202 { 203 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 204 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 205 enum phy phy; 206 u32 tmp; 207 int lane; 208 209 for_each_dsi_phy(phy, intel_dsi->phys) { 210 /* 211 * Program voltage swing and pre-emphasis level values as per 212 * table in BSPEC under DDI buffer programing 213 */ 214 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 215 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 216 tmp |= SCALING_MODE_SEL(0x2); 217 tmp |= TAP2_DISABLE | TAP3_DISABLE; 218 tmp |= RTERM_SELECT(0x6); 219 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); 220 221 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); 222 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 223 tmp |= SCALING_MODE_SEL(0x2); 224 tmp |= TAP2_DISABLE | TAP3_DISABLE; 225 tmp |= RTERM_SELECT(0x6); 226 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); 227 228 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); 229 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 230 RCOMP_SCALAR_MASK); 231 tmp |= SWING_SEL_UPPER(0x2); 232 tmp |= SWING_SEL_LOWER(0x2); 233 tmp |= RCOMP_SCALAR(0x98); 234 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp); 235 236 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); 237 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 238 RCOMP_SCALAR_MASK); 239 tmp |= SWING_SEL_UPPER(0x2); 240 tmp |= SWING_SEL_LOWER(0x2); 241 tmp |= RCOMP_SCALAR(0x98); 242 I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp); 243 244 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); 245 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 246 CURSOR_COEFF_MASK); 247 tmp |= POST_CURSOR_1(0x0); 248 tmp |= POST_CURSOR_2(0x0); 249 tmp |= CURSOR_COEFF(0x3f); 250 I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp); 251 252 for (lane = 0; lane <= 3; lane++) { 253 /* Bspec: must not use GRP register for write */ 254 tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); 255 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 256 CURSOR_COEFF_MASK); 257 tmp |= POST_CURSOR_1(0x0); 258 tmp |= POST_CURSOR_2(0x0); 259 tmp |= CURSOR_COEFF(0x3f); 260 I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); 261 } 262 } 263 } 264 265 static void configure_dual_link_mode(struct intel_encoder *encoder, 266 const struct intel_crtc_state *pipe_config) 267 { 268 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 269 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 270 u32 dss_ctl1; 271 272 dss_ctl1 = I915_READ(DSS_CTL1); 273 dss_ctl1 |= SPLITTER_ENABLE; 274 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 275 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 276 277 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 278 const struct drm_display_mode *adjusted_mode = 279 &pipe_config->base.adjusted_mode; 280 u32 dss_ctl2; 281 u16 hactive = adjusted_mode->crtc_hdisplay; 282 u16 dl_buffer_depth; 283 284 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 285 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 286 287 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 288 DRM_ERROR("DL buffer depth exceed max value\n"); 289 290 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 291 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 292 dss_ctl2 = I915_READ(DSS_CTL2); 293 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; 294 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 295 I915_WRITE(DSS_CTL2, dss_ctl2); 296 } else { 297 /* Interleave */ 298 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 299 } 300 301 I915_WRITE(DSS_CTL1, dss_ctl1); 302 } 303 304 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder) 305 { 306 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 307 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 308 enum port port; 309 u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 310 u32 afe_clk_khz; /* 8X Clock */ 311 u32 esc_clk_div_m; 312 313 afe_clk_khz = DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, 314 intel_dsi->lane_count); 315 316 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 317 318 for_each_dsi_port(port, intel_dsi->ports) { 319 I915_WRITE(ICL_DSI_ESC_CLK_DIV(port), 320 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 321 POSTING_READ(ICL_DSI_ESC_CLK_DIV(port)); 322 } 323 324 for_each_dsi_port(port, intel_dsi->ports) { 325 I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port), 326 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 327 POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port)); 328 } 329 } 330 331 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, 332 struct intel_dsi *intel_dsi) 333 { 334 enum port port; 335 336 for_each_dsi_port(port, intel_dsi->ports) { 337 WARN_ON(intel_dsi->io_wakeref[port]); 338 intel_dsi->io_wakeref[port] = 339 intel_display_power_get(dev_priv, 340 port == PORT_A ? 341 POWER_DOMAIN_PORT_DDI_A_IO : 342 POWER_DOMAIN_PORT_DDI_B_IO); 343 } 344 } 345 346 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 347 { 348 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 349 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 350 enum port port; 351 u32 tmp; 352 353 for_each_dsi_port(port, intel_dsi->ports) { 354 tmp = I915_READ(ICL_DSI_IO_MODECTL(port)); 355 tmp |= COMBO_PHY_MODE_DSI; 356 I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp); 357 } 358 359 get_dsi_io_power_domains(dev_priv, intel_dsi); 360 } 361 362 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 363 { 364 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 365 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 366 enum phy phy; 367 368 for_each_dsi_phy(phy, intel_dsi->phys) 369 intel_combo_phy_power_up_lanes(dev_priv, phy, true, 370 intel_dsi->lane_count, false); 371 } 372 373 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 374 { 375 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 376 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 377 enum phy phy; 378 u32 tmp; 379 int lane; 380 381 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 382 for_each_dsi_phy(phy, intel_dsi->phys) { 383 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); 384 tmp &= ~LOADGEN_SELECT; 385 I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp); 386 for (lane = 0; lane <= 3; lane++) { 387 tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); 388 tmp &= ~LOADGEN_SELECT; 389 if (lane != 2) 390 tmp |= LOADGEN_SELECT; 391 I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); 392 } 393 } 394 395 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 396 for_each_dsi_phy(phy, intel_dsi->phys) { 397 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); 398 tmp &= ~FRC_LATENCY_OPTIM_MASK; 399 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 400 I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp); 401 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); 402 tmp &= ~FRC_LATENCY_OPTIM_MASK; 403 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 404 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp); 405 406 /* For EHL set latency optimization for PCS_DW1 lanes */ 407 if (IS_ELKHARTLAKE(dev_priv)) { 408 tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy)); 409 tmp &= ~LATENCY_OPTIM_MASK; 410 tmp |= LATENCY_OPTIM_VAL(0); 411 I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp); 412 413 tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); 414 tmp &= ~LATENCY_OPTIM_MASK; 415 tmp |= LATENCY_OPTIM_VAL(0x1); 416 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp); 417 } 418 } 419 420 } 421 422 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 423 { 424 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 425 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 426 u32 tmp; 427 enum phy phy; 428 429 /* clear common keeper enable bit */ 430 for_each_dsi_phy(phy, intel_dsi->phys) { 431 tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); 432 tmp &= ~COMMON_KEEPER_EN; 433 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp); 434 tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy)); 435 tmp &= ~COMMON_KEEPER_EN; 436 I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp); 437 } 438 439 /* 440 * Set SUS Clock Config bitfield to 11b 441 * Note: loadgen select program is done 442 * as part of lane phy sequence configuration 443 */ 444 for_each_dsi_phy(phy, intel_dsi->phys) { 445 tmp = I915_READ(ICL_PORT_CL_DW5(phy)); 446 tmp |= SUS_CLOCK_CONFIG; 447 I915_WRITE(ICL_PORT_CL_DW5(phy), tmp); 448 } 449 450 /* Clear training enable to change swing values */ 451 for_each_dsi_phy(phy, intel_dsi->phys) { 452 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 453 tmp &= ~TX_TRAINING_EN; 454 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); 455 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); 456 tmp &= ~TX_TRAINING_EN; 457 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); 458 } 459 460 /* Program swing and de-emphasis */ 461 dsi_program_swing_and_deemphasis(encoder); 462 463 /* Set training enable to trigger update */ 464 for_each_dsi_phy(phy, intel_dsi->phys) { 465 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 466 tmp |= TX_TRAINING_EN; 467 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); 468 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); 469 tmp |= TX_TRAINING_EN; 470 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); 471 } 472 } 473 474 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 475 { 476 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 477 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 478 u32 tmp; 479 enum port port; 480 481 for_each_dsi_port(port, intel_dsi->ports) { 482 tmp = I915_READ(DDI_BUF_CTL(port)); 483 tmp |= DDI_BUF_CTL_ENABLE; 484 I915_WRITE(DDI_BUF_CTL(port), tmp); 485 486 if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) & 487 DDI_BUF_IS_IDLE), 488 500)) 489 DRM_ERROR("DDI port:%c buffer idle\n", port_name(port)); 490 } 491 } 492 493 static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder) 494 { 495 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 496 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 497 u32 tmp; 498 enum port port; 499 enum phy phy; 500 501 /* Program T-INIT master registers */ 502 for_each_dsi_port(port, intel_dsi->ports) { 503 tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port)); 504 tmp &= ~MASTER_INIT_TIMER_MASK; 505 tmp |= intel_dsi->init_count; 506 I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp); 507 } 508 509 /* Program DPHY clock lanes timings */ 510 for_each_dsi_port(port, intel_dsi->ports) { 511 I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg); 512 513 /* shadow register inside display core */ 514 I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg); 515 } 516 517 /* Program DPHY data lanes timings */ 518 for_each_dsi_port(port, intel_dsi->ports) { 519 I915_WRITE(DPHY_DATA_TIMING_PARAM(port), 520 intel_dsi->dphy_data_lane_reg); 521 522 /* shadow register inside display core */ 523 I915_WRITE(DSI_DATA_TIMING_PARAM(port), 524 intel_dsi->dphy_data_lane_reg); 525 } 526 527 /* 528 * If DSI link operating at or below an 800 MHz, 529 * TA_SURE should be override and programmed to 530 * a value '0' inside TA_PARAM_REGISTERS otherwise 531 * leave all fields at HW default values. 532 */ 533 if (intel_dsi_bitrate(intel_dsi) <= 800000) { 534 for_each_dsi_port(port, intel_dsi->ports) { 535 tmp = I915_READ(DPHY_TA_TIMING_PARAM(port)); 536 tmp &= ~TA_SURE_MASK; 537 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 538 I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp); 539 540 /* shadow register inside display core */ 541 tmp = I915_READ(DSI_TA_TIMING_PARAM(port)); 542 tmp &= ~TA_SURE_MASK; 543 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 544 I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp); 545 } 546 } 547 548 if (IS_ELKHARTLAKE(dev_priv)) { 549 for_each_dsi_phy(phy, intel_dsi->phys) { 550 tmp = I915_READ(ICL_DPHY_CHKN(phy)); 551 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; 552 I915_WRITE(ICL_DPHY_CHKN(phy), tmp); 553 } 554 } 555 } 556 557 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 558 { 559 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 560 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 561 u32 tmp; 562 enum phy phy; 563 564 mutex_lock(&dev_priv->dpll_lock); 565 tmp = I915_READ(ICL_DPCLKA_CFGCR0); 566 for_each_dsi_phy(phy, intel_dsi->phys) 567 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 568 569 I915_WRITE(ICL_DPCLKA_CFGCR0, tmp); 570 mutex_unlock(&dev_priv->dpll_lock); 571 } 572 573 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 574 { 575 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 576 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 577 u32 tmp; 578 enum phy phy; 579 580 mutex_lock(&dev_priv->dpll_lock); 581 tmp = I915_READ(ICL_DPCLKA_CFGCR0); 582 for_each_dsi_phy(phy, intel_dsi->phys) 583 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 584 585 I915_WRITE(ICL_DPCLKA_CFGCR0, tmp); 586 mutex_unlock(&dev_priv->dpll_lock); 587 } 588 589 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 590 const struct intel_crtc_state *crtc_state) 591 { 592 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 593 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 594 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 595 enum phy phy; 596 u32 val; 597 598 mutex_lock(&dev_priv->dpll_lock); 599 600 val = I915_READ(ICL_DPCLKA_CFGCR0); 601 for_each_dsi_phy(phy, intel_dsi->phys) { 602 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 603 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 604 } 605 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 606 607 for_each_dsi_phy(phy, intel_dsi->phys) { 608 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 609 } 610 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 611 612 POSTING_READ(ICL_DPCLKA_CFGCR0); 613 614 mutex_unlock(&dev_priv->dpll_lock); 615 } 616 617 static void 618 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 619 const struct intel_crtc_state *pipe_config) 620 { 621 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 622 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 623 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 624 enum pipe pipe = intel_crtc->pipe; 625 u32 tmp; 626 enum port port; 627 enum transcoder dsi_trans; 628 629 for_each_dsi_port(port, intel_dsi->ports) { 630 dsi_trans = dsi_port_to_transcoder(port); 631 tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)); 632 633 if (intel_dsi->eotp_pkt) 634 tmp &= ~EOTP_DISABLED; 635 else 636 tmp |= EOTP_DISABLED; 637 638 /* enable link calibration if freq > 1.5Gbps */ 639 if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) { 640 tmp &= ~LINK_CALIBRATION_MASK; 641 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 642 } 643 644 /* configure continuous clock */ 645 tmp &= ~CONTINUOUS_CLK_MASK; 646 if (intel_dsi->clock_stop) 647 tmp |= CLK_ENTER_LP_AFTER_DATA; 648 else 649 tmp |= CLK_HS_CONTINUOUS; 650 651 /* configure buffer threshold limit to minimum */ 652 tmp &= ~PIX_BUF_THRESHOLD_MASK; 653 tmp |= PIX_BUF_THRESHOLD_1_4; 654 655 /* set virtual channel to '0' */ 656 tmp &= ~PIX_VIRT_CHAN_MASK; 657 tmp |= PIX_VIRT_CHAN(0); 658 659 /* program BGR transmission */ 660 if (intel_dsi->bgr_enabled) 661 tmp |= BGR_TRANSMISSION; 662 663 /* select pixel format */ 664 tmp &= ~PIX_FMT_MASK; 665 switch (intel_dsi->pixel_format) { 666 default: 667 MISSING_CASE(intel_dsi->pixel_format); 668 /* fallthrough */ 669 case MIPI_DSI_FMT_RGB565: 670 tmp |= PIX_FMT_RGB565; 671 break; 672 case MIPI_DSI_FMT_RGB666_PACKED: 673 tmp |= PIX_FMT_RGB666_PACKED; 674 break; 675 case MIPI_DSI_FMT_RGB666: 676 tmp |= PIX_FMT_RGB666_LOOSE; 677 break; 678 case MIPI_DSI_FMT_RGB888: 679 tmp |= PIX_FMT_RGB888; 680 break; 681 } 682 683 /* program DSI operation mode */ 684 if (is_vid_mode(intel_dsi)) { 685 tmp &= ~OP_MODE_MASK; 686 switch (intel_dsi->video_mode_format) { 687 default: 688 MISSING_CASE(intel_dsi->video_mode_format); 689 /* fallthrough */ 690 case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS: 691 tmp |= VIDEO_MODE_SYNC_EVENT; 692 break; 693 case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE: 694 tmp |= VIDEO_MODE_SYNC_PULSE; 695 break; 696 } 697 } 698 699 I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 700 } 701 702 /* enable port sync mode if dual link */ 703 if (intel_dsi->dual_link) { 704 for_each_dsi_port(port, intel_dsi->ports) { 705 dsi_trans = dsi_port_to_transcoder(port); 706 tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans)); 707 tmp |= PORT_SYNC_MODE_ENABLE; 708 I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 709 } 710 711 /* configure stream splitting */ 712 configure_dual_link_mode(encoder, pipe_config); 713 } 714 715 for_each_dsi_port(port, intel_dsi->ports) { 716 dsi_trans = dsi_port_to_transcoder(port); 717 718 /* select data lane width */ 719 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); 720 tmp &= ~DDI_PORT_WIDTH_MASK; 721 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); 722 723 /* select input pipe */ 724 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 725 switch (pipe) { 726 default: 727 MISSING_CASE(pipe); 728 /* fallthrough */ 729 case PIPE_A: 730 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 731 break; 732 case PIPE_B: 733 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 734 break; 735 case PIPE_C: 736 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 737 break; 738 } 739 740 /* enable DDI buffer */ 741 tmp |= TRANS_DDI_FUNC_ENABLE; 742 I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 743 } 744 745 /* wait for link ready */ 746 for_each_dsi_port(port, intel_dsi->ports) { 747 dsi_trans = dsi_port_to_transcoder(port); 748 if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) & 749 LINK_READY), 2500)) 750 DRM_ERROR("DSI link not ready\n"); 751 } 752 } 753 754 static void 755 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 756 const struct intel_crtc_state *pipe_config) 757 { 758 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 759 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 760 const struct drm_display_mode *adjusted_mode = 761 &pipe_config->base.adjusted_mode; 762 enum port port; 763 enum transcoder dsi_trans; 764 /* horizontal timings */ 765 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 766 u16 hback_porch; 767 /* vertical timings */ 768 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 769 770 hactive = adjusted_mode->crtc_hdisplay; 771 htotal = adjusted_mode->crtc_htotal; 772 hsync_start = adjusted_mode->crtc_hsync_start; 773 hsync_end = adjusted_mode->crtc_hsync_end; 774 hsync_size = hsync_end - hsync_start; 775 hback_porch = (adjusted_mode->crtc_htotal - 776 adjusted_mode->crtc_hsync_end); 777 vactive = adjusted_mode->crtc_vdisplay; 778 vtotal = adjusted_mode->crtc_vtotal; 779 vsync_start = adjusted_mode->crtc_vsync_start; 780 vsync_end = adjusted_mode->crtc_vsync_end; 781 vsync_shift = hsync_start - htotal / 2; 782 783 if (intel_dsi->dual_link) { 784 hactive /= 2; 785 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 786 hactive += intel_dsi->pixel_overlap; 787 htotal /= 2; 788 } 789 790 /* minimum hactive as per bspec: 256 pixels */ 791 if (adjusted_mode->crtc_hdisplay < 256) 792 DRM_ERROR("hactive is less then 256 pixels\n"); 793 794 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 795 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 796 DRM_ERROR("hactive pixels are not multiple of 4\n"); 797 798 /* program TRANS_HTOTAL register */ 799 for_each_dsi_port(port, intel_dsi->ports) { 800 dsi_trans = dsi_port_to_transcoder(port); 801 I915_WRITE(HTOTAL(dsi_trans), 802 (hactive - 1) | ((htotal - 1) << 16)); 803 } 804 805 /* TRANS_HSYNC register to be programmed only for video mode */ 806 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 807 if (intel_dsi->video_mode_format == 808 VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) { 809 /* BSPEC: hsync size should be atleast 16 pixels */ 810 if (hsync_size < 16) 811 DRM_ERROR("hsync size < 16 pixels\n"); 812 } 813 814 if (hback_porch < 16) 815 DRM_ERROR("hback porch < 16 pixels\n"); 816 817 if (intel_dsi->dual_link) { 818 hsync_start /= 2; 819 hsync_end /= 2; 820 } 821 822 for_each_dsi_port(port, intel_dsi->ports) { 823 dsi_trans = dsi_port_to_transcoder(port); 824 I915_WRITE(HSYNC(dsi_trans), 825 (hsync_start - 1) | ((hsync_end - 1) << 16)); 826 } 827 } 828 829 /* program TRANS_VTOTAL register */ 830 for_each_dsi_port(port, intel_dsi->ports) { 831 dsi_trans = dsi_port_to_transcoder(port); 832 /* 833 * FIXME: Programing this by assuming progressive mode, since 834 * non-interlaced info from VBT is not saved inside 835 * struct drm_display_mode. 836 * For interlace mode: program required pixel minus 2 837 */ 838 I915_WRITE(VTOTAL(dsi_trans), 839 (vactive - 1) | ((vtotal - 1) << 16)); 840 } 841 842 if (vsync_end < vsync_start || vsync_end > vtotal) 843 DRM_ERROR("Invalid vsync_end value\n"); 844 845 if (vsync_start < vactive) 846 DRM_ERROR("vsync_start less than vactive\n"); 847 848 /* program TRANS_VSYNC register */ 849 for_each_dsi_port(port, intel_dsi->ports) { 850 dsi_trans = dsi_port_to_transcoder(port); 851 I915_WRITE(VSYNC(dsi_trans), 852 (vsync_start - 1) | ((vsync_end - 1) << 16)); 853 } 854 855 /* 856 * FIXME: It has to be programmed only for interlaced 857 * modes. Put the check condition here once interlaced 858 * info available as described above. 859 * program TRANS_VSYNCSHIFT register 860 */ 861 for_each_dsi_port(port, intel_dsi->ports) { 862 dsi_trans = dsi_port_to_transcoder(port); 863 I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift); 864 } 865 } 866 867 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 868 { 869 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 870 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 871 enum port port; 872 enum transcoder dsi_trans; 873 u32 tmp; 874 875 for_each_dsi_port(port, intel_dsi->ports) { 876 dsi_trans = dsi_port_to_transcoder(port); 877 tmp = I915_READ(PIPECONF(dsi_trans)); 878 tmp |= PIPECONF_ENABLE; 879 I915_WRITE(PIPECONF(dsi_trans), tmp); 880 881 /* wait for transcoder to be enabled */ 882 if (intel_wait_for_register(&dev_priv->uncore, 883 PIPECONF(dsi_trans), 884 I965_PIPECONF_ACTIVE, 885 I965_PIPECONF_ACTIVE, 10)) 886 DRM_ERROR("DSI transcoder not enabled\n"); 887 } 888 } 889 890 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder) 891 { 892 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 893 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 894 enum port port; 895 enum transcoder dsi_trans; 896 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 897 898 /* 899 * escape clock count calculation: 900 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 901 * UI (nsec) = (10^6)/Bitrate 902 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 903 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 904 */ 905 divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) * 1000; 906 mul = 8 * 1000000; 907 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 908 divisor); 909 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 910 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 911 912 for_each_dsi_port(port, intel_dsi->ports) { 913 dsi_trans = dsi_port_to_transcoder(port); 914 915 /* program hst_tx_timeout */ 916 tmp = I915_READ(DSI_HSTX_TO(dsi_trans)); 917 tmp &= ~HSTX_TIMEOUT_VALUE_MASK; 918 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout); 919 I915_WRITE(DSI_HSTX_TO(dsi_trans), tmp); 920 921 /* FIXME: DSI_CALIB_TO */ 922 923 /* program lp_rx_host timeout */ 924 tmp = I915_READ(DSI_LPRX_HOST_TO(dsi_trans)); 925 tmp &= ~LPRX_TIMEOUT_VALUE_MASK; 926 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout); 927 I915_WRITE(DSI_LPRX_HOST_TO(dsi_trans), tmp); 928 929 /* FIXME: DSI_PWAIT_TO */ 930 931 /* program turn around timeout */ 932 tmp = I915_READ(DSI_TA_TO(dsi_trans)); 933 tmp &= ~TA_TIMEOUT_VALUE_MASK; 934 tmp |= TA_TIMEOUT_VALUE(ta_timeout); 935 I915_WRITE(DSI_TA_TO(dsi_trans), tmp); 936 } 937 } 938 939 static void 940 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 941 const struct intel_crtc_state *pipe_config) 942 { 943 /* step 4a: power up all lanes of the DDI used by DSI */ 944 gen11_dsi_power_up_lanes(encoder); 945 946 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 947 gen11_dsi_config_phy_lanes_sequence(encoder); 948 949 /* step 4c: configure voltage swing and skew */ 950 gen11_dsi_voltage_swing_program_seq(encoder); 951 952 /* enable DDI buffer */ 953 gen11_dsi_enable_ddi_buffer(encoder); 954 955 /* setup D-PHY timings */ 956 gen11_dsi_setup_dphy_timings(encoder); 957 958 /* step 4h: setup DSI protocol timeouts */ 959 gen11_dsi_setup_timeouts(encoder); 960 961 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 962 gen11_dsi_configure_transcoder(encoder, pipe_config); 963 964 /* Step 4l: Gate DDI clocks */ 965 gen11_dsi_gate_clocks(encoder); 966 } 967 968 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 969 { 970 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 971 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 972 struct mipi_dsi_device *dsi; 973 enum port port; 974 enum transcoder dsi_trans; 975 u32 tmp; 976 int ret; 977 978 /* set maximum return packet size */ 979 for_each_dsi_port(port, intel_dsi->ports) { 980 dsi_trans = dsi_port_to_transcoder(port); 981 982 /* 983 * FIXME: This uses the number of DW's currently in the payload 984 * receive queue. This is probably not what we want here. 985 */ 986 tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans)); 987 tmp &= NUMBER_RX_PLOAD_DW_MASK; 988 /* multiply "Number Rx Payload DW" by 4 to get max value */ 989 tmp = tmp * 4; 990 dsi = intel_dsi->dsi_hosts[port]->device; 991 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 992 if (ret < 0) 993 DRM_ERROR("error setting max return pkt size%d\n", tmp); 994 } 995 996 /* panel power on related mipi dsi vbt sequences */ 997 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 998 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 999 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1000 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1001 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1002 1003 /* ensure all panel commands dispatched before enabling transcoder */ 1004 wait_for_cmds_dispatched_to_panel(encoder); 1005 } 1006 1007 static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder, 1008 const struct intel_crtc_state *pipe_config, 1009 const struct drm_connector_state *conn_state) 1010 { 1011 /* step2: enable IO power */ 1012 gen11_dsi_enable_io_power(encoder); 1013 1014 /* step3: enable DSI PLL */ 1015 gen11_dsi_program_esc_clk_div(encoder); 1016 } 1017 1018 static void gen11_dsi_pre_enable(struct intel_encoder *encoder, 1019 const struct intel_crtc_state *pipe_config, 1020 const struct drm_connector_state *conn_state) 1021 { 1022 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 1023 1024 /* step3b */ 1025 gen11_dsi_map_pll(encoder, pipe_config); 1026 1027 /* step4: enable DSI port and DPHY */ 1028 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1029 1030 /* step5: program and powerup panel */ 1031 gen11_dsi_powerup_panel(encoder); 1032 1033 /* step6c: configure transcoder timings */ 1034 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1035 1036 /* step6d: enable dsi transcoder */ 1037 gen11_dsi_enable_transcoder(encoder); 1038 1039 /* step7: enable backlight */ 1040 intel_panel_enable_backlight(pipe_config, conn_state); 1041 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1042 } 1043 1044 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1045 { 1046 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1047 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 1048 enum port port; 1049 enum transcoder dsi_trans; 1050 u32 tmp; 1051 1052 for_each_dsi_port(port, intel_dsi->ports) { 1053 dsi_trans = dsi_port_to_transcoder(port); 1054 1055 /* disable transcoder */ 1056 tmp = I915_READ(PIPECONF(dsi_trans)); 1057 tmp &= ~PIPECONF_ENABLE; 1058 I915_WRITE(PIPECONF(dsi_trans), tmp); 1059 1060 /* wait for transcoder to be disabled */ 1061 if (intel_wait_for_register(&dev_priv->uncore, 1062 PIPECONF(dsi_trans), 1063 I965_PIPECONF_ACTIVE, 0, 50)) 1064 DRM_ERROR("DSI trancoder not disabled\n"); 1065 } 1066 } 1067 1068 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1069 { 1070 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 1071 1072 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1073 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1074 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1075 1076 /* ensure cmds dispatched to panel */ 1077 wait_for_cmds_dispatched_to_panel(encoder); 1078 } 1079 1080 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1081 { 1082 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1083 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 1084 enum port port; 1085 enum transcoder dsi_trans; 1086 u32 tmp; 1087 1088 /* put dsi link in ULPS */ 1089 for_each_dsi_port(port, intel_dsi->ports) { 1090 dsi_trans = dsi_port_to_transcoder(port); 1091 tmp = I915_READ(DSI_LP_MSG(dsi_trans)); 1092 tmp |= LINK_ENTER_ULPS; 1093 tmp &= ~LINK_ULPS_TYPE_LP11; 1094 I915_WRITE(DSI_LP_MSG(dsi_trans), tmp); 1095 1096 if (wait_for_us((I915_READ(DSI_LP_MSG(dsi_trans)) & 1097 LINK_IN_ULPS), 1098 10)) 1099 DRM_ERROR("DSI link not in ULPS\n"); 1100 } 1101 1102 /* disable ddi function */ 1103 for_each_dsi_port(port, intel_dsi->ports) { 1104 dsi_trans = dsi_port_to_transcoder(port); 1105 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); 1106 tmp &= ~TRANS_DDI_FUNC_ENABLE; 1107 I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 1108 } 1109 1110 /* disable port sync mode if dual link */ 1111 if (intel_dsi->dual_link) { 1112 for_each_dsi_port(port, intel_dsi->ports) { 1113 dsi_trans = dsi_port_to_transcoder(port); 1114 tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans)); 1115 tmp &= ~PORT_SYNC_MODE_ENABLE; 1116 I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 1117 } 1118 } 1119 } 1120 1121 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1122 { 1123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1124 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 1125 u32 tmp; 1126 enum port port; 1127 1128 gen11_dsi_ungate_clocks(encoder); 1129 for_each_dsi_port(port, intel_dsi->ports) { 1130 tmp = I915_READ(DDI_BUF_CTL(port)); 1131 tmp &= ~DDI_BUF_CTL_ENABLE; 1132 I915_WRITE(DDI_BUF_CTL(port), tmp); 1133 1134 if (wait_for_us((I915_READ(DDI_BUF_CTL(port)) & 1135 DDI_BUF_IS_IDLE), 1136 8)) 1137 DRM_ERROR("DDI port:%c buffer not idle\n", 1138 port_name(port)); 1139 } 1140 gen11_dsi_gate_clocks(encoder); 1141 } 1142 1143 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1144 { 1145 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1146 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 1147 enum port port; 1148 u32 tmp; 1149 1150 for_each_dsi_port(port, intel_dsi->ports) { 1151 intel_wakeref_t wakeref; 1152 1153 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1154 intel_display_power_put(dev_priv, 1155 port == PORT_A ? 1156 POWER_DOMAIN_PORT_DDI_A_IO : 1157 POWER_DOMAIN_PORT_DDI_B_IO, 1158 wakeref); 1159 } 1160 1161 /* set mode to DDI */ 1162 for_each_dsi_port(port, intel_dsi->ports) { 1163 tmp = I915_READ(ICL_DSI_IO_MODECTL(port)); 1164 tmp &= ~COMBO_PHY_MODE_DSI; 1165 I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp); 1166 } 1167 } 1168 1169 static void gen11_dsi_disable(struct intel_encoder *encoder, 1170 const struct intel_crtc_state *old_crtc_state, 1171 const struct drm_connector_state *old_conn_state) 1172 { 1173 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 1174 1175 /* step1: turn off backlight */ 1176 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1177 intel_panel_disable_backlight(old_conn_state); 1178 1179 /* step2d,e: disable transcoder and wait */ 1180 gen11_dsi_disable_transcoder(encoder); 1181 1182 /* step2f,g: powerdown panel */ 1183 gen11_dsi_powerdown_panel(encoder); 1184 1185 /* step2h,i,j: deconfig trancoder */ 1186 gen11_dsi_deconfigure_trancoder(encoder); 1187 1188 /* step3: disable port */ 1189 gen11_dsi_disable_port(encoder); 1190 1191 /* step4: disable IO power */ 1192 gen11_dsi_disable_io_power(encoder); 1193 } 1194 1195 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1196 struct intel_crtc_state *pipe_config) 1197 { 1198 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 1199 struct drm_display_mode *adjusted_mode = 1200 &pipe_config->base.adjusted_mode; 1201 1202 if (intel_dsi->dual_link) { 1203 adjusted_mode->crtc_hdisplay *= 2; 1204 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1205 adjusted_mode->crtc_hdisplay -= 1206 intel_dsi->pixel_overlap; 1207 adjusted_mode->crtc_htotal *= 2; 1208 } 1209 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1210 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1211 1212 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1213 if (intel_dsi->dual_link) { 1214 adjusted_mode->crtc_hsync_start *= 2; 1215 adjusted_mode->crtc_hsync_end *= 2; 1216 } 1217 } 1218 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1219 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1220 } 1221 1222 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1223 struct intel_crtc_state *pipe_config) 1224 { 1225 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1226 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 1227 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 1228 1229 /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */ 1230 pipe_config->port_clock = 1231 cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state); 1232 1233 pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk; 1234 if (intel_dsi->dual_link) 1235 pipe_config->base.adjusted_mode.crtc_clock *= 2; 1236 1237 gen11_dsi_get_timings(encoder, pipe_config); 1238 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1239 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1240 } 1241 1242 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1243 struct intel_crtc_state *pipe_config, 1244 struct drm_connector_state *conn_state) 1245 { 1246 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 1247 base); 1248 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1249 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 1250 const struct drm_display_mode *fixed_mode = 1251 intel_connector->panel.fixed_mode; 1252 struct drm_display_mode *adjusted_mode = 1253 &pipe_config->base.adjusted_mode; 1254 1255 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1256 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 1257 intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode); 1258 1259 adjusted_mode->flags = 0; 1260 1261 /* Dual link goes to trancoder DSI'0' */ 1262 if (intel_dsi->ports == BIT(PORT_B)) 1263 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1264 else 1265 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1266 1267 pipe_config->clock_set = true; 1268 pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5; 1269 1270 return 0; 1271 } 1272 1273 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1274 struct intel_crtc_state *crtc_state) 1275 { 1276 get_dsi_io_power_domains(to_i915(encoder->base.dev), 1277 enc_to_intel_dsi(&encoder->base)); 1278 } 1279 1280 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1281 enum pipe *pipe) 1282 { 1283 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1284 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 1285 enum transcoder dsi_trans; 1286 intel_wakeref_t wakeref; 1287 enum port port; 1288 bool ret = false; 1289 u32 tmp; 1290 1291 wakeref = intel_display_power_get_if_enabled(dev_priv, 1292 encoder->power_domain); 1293 if (!wakeref) 1294 return false; 1295 1296 for_each_dsi_port(port, intel_dsi->ports) { 1297 dsi_trans = dsi_port_to_transcoder(port); 1298 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); 1299 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1300 case TRANS_DDI_EDP_INPUT_A_ON: 1301 *pipe = PIPE_A; 1302 break; 1303 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1304 *pipe = PIPE_B; 1305 break; 1306 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1307 *pipe = PIPE_C; 1308 break; 1309 default: 1310 DRM_ERROR("Invalid PIPE input\n"); 1311 goto out; 1312 } 1313 1314 tmp = I915_READ(PIPECONF(dsi_trans)); 1315 ret = tmp & PIPECONF_ENABLE; 1316 } 1317 out: 1318 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1319 return ret; 1320 } 1321 1322 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1323 { 1324 intel_encoder_destroy(encoder); 1325 } 1326 1327 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1328 .destroy = gen11_dsi_encoder_destroy, 1329 }; 1330 1331 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1332 .late_register = intel_connector_register, 1333 .early_unregister = intel_connector_unregister, 1334 .destroy = intel_connector_destroy, 1335 .fill_modes = drm_helper_probe_single_connector_modes, 1336 .atomic_get_property = intel_digital_connector_atomic_get_property, 1337 .atomic_set_property = intel_digital_connector_atomic_set_property, 1338 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1339 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1340 }; 1341 1342 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1343 .get_modes = intel_dsi_get_modes, 1344 .mode_valid = intel_dsi_mode_valid, 1345 .atomic_check = intel_digital_connector_atomic_check, 1346 }; 1347 1348 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1349 struct mipi_dsi_device *dsi) 1350 { 1351 return 0; 1352 } 1353 1354 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1355 struct mipi_dsi_device *dsi) 1356 { 1357 return 0; 1358 } 1359 1360 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1361 const struct mipi_dsi_msg *msg) 1362 { 1363 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1364 struct mipi_dsi_packet dsi_pkt; 1365 ssize_t ret; 1366 bool enable_lpdt = false; 1367 1368 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1369 if (ret < 0) 1370 return ret; 1371 1372 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1373 enable_lpdt = true; 1374 1375 /* send packet header */ 1376 ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt); 1377 if (ret < 0) 1378 return ret; 1379 1380 /* only long packet contains payload */ 1381 if (mipi_dsi_packet_format_is_long(msg->type)) { 1382 ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt); 1383 if (ret < 0) 1384 return ret; 1385 } 1386 1387 //TODO: add payload receive code if needed 1388 1389 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1390 1391 return ret; 1392 } 1393 1394 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1395 .attach = gen11_dsi_host_attach, 1396 .detach = gen11_dsi_host_detach, 1397 .transfer = gen11_dsi_host_transfer, 1398 }; 1399 1400 #define ICL_PREPARE_CNT_MAX 0x7 1401 #define ICL_CLK_ZERO_CNT_MAX 0xf 1402 #define ICL_TRAIL_CNT_MAX 0x7 1403 #define ICL_TCLK_PRE_CNT_MAX 0x3 1404 #define ICL_TCLK_POST_CNT_MAX 0x7 1405 #define ICL_HS_ZERO_CNT_MAX 0xf 1406 #define ICL_EXIT_ZERO_CNT_MAX 0x7 1407 1408 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1409 { 1410 struct drm_device *dev = intel_dsi->base.base.dev; 1411 struct drm_i915_private *dev_priv = to_i915(dev); 1412 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 1413 u32 tlpx_ns; 1414 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1415 u32 ths_prepare_ns, tclk_trail_ns; 1416 u32 hs_zero_cnt; 1417 u32 tclk_pre_cnt, tclk_post_cnt; 1418 1419 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1420 1421 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1422 ths_prepare_ns = max(mipi_config->ths_prepare, 1423 mipi_config->tclk_prepare); 1424 1425 /* 1426 * prepare cnt in escape clocks 1427 * this field represents a hexadecimal value with a precision 1428 * of 1.2 – i.e. the most significant bit is the integer 1429 * and the least significant 2 bits are fraction bits. 1430 * so, the field can represent a range of 0.25 to 1.75 1431 */ 1432 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1433 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1434 DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt); 1435 prepare_cnt = ICL_PREPARE_CNT_MAX; 1436 } 1437 1438 /* clk zero count in escape clocks */ 1439 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1440 ths_prepare_ns, tlpx_ns); 1441 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1442 DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1443 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1444 } 1445 1446 /* trail cnt in escape clocks*/ 1447 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1448 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1449 DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt); 1450 trail_cnt = ICL_TRAIL_CNT_MAX; 1451 } 1452 1453 /* tclk pre count in escape clocks */ 1454 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1455 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1456 DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1457 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1458 } 1459 1460 /* tclk post count in escape clocks */ 1461 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); 1462 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { 1463 DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt); 1464 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; 1465 } 1466 1467 /* hs zero cnt in escape clocks */ 1468 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1469 ths_prepare_ns, tlpx_ns); 1470 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1471 DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt); 1472 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1473 } 1474 1475 /* hs exit zero cnt in escape clocks */ 1476 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1477 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1478 DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt); 1479 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1480 } 1481 1482 /* clock lane dphy timings */ 1483 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1484 CLK_PREPARE(prepare_cnt) | 1485 CLK_ZERO_OVERRIDE | 1486 CLK_ZERO(clk_zero_cnt) | 1487 CLK_PRE_OVERRIDE | 1488 CLK_PRE(tclk_pre_cnt) | 1489 CLK_POST_OVERRIDE | 1490 CLK_POST(tclk_post_cnt) | 1491 CLK_TRAIL_OVERRIDE | 1492 CLK_TRAIL(trail_cnt)); 1493 1494 /* data lanes dphy timings */ 1495 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1496 HS_PREPARE(prepare_cnt) | 1497 HS_ZERO_OVERRIDE | 1498 HS_ZERO(hs_zero_cnt) | 1499 HS_TRAIL_OVERRIDE | 1500 HS_TRAIL(trail_cnt) | 1501 HS_EXIT_OVERRIDE | 1502 HS_EXIT(exit_zero_cnt)); 1503 1504 intel_dsi_log_params(intel_dsi); 1505 } 1506 1507 static void icl_dsi_add_properties(struct intel_connector *connector) 1508 { 1509 u32 allowed_scalers; 1510 1511 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | 1512 BIT(DRM_MODE_SCALE_FULLSCREEN) | 1513 BIT(DRM_MODE_SCALE_CENTER); 1514 1515 drm_connector_attach_scaling_mode_property(&connector->base, 1516 allowed_scalers); 1517 1518 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1519 1520 connector->base.display_info.panel_orientation = 1521 intel_dsi_get_panel_orientation(connector); 1522 drm_connector_init_panel_orientation_property(&connector->base, 1523 connector->panel.fixed_mode->hdisplay, 1524 connector->panel.fixed_mode->vdisplay); 1525 } 1526 1527 void icl_dsi_init(struct drm_i915_private *dev_priv) 1528 { 1529 struct drm_device *dev = &dev_priv->drm; 1530 struct intel_dsi *intel_dsi; 1531 struct intel_encoder *encoder; 1532 struct intel_connector *intel_connector; 1533 struct drm_connector *connector; 1534 struct drm_display_mode *fixed_mode; 1535 enum port port; 1536 1537 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1538 return; 1539 1540 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1541 if (!intel_dsi) 1542 return; 1543 1544 intel_connector = intel_connector_alloc(); 1545 if (!intel_connector) { 1546 kfree(intel_dsi); 1547 return; 1548 } 1549 1550 encoder = &intel_dsi->base; 1551 intel_dsi->attached_connector = intel_connector; 1552 connector = &intel_connector->base; 1553 1554 /* register DSI encoder with DRM subsystem */ 1555 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs, 1556 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 1557 1558 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 1559 encoder->pre_enable = gen11_dsi_pre_enable; 1560 encoder->disable = gen11_dsi_disable; 1561 encoder->port = port; 1562 encoder->get_config = gen11_dsi_get_config; 1563 encoder->update_pipe = intel_panel_update_backlight; 1564 encoder->compute_config = gen11_dsi_compute_config; 1565 encoder->get_hw_state = gen11_dsi_get_hw_state; 1566 encoder->type = INTEL_OUTPUT_DSI; 1567 encoder->cloneable = 0; 1568 encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); 1569 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1570 encoder->get_power_domains = gen11_dsi_get_power_domains; 1571 1572 /* register DSI connector with DRM subsystem */ 1573 drm_connector_init(dev, connector, &gen11_dsi_connector_funcs, 1574 DRM_MODE_CONNECTOR_DSI); 1575 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 1576 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1577 connector->interlace_allowed = false; 1578 connector->doublescan_allowed = false; 1579 intel_connector->get_hw_state = intel_connector_get_hw_state; 1580 1581 /* attach connector to encoder */ 1582 intel_connector_attach_encoder(intel_connector, encoder); 1583 1584 mutex_lock(&dev->mode_config.mutex); 1585 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 1586 mutex_unlock(&dev->mode_config.mutex); 1587 1588 if (!fixed_mode) { 1589 DRM_ERROR("DSI fixed mode info missing\n"); 1590 goto err; 1591 } 1592 1593 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 1594 intel_panel_setup_backlight(connector, INVALID_PIPE); 1595 1596 if (dev_priv->vbt.dsi.config->dual_link) 1597 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 1598 else 1599 intel_dsi->ports = BIT(port); 1600 1601 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; 1602 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; 1603 1604 for_each_dsi_port(port, intel_dsi->ports) { 1605 struct intel_dsi_host *host; 1606 1607 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 1608 if (!host) 1609 goto err; 1610 1611 intel_dsi->dsi_hosts[port] = host; 1612 } 1613 1614 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 1615 DRM_DEBUG_KMS("no device found\n"); 1616 goto err; 1617 } 1618 1619 icl_dphy_param_init(intel_dsi); 1620 1621 icl_dsi_add_properties(intel_connector); 1622 return; 1623 1624 err: 1625 drm_encoder_cleanup(&encoder->base); 1626 kfree(intel_dsi); 1627 kfree(intel_connector); 1628 } 1629