1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_mipi_dsi.h> 30 31 #include "intel_atomic.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_ddi.h" 35 #include "intel_dsi.h" 36 #include "intel_panel.h" 37 #include "intel_vdsc.h" 38 39 static inline int header_credits_available(struct drm_i915_private *dev_priv, 40 enum transcoder dsi_trans) 41 { 42 return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 43 >> FREE_HEADER_CREDIT_SHIFT; 44 } 45 46 static inline int payload_credits_available(struct drm_i915_private *dev_priv, 47 enum transcoder dsi_trans) 48 { 49 return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 50 >> FREE_PLOAD_CREDIT_SHIFT; 51 } 52 53 static void wait_for_header_credits(struct drm_i915_private *dev_priv, 54 enum transcoder dsi_trans) 55 { 56 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= 57 MAX_HEADER_CREDIT, 100)) 58 DRM_ERROR("DSI header credits not released\n"); 59 } 60 61 static void wait_for_payload_credits(struct drm_i915_private *dev_priv, 62 enum transcoder dsi_trans) 63 { 64 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= 65 MAX_PLOAD_CREDIT, 100)) 66 DRM_ERROR("DSI payload credits not released\n"); 67 } 68 69 static enum transcoder dsi_port_to_transcoder(enum port port) 70 { 71 if (port == PORT_A) 72 return TRANSCODER_DSI_0; 73 else 74 return TRANSCODER_DSI_1; 75 } 76 77 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 78 { 79 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 80 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 81 struct mipi_dsi_device *dsi; 82 enum port port; 83 enum transcoder dsi_trans; 84 int ret; 85 86 /* wait for header/payload credits to be released */ 87 for_each_dsi_port(port, intel_dsi->ports) { 88 dsi_trans = dsi_port_to_transcoder(port); 89 wait_for_header_credits(dev_priv, dsi_trans); 90 wait_for_payload_credits(dev_priv, dsi_trans); 91 } 92 93 /* send nop DCS command */ 94 for_each_dsi_port(port, intel_dsi->ports) { 95 dsi = intel_dsi->dsi_hosts[port]->device; 96 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 97 dsi->channel = 0; 98 ret = mipi_dsi_dcs_nop(dsi); 99 if (ret < 0) 100 DRM_ERROR("error sending DCS NOP command\n"); 101 } 102 103 /* wait for header credits to be released */ 104 for_each_dsi_port(port, intel_dsi->ports) { 105 dsi_trans = dsi_port_to_transcoder(port); 106 wait_for_header_credits(dev_priv, dsi_trans); 107 } 108 109 /* wait for LP TX in progress bit to be cleared */ 110 for_each_dsi_port(port, intel_dsi->ports) { 111 dsi_trans = dsi_port_to_transcoder(port); 112 if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) & 113 LPTX_IN_PROGRESS), 20)) 114 DRM_ERROR("LPTX bit not cleared\n"); 115 } 116 } 117 118 static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data, 119 u32 len) 120 { 121 struct intel_dsi *intel_dsi = host->intel_dsi; 122 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 123 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 124 int free_credits; 125 int i, j; 126 127 for (i = 0; i < len; i += 4) { 128 u32 tmp = 0; 129 130 free_credits = payload_credits_available(dev_priv, dsi_trans); 131 if (free_credits < 1) { 132 DRM_ERROR("Payload credit not available\n"); 133 return false; 134 } 135 136 for (j = 0; j < min_t(u32, len - i, 4); j++) 137 tmp |= *data++ << 8 * j; 138 139 I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp); 140 } 141 142 return true; 143 } 144 145 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 146 struct mipi_dsi_packet pkt, bool enable_lpdt) 147 { 148 struct intel_dsi *intel_dsi = host->intel_dsi; 149 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 150 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 151 u32 tmp; 152 int free_credits; 153 154 /* check if header credit available */ 155 free_credits = header_credits_available(dev_priv, dsi_trans); 156 if (free_credits < 1) { 157 DRM_ERROR("send pkt header failed, not enough hdr credits\n"); 158 return -1; 159 } 160 161 tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans)); 162 163 if (pkt.payload) 164 tmp |= PAYLOAD_PRESENT; 165 else 166 tmp &= ~PAYLOAD_PRESENT; 167 168 tmp &= ~VBLANK_FENCE; 169 170 if (enable_lpdt) 171 tmp |= LP_DATA_TRANSFER; 172 173 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 174 tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT); 175 tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT); 176 tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT); 177 tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT); 178 I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp); 179 180 return 0; 181 } 182 183 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 184 struct mipi_dsi_packet pkt) 185 { 186 /* payload queue can accept *256 bytes*, check limit */ 187 if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) { 188 DRM_ERROR("payload size exceeds max queue limit\n"); 189 return -1; 190 } 191 192 /* load data into command payload queue */ 193 if (!add_payld_to_queue(host, pkt.payload, 194 pkt.payload_length)) { 195 DRM_ERROR("adding payload to queue failed\n"); 196 return -1; 197 } 198 199 return 0; 200 } 201 202 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 203 { 204 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 205 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 206 enum phy phy; 207 u32 tmp; 208 int lane; 209 210 for_each_dsi_phy(phy, intel_dsi->phys) { 211 /* 212 * Program voltage swing and pre-emphasis level values as per 213 * table in BSPEC under DDI buffer programing 214 */ 215 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 216 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 217 tmp |= SCALING_MODE_SEL(0x2); 218 tmp |= TAP2_DISABLE | TAP3_DISABLE; 219 tmp |= RTERM_SELECT(0x6); 220 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); 221 222 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); 223 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 224 tmp |= SCALING_MODE_SEL(0x2); 225 tmp |= TAP2_DISABLE | TAP3_DISABLE; 226 tmp |= RTERM_SELECT(0x6); 227 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); 228 229 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); 230 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 231 RCOMP_SCALAR_MASK); 232 tmp |= SWING_SEL_UPPER(0x2); 233 tmp |= SWING_SEL_LOWER(0x2); 234 tmp |= RCOMP_SCALAR(0x98); 235 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp); 236 237 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); 238 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 239 RCOMP_SCALAR_MASK); 240 tmp |= SWING_SEL_UPPER(0x2); 241 tmp |= SWING_SEL_LOWER(0x2); 242 tmp |= RCOMP_SCALAR(0x98); 243 I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp); 244 245 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); 246 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 247 CURSOR_COEFF_MASK); 248 tmp |= POST_CURSOR_1(0x0); 249 tmp |= POST_CURSOR_2(0x0); 250 tmp |= CURSOR_COEFF(0x3f); 251 I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp); 252 253 for (lane = 0; lane <= 3; lane++) { 254 /* Bspec: must not use GRP register for write */ 255 tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); 256 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 257 CURSOR_COEFF_MASK); 258 tmp |= POST_CURSOR_1(0x0); 259 tmp |= POST_CURSOR_2(0x0); 260 tmp |= CURSOR_COEFF(0x3f); 261 I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); 262 } 263 } 264 } 265 266 static void configure_dual_link_mode(struct intel_encoder *encoder, 267 const struct intel_crtc_state *pipe_config) 268 { 269 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 270 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 271 u32 dss_ctl1; 272 273 dss_ctl1 = I915_READ(DSS_CTL1); 274 dss_ctl1 |= SPLITTER_ENABLE; 275 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 276 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 277 278 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 279 const struct drm_display_mode *adjusted_mode = 280 &pipe_config->hw.adjusted_mode; 281 u32 dss_ctl2; 282 u16 hactive = adjusted_mode->crtc_hdisplay; 283 u16 dl_buffer_depth; 284 285 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 286 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 287 288 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 289 DRM_ERROR("DL buffer depth exceed max value\n"); 290 291 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 292 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 293 dss_ctl2 = I915_READ(DSS_CTL2); 294 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; 295 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 296 I915_WRITE(DSS_CTL2, dss_ctl2); 297 } else { 298 /* Interleave */ 299 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 300 } 301 302 I915_WRITE(DSS_CTL1, dss_ctl1); 303 } 304 305 /* aka DSI 8X clock */ 306 static int afe_clk(struct intel_encoder *encoder, 307 const struct intel_crtc_state *crtc_state) 308 { 309 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 310 int bpp; 311 312 if (crtc_state->dsc.compression_enable) 313 bpp = crtc_state->dsc.compressed_bpp; 314 else 315 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 316 317 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 318 } 319 320 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 321 const struct intel_crtc_state *crtc_state) 322 { 323 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 324 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 325 enum port port; 326 int afe_clk_khz; 327 u32 esc_clk_div_m; 328 329 afe_clk_khz = afe_clk(encoder, crtc_state); 330 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 331 332 for_each_dsi_port(port, intel_dsi->ports) { 333 I915_WRITE(ICL_DSI_ESC_CLK_DIV(port), 334 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 335 POSTING_READ(ICL_DSI_ESC_CLK_DIV(port)); 336 } 337 338 for_each_dsi_port(port, intel_dsi->ports) { 339 I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port), 340 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 341 POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port)); 342 } 343 } 344 345 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, 346 struct intel_dsi *intel_dsi) 347 { 348 enum port port; 349 350 for_each_dsi_port(port, intel_dsi->ports) { 351 WARN_ON(intel_dsi->io_wakeref[port]); 352 intel_dsi->io_wakeref[port] = 353 intel_display_power_get(dev_priv, 354 port == PORT_A ? 355 POWER_DOMAIN_PORT_DDI_A_IO : 356 POWER_DOMAIN_PORT_DDI_B_IO); 357 } 358 } 359 360 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 361 { 362 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 363 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 364 enum port port; 365 u32 tmp; 366 367 for_each_dsi_port(port, intel_dsi->ports) { 368 tmp = I915_READ(ICL_DSI_IO_MODECTL(port)); 369 tmp |= COMBO_PHY_MODE_DSI; 370 I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp); 371 } 372 373 get_dsi_io_power_domains(dev_priv, intel_dsi); 374 } 375 376 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 377 { 378 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 379 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 380 enum phy phy; 381 382 for_each_dsi_phy(phy, intel_dsi->phys) 383 intel_combo_phy_power_up_lanes(dev_priv, phy, true, 384 intel_dsi->lane_count, false); 385 } 386 387 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 388 { 389 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 390 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 391 enum phy phy; 392 u32 tmp; 393 int lane; 394 395 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 396 for_each_dsi_phy(phy, intel_dsi->phys) { 397 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); 398 tmp &= ~LOADGEN_SELECT; 399 I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp); 400 for (lane = 0; lane <= 3; lane++) { 401 tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); 402 tmp &= ~LOADGEN_SELECT; 403 if (lane != 2) 404 tmp |= LOADGEN_SELECT; 405 I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); 406 } 407 } 408 409 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 410 for_each_dsi_phy(phy, intel_dsi->phys) { 411 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); 412 tmp &= ~FRC_LATENCY_OPTIM_MASK; 413 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 414 I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp); 415 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); 416 tmp &= ~FRC_LATENCY_OPTIM_MASK; 417 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 418 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp); 419 420 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 421 if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) { 422 tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy)); 423 tmp &= ~LATENCY_OPTIM_MASK; 424 tmp |= LATENCY_OPTIM_VAL(0); 425 I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp); 426 427 tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); 428 tmp &= ~LATENCY_OPTIM_MASK; 429 tmp |= LATENCY_OPTIM_VAL(0x1); 430 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp); 431 } 432 } 433 434 } 435 436 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 437 { 438 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 439 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 440 u32 tmp; 441 enum phy phy; 442 443 /* clear common keeper enable bit */ 444 for_each_dsi_phy(phy, intel_dsi->phys) { 445 tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); 446 tmp &= ~COMMON_KEEPER_EN; 447 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp); 448 tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy)); 449 tmp &= ~COMMON_KEEPER_EN; 450 I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp); 451 } 452 453 /* 454 * Set SUS Clock Config bitfield to 11b 455 * Note: loadgen select program is done 456 * as part of lane phy sequence configuration 457 */ 458 for_each_dsi_phy(phy, intel_dsi->phys) { 459 tmp = I915_READ(ICL_PORT_CL_DW5(phy)); 460 tmp |= SUS_CLOCK_CONFIG; 461 I915_WRITE(ICL_PORT_CL_DW5(phy), tmp); 462 } 463 464 /* Clear training enable to change swing values */ 465 for_each_dsi_phy(phy, intel_dsi->phys) { 466 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 467 tmp &= ~TX_TRAINING_EN; 468 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); 469 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); 470 tmp &= ~TX_TRAINING_EN; 471 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); 472 } 473 474 /* Program swing and de-emphasis */ 475 dsi_program_swing_and_deemphasis(encoder); 476 477 /* Set training enable to trigger update */ 478 for_each_dsi_phy(phy, intel_dsi->phys) { 479 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 480 tmp |= TX_TRAINING_EN; 481 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); 482 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); 483 tmp |= TX_TRAINING_EN; 484 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); 485 } 486 } 487 488 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 489 { 490 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 491 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 492 u32 tmp; 493 enum port port; 494 495 for_each_dsi_port(port, intel_dsi->ports) { 496 tmp = I915_READ(DDI_BUF_CTL(port)); 497 tmp |= DDI_BUF_CTL_ENABLE; 498 I915_WRITE(DDI_BUF_CTL(port), tmp); 499 500 if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) & 501 DDI_BUF_IS_IDLE), 502 500)) 503 DRM_ERROR("DDI port:%c buffer idle\n", port_name(port)); 504 } 505 } 506 507 static void 508 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 509 const struct intel_crtc_state *crtc_state) 510 { 511 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 512 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 513 u32 tmp; 514 enum port port; 515 enum phy phy; 516 517 /* Program T-INIT master registers */ 518 for_each_dsi_port(port, intel_dsi->ports) { 519 tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port)); 520 tmp &= ~MASTER_INIT_TIMER_MASK; 521 tmp |= intel_dsi->init_count; 522 I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp); 523 } 524 525 /* Program DPHY clock lanes timings */ 526 for_each_dsi_port(port, intel_dsi->ports) { 527 I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg); 528 529 /* shadow register inside display core */ 530 I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg); 531 } 532 533 /* Program DPHY data lanes timings */ 534 for_each_dsi_port(port, intel_dsi->ports) { 535 I915_WRITE(DPHY_DATA_TIMING_PARAM(port), 536 intel_dsi->dphy_data_lane_reg); 537 538 /* shadow register inside display core */ 539 I915_WRITE(DSI_DATA_TIMING_PARAM(port), 540 intel_dsi->dphy_data_lane_reg); 541 } 542 543 /* 544 * If DSI link operating at or below an 800 MHz, 545 * TA_SURE should be override and programmed to 546 * a value '0' inside TA_PARAM_REGISTERS otherwise 547 * leave all fields at HW default values. 548 */ 549 if (IS_GEN(dev_priv, 11)) { 550 if (afe_clk(encoder, crtc_state) <= 800000) { 551 for_each_dsi_port(port, intel_dsi->ports) { 552 tmp = I915_READ(DPHY_TA_TIMING_PARAM(port)); 553 tmp &= ~TA_SURE_MASK; 554 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 555 I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp); 556 557 /* shadow register inside display core */ 558 tmp = I915_READ(DSI_TA_TIMING_PARAM(port)); 559 tmp &= ~TA_SURE_MASK; 560 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 561 I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp); 562 } 563 } 564 } 565 566 if (IS_ELKHARTLAKE(dev_priv)) { 567 for_each_dsi_phy(phy, intel_dsi->phys) { 568 tmp = I915_READ(ICL_DPHY_CHKN(phy)); 569 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; 570 I915_WRITE(ICL_DPHY_CHKN(phy), tmp); 571 } 572 } 573 } 574 575 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 576 { 577 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 578 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 579 u32 tmp; 580 enum phy phy; 581 582 mutex_lock(&dev_priv->dpll_lock); 583 tmp = I915_READ(ICL_DPCLKA_CFGCR0); 584 for_each_dsi_phy(phy, intel_dsi->phys) 585 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 586 587 I915_WRITE(ICL_DPCLKA_CFGCR0, tmp); 588 mutex_unlock(&dev_priv->dpll_lock); 589 } 590 591 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 592 { 593 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 594 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 595 u32 tmp; 596 enum phy phy; 597 598 mutex_lock(&dev_priv->dpll_lock); 599 tmp = I915_READ(ICL_DPCLKA_CFGCR0); 600 for_each_dsi_phy(phy, intel_dsi->phys) 601 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 602 603 I915_WRITE(ICL_DPCLKA_CFGCR0, tmp); 604 mutex_unlock(&dev_priv->dpll_lock); 605 } 606 607 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 608 const struct intel_crtc_state *crtc_state) 609 { 610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 611 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 612 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 613 enum phy phy; 614 u32 val; 615 616 mutex_lock(&dev_priv->dpll_lock); 617 618 val = I915_READ(ICL_DPCLKA_CFGCR0); 619 for_each_dsi_phy(phy, intel_dsi->phys) { 620 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 621 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 622 } 623 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 624 625 for_each_dsi_phy(phy, intel_dsi->phys) { 626 if (INTEL_GEN(dev_priv) >= 12) 627 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 628 else 629 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 630 } 631 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 632 633 POSTING_READ(ICL_DPCLKA_CFGCR0); 634 635 mutex_unlock(&dev_priv->dpll_lock); 636 } 637 638 static void 639 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 640 const struct intel_crtc_state *pipe_config) 641 { 642 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 643 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 644 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 645 enum pipe pipe = intel_crtc->pipe; 646 u32 tmp; 647 enum port port; 648 enum transcoder dsi_trans; 649 650 for_each_dsi_port(port, intel_dsi->ports) { 651 dsi_trans = dsi_port_to_transcoder(port); 652 tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)); 653 654 if (intel_dsi->eotp_pkt) 655 tmp &= ~EOTP_DISABLED; 656 else 657 tmp |= EOTP_DISABLED; 658 659 /* enable link calibration if freq > 1.5Gbps */ 660 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 661 tmp &= ~LINK_CALIBRATION_MASK; 662 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 663 } 664 665 /* configure continuous clock */ 666 tmp &= ~CONTINUOUS_CLK_MASK; 667 if (intel_dsi->clock_stop) 668 tmp |= CLK_ENTER_LP_AFTER_DATA; 669 else 670 tmp |= CLK_HS_CONTINUOUS; 671 672 /* configure buffer threshold limit to minimum */ 673 tmp &= ~PIX_BUF_THRESHOLD_MASK; 674 tmp |= PIX_BUF_THRESHOLD_1_4; 675 676 /* set virtual channel to '0' */ 677 tmp &= ~PIX_VIRT_CHAN_MASK; 678 tmp |= PIX_VIRT_CHAN(0); 679 680 /* program BGR transmission */ 681 if (intel_dsi->bgr_enabled) 682 tmp |= BGR_TRANSMISSION; 683 684 /* select pixel format */ 685 tmp &= ~PIX_FMT_MASK; 686 if (pipe_config->dsc.compression_enable) { 687 tmp |= PIX_FMT_COMPRESSED; 688 } else { 689 switch (intel_dsi->pixel_format) { 690 default: 691 MISSING_CASE(intel_dsi->pixel_format); 692 /* fallthrough */ 693 case MIPI_DSI_FMT_RGB565: 694 tmp |= PIX_FMT_RGB565; 695 break; 696 case MIPI_DSI_FMT_RGB666_PACKED: 697 tmp |= PIX_FMT_RGB666_PACKED; 698 break; 699 case MIPI_DSI_FMT_RGB666: 700 tmp |= PIX_FMT_RGB666_LOOSE; 701 break; 702 case MIPI_DSI_FMT_RGB888: 703 tmp |= PIX_FMT_RGB888; 704 break; 705 } 706 } 707 708 if (INTEL_GEN(dev_priv) >= 12) { 709 if (is_vid_mode(intel_dsi)) 710 tmp |= BLANKING_PACKET_ENABLE; 711 } 712 713 /* program DSI operation mode */ 714 if (is_vid_mode(intel_dsi)) { 715 tmp &= ~OP_MODE_MASK; 716 switch (intel_dsi->video_mode_format) { 717 default: 718 MISSING_CASE(intel_dsi->video_mode_format); 719 /* fallthrough */ 720 case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS: 721 tmp |= VIDEO_MODE_SYNC_EVENT; 722 break; 723 case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE: 724 tmp |= VIDEO_MODE_SYNC_PULSE; 725 break; 726 } 727 } 728 729 I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 730 } 731 732 /* enable port sync mode if dual link */ 733 if (intel_dsi->dual_link) { 734 for_each_dsi_port(port, intel_dsi->ports) { 735 dsi_trans = dsi_port_to_transcoder(port); 736 tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans)); 737 tmp |= PORT_SYNC_MODE_ENABLE; 738 I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 739 } 740 741 /* configure stream splitting */ 742 configure_dual_link_mode(encoder, pipe_config); 743 } 744 745 for_each_dsi_port(port, intel_dsi->ports) { 746 dsi_trans = dsi_port_to_transcoder(port); 747 748 /* select data lane width */ 749 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); 750 tmp &= ~DDI_PORT_WIDTH_MASK; 751 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); 752 753 /* select input pipe */ 754 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 755 switch (pipe) { 756 default: 757 MISSING_CASE(pipe); 758 /* fallthrough */ 759 case PIPE_A: 760 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 761 break; 762 case PIPE_B: 763 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 764 break; 765 case PIPE_C: 766 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 767 break; 768 case PIPE_D: 769 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 770 break; 771 } 772 773 /* enable DDI buffer */ 774 tmp |= TRANS_DDI_FUNC_ENABLE; 775 I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 776 } 777 778 /* wait for link ready */ 779 for_each_dsi_port(port, intel_dsi->ports) { 780 dsi_trans = dsi_port_to_transcoder(port); 781 if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) & 782 LINK_READY), 2500)) 783 DRM_ERROR("DSI link not ready\n"); 784 } 785 } 786 787 static void 788 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 789 const struct intel_crtc_state *crtc_state) 790 { 791 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 792 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 793 const struct drm_display_mode *adjusted_mode = 794 &crtc_state->hw.adjusted_mode; 795 enum port port; 796 enum transcoder dsi_trans; 797 /* horizontal timings */ 798 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 799 u16 hback_porch; 800 /* vertical timings */ 801 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 802 int mul = 1, div = 1; 803 804 /* 805 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 806 * for slower link speed if DSC is enabled. 807 * 808 * The compression frequency ratio is the ratio between compressed and 809 * non-compressed link speeds, and simplifies down to the ratio between 810 * compressed and non-compressed bpp. 811 */ 812 if (crtc_state->dsc.compression_enable) { 813 mul = crtc_state->dsc.compressed_bpp; 814 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 815 } 816 817 hactive = adjusted_mode->crtc_hdisplay; 818 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 819 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 820 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 821 hsync_size = hsync_end - hsync_start; 822 hback_porch = (adjusted_mode->crtc_htotal - 823 adjusted_mode->crtc_hsync_end); 824 vactive = adjusted_mode->crtc_vdisplay; 825 vtotal = adjusted_mode->crtc_vtotal; 826 vsync_start = adjusted_mode->crtc_vsync_start; 827 vsync_end = adjusted_mode->crtc_vsync_end; 828 vsync_shift = hsync_start - htotal / 2; 829 830 if (intel_dsi->dual_link) { 831 hactive /= 2; 832 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 833 hactive += intel_dsi->pixel_overlap; 834 htotal /= 2; 835 } 836 837 /* minimum hactive as per bspec: 256 pixels */ 838 if (adjusted_mode->crtc_hdisplay < 256) 839 DRM_ERROR("hactive is less then 256 pixels\n"); 840 841 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 842 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 843 DRM_ERROR("hactive pixels are not multiple of 4\n"); 844 845 /* program TRANS_HTOTAL register */ 846 for_each_dsi_port(port, intel_dsi->ports) { 847 dsi_trans = dsi_port_to_transcoder(port); 848 I915_WRITE(HTOTAL(dsi_trans), 849 (hactive - 1) | ((htotal - 1) << 16)); 850 } 851 852 /* TRANS_HSYNC register to be programmed only for video mode */ 853 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 854 if (intel_dsi->video_mode_format == 855 VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) { 856 /* BSPEC: hsync size should be atleast 16 pixels */ 857 if (hsync_size < 16) 858 DRM_ERROR("hsync size < 16 pixels\n"); 859 } 860 861 if (hback_porch < 16) 862 DRM_ERROR("hback porch < 16 pixels\n"); 863 864 if (intel_dsi->dual_link) { 865 hsync_start /= 2; 866 hsync_end /= 2; 867 } 868 869 for_each_dsi_port(port, intel_dsi->ports) { 870 dsi_trans = dsi_port_to_transcoder(port); 871 I915_WRITE(HSYNC(dsi_trans), 872 (hsync_start - 1) | ((hsync_end - 1) << 16)); 873 } 874 } 875 876 /* program TRANS_VTOTAL register */ 877 for_each_dsi_port(port, intel_dsi->ports) { 878 dsi_trans = dsi_port_to_transcoder(port); 879 /* 880 * FIXME: Programing this by assuming progressive mode, since 881 * non-interlaced info from VBT is not saved inside 882 * struct drm_display_mode. 883 * For interlace mode: program required pixel minus 2 884 */ 885 I915_WRITE(VTOTAL(dsi_trans), 886 (vactive - 1) | ((vtotal - 1) << 16)); 887 } 888 889 if (vsync_end < vsync_start || vsync_end > vtotal) 890 DRM_ERROR("Invalid vsync_end value\n"); 891 892 if (vsync_start < vactive) 893 DRM_ERROR("vsync_start less than vactive\n"); 894 895 /* program TRANS_VSYNC register */ 896 for_each_dsi_port(port, intel_dsi->ports) { 897 dsi_trans = dsi_port_to_transcoder(port); 898 I915_WRITE(VSYNC(dsi_trans), 899 (vsync_start - 1) | ((vsync_end - 1) << 16)); 900 } 901 902 /* 903 * FIXME: It has to be programmed only for interlaced 904 * modes. Put the check condition here once interlaced 905 * info available as described above. 906 * program TRANS_VSYNCSHIFT register 907 */ 908 for_each_dsi_port(port, intel_dsi->ports) { 909 dsi_trans = dsi_port_to_transcoder(port); 910 I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift); 911 } 912 913 /* program TRANS_VBLANK register, should be same as vtotal programmed */ 914 if (INTEL_GEN(dev_priv) >= 12) { 915 for_each_dsi_port(port, intel_dsi->ports) { 916 dsi_trans = dsi_port_to_transcoder(port); 917 I915_WRITE(VBLANK(dsi_trans), 918 (vactive - 1) | ((vtotal - 1) << 16)); 919 } 920 } 921 } 922 923 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 924 { 925 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 926 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 927 enum port port; 928 enum transcoder dsi_trans; 929 u32 tmp; 930 931 for_each_dsi_port(port, intel_dsi->ports) { 932 dsi_trans = dsi_port_to_transcoder(port); 933 tmp = I915_READ(PIPECONF(dsi_trans)); 934 tmp |= PIPECONF_ENABLE; 935 I915_WRITE(PIPECONF(dsi_trans), tmp); 936 937 /* wait for transcoder to be enabled */ 938 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), 939 I965_PIPECONF_ACTIVE, 10)) 940 DRM_ERROR("DSI transcoder not enabled\n"); 941 } 942 } 943 944 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 945 const struct intel_crtc_state *crtc_state) 946 { 947 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 948 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 949 enum port port; 950 enum transcoder dsi_trans; 951 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 952 953 /* 954 * escape clock count calculation: 955 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 956 * UI (nsec) = (10^6)/Bitrate 957 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 958 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 959 */ 960 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 961 mul = 8 * 1000000; 962 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 963 divisor); 964 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 965 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 966 967 for_each_dsi_port(port, intel_dsi->ports) { 968 dsi_trans = dsi_port_to_transcoder(port); 969 970 /* program hst_tx_timeout */ 971 tmp = I915_READ(DSI_HSTX_TO(dsi_trans)); 972 tmp &= ~HSTX_TIMEOUT_VALUE_MASK; 973 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout); 974 I915_WRITE(DSI_HSTX_TO(dsi_trans), tmp); 975 976 /* FIXME: DSI_CALIB_TO */ 977 978 /* program lp_rx_host timeout */ 979 tmp = I915_READ(DSI_LPRX_HOST_TO(dsi_trans)); 980 tmp &= ~LPRX_TIMEOUT_VALUE_MASK; 981 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout); 982 I915_WRITE(DSI_LPRX_HOST_TO(dsi_trans), tmp); 983 984 /* FIXME: DSI_PWAIT_TO */ 985 986 /* program turn around timeout */ 987 tmp = I915_READ(DSI_TA_TO(dsi_trans)); 988 tmp &= ~TA_TIMEOUT_VALUE_MASK; 989 tmp |= TA_TIMEOUT_VALUE(ta_timeout); 990 I915_WRITE(DSI_TA_TO(dsi_trans), tmp); 991 } 992 } 993 994 static void 995 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 996 const struct intel_crtc_state *crtc_state) 997 { 998 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 999 1000 /* step 4a: power up all lanes of the DDI used by DSI */ 1001 gen11_dsi_power_up_lanes(encoder); 1002 1003 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1004 gen11_dsi_config_phy_lanes_sequence(encoder); 1005 1006 /* step 4c: configure voltage swing and skew */ 1007 gen11_dsi_voltage_swing_program_seq(encoder); 1008 1009 /* enable DDI buffer */ 1010 gen11_dsi_enable_ddi_buffer(encoder); 1011 1012 /* setup D-PHY timings */ 1013 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1014 1015 /* step 4h: setup DSI protocol timeouts */ 1016 gen11_dsi_setup_timeouts(encoder, crtc_state); 1017 1018 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1019 gen11_dsi_configure_transcoder(encoder, crtc_state); 1020 1021 /* Step 4l: Gate DDI clocks */ 1022 if (IS_GEN(dev_priv, 11)) 1023 gen11_dsi_gate_clocks(encoder); 1024 } 1025 1026 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1027 { 1028 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1029 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1030 struct mipi_dsi_device *dsi; 1031 enum port port; 1032 enum transcoder dsi_trans; 1033 u32 tmp; 1034 int ret; 1035 1036 /* set maximum return packet size */ 1037 for_each_dsi_port(port, intel_dsi->ports) { 1038 dsi_trans = dsi_port_to_transcoder(port); 1039 1040 /* 1041 * FIXME: This uses the number of DW's currently in the payload 1042 * receive queue. This is probably not what we want here. 1043 */ 1044 tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans)); 1045 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1046 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1047 tmp = tmp * 4; 1048 dsi = intel_dsi->dsi_hosts[port]->device; 1049 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1050 if (ret < 0) 1051 DRM_ERROR("error setting max return pkt size%d\n", tmp); 1052 } 1053 1054 /* panel power on related mipi dsi vbt sequences */ 1055 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1056 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 1057 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1058 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1059 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1060 1061 /* ensure all panel commands dispatched before enabling transcoder */ 1062 wait_for_cmds_dispatched_to_panel(encoder); 1063 } 1064 1065 static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder, 1066 const struct intel_crtc_state *crtc_state, 1067 const struct drm_connector_state *conn_state) 1068 { 1069 /* step2: enable IO power */ 1070 gen11_dsi_enable_io_power(encoder); 1071 1072 /* step3: enable DSI PLL */ 1073 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1074 } 1075 1076 static void gen11_dsi_pre_enable(struct intel_encoder *encoder, 1077 const struct intel_crtc_state *pipe_config, 1078 const struct drm_connector_state *conn_state) 1079 { 1080 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1081 1082 /* step3b */ 1083 gen11_dsi_map_pll(encoder, pipe_config); 1084 1085 /* step4: enable DSI port and DPHY */ 1086 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1087 1088 /* step5: program and powerup panel */ 1089 gen11_dsi_powerup_panel(encoder); 1090 1091 intel_dsc_enable(encoder, pipe_config); 1092 1093 /* step6c: configure transcoder timings */ 1094 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1095 1096 /* step6d: enable dsi transcoder */ 1097 gen11_dsi_enable_transcoder(encoder); 1098 1099 /* step7: enable backlight */ 1100 intel_panel_enable_backlight(pipe_config, conn_state); 1101 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1102 } 1103 1104 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1105 { 1106 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1107 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1108 enum port port; 1109 enum transcoder dsi_trans; 1110 u32 tmp; 1111 1112 for_each_dsi_port(port, intel_dsi->ports) { 1113 dsi_trans = dsi_port_to_transcoder(port); 1114 1115 /* disable transcoder */ 1116 tmp = I915_READ(PIPECONF(dsi_trans)); 1117 tmp &= ~PIPECONF_ENABLE; 1118 I915_WRITE(PIPECONF(dsi_trans), tmp); 1119 1120 /* wait for transcoder to be disabled */ 1121 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), 1122 I965_PIPECONF_ACTIVE, 50)) 1123 DRM_ERROR("DSI trancoder not disabled\n"); 1124 } 1125 } 1126 1127 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1128 { 1129 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1130 1131 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1132 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1133 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1134 1135 /* ensure cmds dispatched to panel */ 1136 wait_for_cmds_dispatched_to_panel(encoder); 1137 } 1138 1139 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1140 { 1141 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1142 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1143 enum port port; 1144 enum transcoder dsi_trans; 1145 u32 tmp; 1146 1147 /* put dsi link in ULPS */ 1148 for_each_dsi_port(port, intel_dsi->ports) { 1149 dsi_trans = dsi_port_to_transcoder(port); 1150 tmp = I915_READ(DSI_LP_MSG(dsi_trans)); 1151 tmp |= LINK_ENTER_ULPS; 1152 tmp &= ~LINK_ULPS_TYPE_LP11; 1153 I915_WRITE(DSI_LP_MSG(dsi_trans), tmp); 1154 1155 if (wait_for_us((I915_READ(DSI_LP_MSG(dsi_trans)) & 1156 LINK_IN_ULPS), 1157 10)) 1158 DRM_ERROR("DSI link not in ULPS\n"); 1159 } 1160 1161 /* disable ddi function */ 1162 for_each_dsi_port(port, intel_dsi->ports) { 1163 dsi_trans = dsi_port_to_transcoder(port); 1164 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); 1165 tmp &= ~TRANS_DDI_FUNC_ENABLE; 1166 I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 1167 } 1168 1169 /* disable port sync mode if dual link */ 1170 if (intel_dsi->dual_link) { 1171 for_each_dsi_port(port, intel_dsi->ports) { 1172 dsi_trans = dsi_port_to_transcoder(port); 1173 tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans)); 1174 tmp &= ~PORT_SYNC_MODE_ENABLE; 1175 I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 1176 } 1177 } 1178 } 1179 1180 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1181 { 1182 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1183 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1184 u32 tmp; 1185 enum port port; 1186 1187 gen11_dsi_ungate_clocks(encoder); 1188 for_each_dsi_port(port, intel_dsi->ports) { 1189 tmp = I915_READ(DDI_BUF_CTL(port)); 1190 tmp &= ~DDI_BUF_CTL_ENABLE; 1191 I915_WRITE(DDI_BUF_CTL(port), tmp); 1192 1193 if (wait_for_us((I915_READ(DDI_BUF_CTL(port)) & 1194 DDI_BUF_IS_IDLE), 1195 8)) 1196 DRM_ERROR("DDI port:%c buffer not idle\n", 1197 port_name(port)); 1198 } 1199 gen11_dsi_gate_clocks(encoder); 1200 } 1201 1202 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1203 { 1204 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1205 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1206 enum port port; 1207 u32 tmp; 1208 1209 for_each_dsi_port(port, intel_dsi->ports) { 1210 intel_wakeref_t wakeref; 1211 1212 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1213 intel_display_power_put(dev_priv, 1214 port == PORT_A ? 1215 POWER_DOMAIN_PORT_DDI_A_IO : 1216 POWER_DOMAIN_PORT_DDI_B_IO, 1217 wakeref); 1218 } 1219 1220 /* set mode to DDI */ 1221 for_each_dsi_port(port, intel_dsi->ports) { 1222 tmp = I915_READ(ICL_DSI_IO_MODECTL(port)); 1223 tmp &= ~COMBO_PHY_MODE_DSI; 1224 I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp); 1225 } 1226 } 1227 1228 static void gen11_dsi_disable(struct intel_encoder *encoder, 1229 const struct intel_crtc_state *old_crtc_state, 1230 const struct drm_connector_state *old_conn_state) 1231 { 1232 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1233 1234 /* step1: turn off backlight */ 1235 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1236 intel_panel_disable_backlight(old_conn_state); 1237 1238 /* step2d,e: disable transcoder and wait */ 1239 gen11_dsi_disable_transcoder(encoder); 1240 1241 /* step2f,g: powerdown panel */ 1242 gen11_dsi_powerdown_panel(encoder); 1243 1244 /* step2h,i,j: deconfig trancoder */ 1245 gen11_dsi_deconfigure_trancoder(encoder); 1246 1247 /* step3: disable port */ 1248 gen11_dsi_disable_port(encoder); 1249 1250 /* step4: disable IO power */ 1251 gen11_dsi_disable_io_power(encoder); 1252 } 1253 1254 static void gen11_dsi_post_disable(struct intel_encoder *encoder, 1255 const struct intel_crtc_state *old_crtc_state, 1256 const struct drm_connector_state *old_conn_state) 1257 { 1258 intel_crtc_vblank_off(old_crtc_state); 1259 1260 intel_dsc_disable(old_crtc_state); 1261 1262 skl_scaler_disable(old_crtc_state); 1263 } 1264 1265 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1266 struct drm_display_mode *mode) 1267 { 1268 /* FIXME: DSC? */ 1269 return intel_dsi_mode_valid(connector, mode); 1270 } 1271 1272 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1273 struct intel_crtc_state *pipe_config) 1274 { 1275 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1276 struct drm_display_mode *adjusted_mode = 1277 &pipe_config->hw.adjusted_mode; 1278 1279 if (pipe_config->dsc.compressed_bpp) { 1280 int div = pipe_config->dsc.compressed_bpp; 1281 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1282 1283 adjusted_mode->crtc_htotal = 1284 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1285 adjusted_mode->crtc_hsync_start = 1286 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1287 adjusted_mode->crtc_hsync_end = 1288 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1289 } 1290 1291 if (intel_dsi->dual_link) { 1292 adjusted_mode->crtc_hdisplay *= 2; 1293 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1294 adjusted_mode->crtc_hdisplay -= 1295 intel_dsi->pixel_overlap; 1296 adjusted_mode->crtc_htotal *= 2; 1297 } 1298 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1299 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1300 1301 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1302 if (intel_dsi->dual_link) { 1303 adjusted_mode->crtc_hsync_start *= 2; 1304 adjusted_mode->crtc_hsync_end *= 2; 1305 } 1306 } 1307 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1308 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1309 } 1310 1311 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1312 struct intel_crtc_state *pipe_config) 1313 { 1314 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1315 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1316 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1317 1318 intel_dsc_get_config(encoder, pipe_config); 1319 1320 /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */ 1321 pipe_config->port_clock = 1322 cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state); 1323 1324 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1325 if (intel_dsi->dual_link) 1326 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1327 1328 gen11_dsi_get_timings(encoder, pipe_config); 1329 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1330 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1331 } 1332 1333 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1334 struct intel_crtc_state *crtc_state) 1335 { 1336 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1337 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1338 int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10; 1339 bool use_dsc; 1340 int ret; 1341 1342 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1343 if (!use_dsc) 1344 return 0; 1345 1346 if (crtc_state->pipe_bpp < 8 * 3) 1347 return -EINVAL; 1348 1349 /* FIXME: split only when necessary */ 1350 if (crtc_state->dsc.slice_count > 1) 1351 crtc_state->dsc.dsc_split = true; 1352 1353 vdsc_cfg->convert_rgb = true; 1354 1355 ret = intel_dsc_compute_params(encoder, crtc_state); 1356 if (ret) 1357 return ret; 1358 1359 /* DSI specific sanity checks on the common code */ 1360 WARN_ON(vdsc_cfg->vbr_enable); 1361 WARN_ON(vdsc_cfg->simple_422); 1362 WARN_ON(vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1363 WARN_ON(vdsc_cfg->slice_height < 8); 1364 WARN_ON(vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1365 1366 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1367 if (ret) 1368 return ret; 1369 1370 crtc_state->dsc.compression_enable = true; 1371 1372 return 0; 1373 } 1374 1375 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1376 struct intel_crtc_state *pipe_config, 1377 struct drm_connector_state *conn_state) 1378 { 1379 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 1380 base); 1381 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1382 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1383 const struct drm_display_mode *fixed_mode = 1384 intel_connector->panel.fixed_mode; 1385 struct drm_display_mode *adjusted_mode = 1386 &pipe_config->hw.adjusted_mode; 1387 1388 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1389 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 1390 intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode); 1391 1392 adjusted_mode->flags = 0; 1393 1394 /* Dual link goes to trancoder DSI'0' */ 1395 if (intel_dsi->ports == BIT(PORT_B)) 1396 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1397 else 1398 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1399 1400 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1401 pipe_config->pipe_bpp = 24; 1402 else 1403 pipe_config->pipe_bpp = 18; 1404 1405 pipe_config->clock_set = true; 1406 1407 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1408 DRM_DEBUG_KMS("Attempting to use DSC failed\n"); 1409 1410 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1411 1412 return 0; 1413 } 1414 1415 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1416 struct intel_crtc_state *crtc_state) 1417 { 1418 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1419 1420 get_dsi_io_power_domains(i915, 1421 enc_to_intel_dsi(encoder)); 1422 1423 if (crtc_state->dsc.compression_enable) 1424 intel_display_power_get(i915, 1425 intel_dsc_power_domain(crtc_state)); 1426 } 1427 1428 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1429 enum pipe *pipe) 1430 { 1431 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1432 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1433 enum transcoder dsi_trans; 1434 intel_wakeref_t wakeref; 1435 enum port port; 1436 bool ret = false; 1437 u32 tmp; 1438 1439 wakeref = intel_display_power_get_if_enabled(dev_priv, 1440 encoder->power_domain); 1441 if (!wakeref) 1442 return false; 1443 1444 for_each_dsi_port(port, intel_dsi->ports) { 1445 dsi_trans = dsi_port_to_transcoder(port); 1446 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); 1447 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1448 case TRANS_DDI_EDP_INPUT_A_ON: 1449 *pipe = PIPE_A; 1450 break; 1451 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1452 *pipe = PIPE_B; 1453 break; 1454 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1455 *pipe = PIPE_C; 1456 break; 1457 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1458 *pipe = PIPE_D; 1459 break; 1460 default: 1461 DRM_ERROR("Invalid PIPE input\n"); 1462 goto out; 1463 } 1464 1465 tmp = I915_READ(PIPECONF(dsi_trans)); 1466 ret = tmp & PIPECONF_ENABLE; 1467 } 1468 out: 1469 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1470 return ret; 1471 } 1472 1473 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1474 { 1475 intel_encoder_destroy(encoder); 1476 } 1477 1478 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1479 .destroy = gen11_dsi_encoder_destroy, 1480 }; 1481 1482 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1483 .late_register = intel_connector_register, 1484 .early_unregister = intel_connector_unregister, 1485 .destroy = intel_connector_destroy, 1486 .fill_modes = drm_helper_probe_single_connector_modes, 1487 .atomic_get_property = intel_digital_connector_atomic_get_property, 1488 .atomic_set_property = intel_digital_connector_atomic_set_property, 1489 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1490 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1491 }; 1492 1493 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1494 .get_modes = intel_dsi_get_modes, 1495 .mode_valid = gen11_dsi_mode_valid, 1496 .atomic_check = intel_digital_connector_atomic_check, 1497 }; 1498 1499 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1500 struct mipi_dsi_device *dsi) 1501 { 1502 return 0; 1503 } 1504 1505 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1506 struct mipi_dsi_device *dsi) 1507 { 1508 return 0; 1509 } 1510 1511 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1512 const struct mipi_dsi_msg *msg) 1513 { 1514 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1515 struct mipi_dsi_packet dsi_pkt; 1516 ssize_t ret; 1517 bool enable_lpdt = false; 1518 1519 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1520 if (ret < 0) 1521 return ret; 1522 1523 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1524 enable_lpdt = true; 1525 1526 /* send packet header */ 1527 ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt); 1528 if (ret < 0) 1529 return ret; 1530 1531 /* only long packet contains payload */ 1532 if (mipi_dsi_packet_format_is_long(msg->type)) { 1533 ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt); 1534 if (ret < 0) 1535 return ret; 1536 } 1537 1538 //TODO: add payload receive code if needed 1539 1540 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1541 1542 return ret; 1543 } 1544 1545 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1546 .attach = gen11_dsi_host_attach, 1547 .detach = gen11_dsi_host_detach, 1548 .transfer = gen11_dsi_host_transfer, 1549 }; 1550 1551 #define ICL_PREPARE_CNT_MAX 0x7 1552 #define ICL_CLK_ZERO_CNT_MAX 0xf 1553 #define ICL_TRAIL_CNT_MAX 0x7 1554 #define ICL_TCLK_PRE_CNT_MAX 0x3 1555 #define ICL_TCLK_POST_CNT_MAX 0x7 1556 #define ICL_HS_ZERO_CNT_MAX 0xf 1557 #define ICL_EXIT_ZERO_CNT_MAX 0x7 1558 1559 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1560 { 1561 struct drm_device *dev = intel_dsi->base.base.dev; 1562 struct drm_i915_private *dev_priv = to_i915(dev); 1563 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 1564 u32 tlpx_ns; 1565 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1566 u32 ths_prepare_ns, tclk_trail_ns; 1567 u32 hs_zero_cnt; 1568 u32 tclk_pre_cnt, tclk_post_cnt; 1569 1570 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1571 1572 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1573 ths_prepare_ns = max(mipi_config->ths_prepare, 1574 mipi_config->tclk_prepare); 1575 1576 /* 1577 * prepare cnt in escape clocks 1578 * this field represents a hexadecimal value with a precision 1579 * of 1.2 – i.e. the most significant bit is the integer 1580 * and the least significant 2 bits are fraction bits. 1581 * so, the field can represent a range of 0.25 to 1.75 1582 */ 1583 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1584 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1585 DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt); 1586 prepare_cnt = ICL_PREPARE_CNT_MAX; 1587 } 1588 1589 /* clk zero count in escape clocks */ 1590 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1591 ths_prepare_ns, tlpx_ns); 1592 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1593 DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1594 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1595 } 1596 1597 /* trail cnt in escape clocks*/ 1598 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1599 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1600 DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt); 1601 trail_cnt = ICL_TRAIL_CNT_MAX; 1602 } 1603 1604 /* tclk pre count in escape clocks */ 1605 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1606 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1607 DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1608 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1609 } 1610 1611 /* tclk post count in escape clocks */ 1612 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); 1613 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { 1614 DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt); 1615 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; 1616 } 1617 1618 /* hs zero cnt in escape clocks */ 1619 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1620 ths_prepare_ns, tlpx_ns); 1621 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1622 DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt); 1623 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1624 } 1625 1626 /* hs exit zero cnt in escape clocks */ 1627 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1628 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1629 DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt); 1630 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1631 } 1632 1633 /* clock lane dphy timings */ 1634 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1635 CLK_PREPARE(prepare_cnt) | 1636 CLK_ZERO_OVERRIDE | 1637 CLK_ZERO(clk_zero_cnt) | 1638 CLK_PRE_OVERRIDE | 1639 CLK_PRE(tclk_pre_cnt) | 1640 CLK_POST_OVERRIDE | 1641 CLK_POST(tclk_post_cnt) | 1642 CLK_TRAIL_OVERRIDE | 1643 CLK_TRAIL(trail_cnt)); 1644 1645 /* data lanes dphy timings */ 1646 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1647 HS_PREPARE(prepare_cnt) | 1648 HS_ZERO_OVERRIDE | 1649 HS_ZERO(hs_zero_cnt) | 1650 HS_TRAIL_OVERRIDE | 1651 HS_TRAIL(trail_cnt) | 1652 HS_EXIT_OVERRIDE | 1653 HS_EXIT(exit_zero_cnt)); 1654 1655 intel_dsi_log_params(intel_dsi); 1656 } 1657 1658 static void icl_dsi_add_properties(struct intel_connector *connector) 1659 { 1660 u32 allowed_scalers; 1661 1662 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | 1663 BIT(DRM_MODE_SCALE_FULLSCREEN) | 1664 BIT(DRM_MODE_SCALE_CENTER); 1665 1666 drm_connector_attach_scaling_mode_property(&connector->base, 1667 allowed_scalers); 1668 1669 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1670 1671 connector->base.display_info.panel_orientation = 1672 intel_dsi_get_panel_orientation(connector); 1673 drm_connector_init_panel_orientation_property(&connector->base, 1674 connector->panel.fixed_mode->hdisplay, 1675 connector->panel.fixed_mode->vdisplay); 1676 } 1677 1678 void icl_dsi_init(struct drm_i915_private *dev_priv) 1679 { 1680 struct drm_device *dev = &dev_priv->drm; 1681 struct intel_dsi *intel_dsi; 1682 struct intel_encoder *encoder; 1683 struct intel_connector *intel_connector; 1684 struct drm_connector *connector; 1685 struct drm_display_mode *fixed_mode; 1686 enum port port; 1687 1688 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1689 return; 1690 1691 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1692 if (!intel_dsi) 1693 return; 1694 1695 intel_connector = intel_connector_alloc(); 1696 if (!intel_connector) { 1697 kfree(intel_dsi); 1698 return; 1699 } 1700 1701 encoder = &intel_dsi->base; 1702 intel_dsi->attached_connector = intel_connector; 1703 connector = &intel_connector->base; 1704 1705 /* register DSI encoder with DRM subsystem */ 1706 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs, 1707 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 1708 1709 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 1710 encoder->pre_enable = gen11_dsi_pre_enable; 1711 encoder->disable = gen11_dsi_disable; 1712 encoder->post_disable = gen11_dsi_post_disable; 1713 encoder->port = port; 1714 encoder->get_config = gen11_dsi_get_config; 1715 encoder->update_pipe = intel_panel_update_backlight; 1716 encoder->compute_config = gen11_dsi_compute_config; 1717 encoder->get_hw_state = gen11_dsi_get_hw_state; 1718 encoder->type = INTEL_OUTPUT_DSI; 1719 encoder->cloneable = 0; 1720 encoder->pipe_mask = ~0; 1721 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1722 encoder->get_power_domains = gen11_dsi_get_power_domains; 1723 1724 /* register DSI connector with DRM subsystem */ 1725 drm_connector_init(dev, connector, &gen11_dsi_connector_funcs, 1726 DRM_MODE_CONNECTOR_DSI); 1727 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 1728 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1729 connector->interlace_allowed = false; 1730 connector->doublescan_allowed = false; 1731 intel_connector->get_hw_state = intel_connector_get_hw_state; 1732 1733 /* attach connector to encoder */ 1734 intel_connector_attach_encoder(intel_connector, encoder); 1735 1736 mutex_lock(&dev->mode_config.mutex); 1737 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 1738 mutex_unlock(&dev->mode_config.mutex); 1739 1740 if (!fixed_mode) { 1741 DRM_ERROR("DSI fixed mode info missing\n"); 1742 goto err; 1743 } 1744 1745 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 1746 intel_panel_setup_backlight(connector, INVALID_PIPE); 1747 1748 if (dev_priv->vbt.dsi.config->dual_link) 1749 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 1750 else 1751 intel_dsi->ports = BIT(port); 1752 1753 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; 1754 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; 1755 1756 for_each_dsi_port(port, intel_dsi->ports) { 1757 struct intel_dsi_host *host; 1758 1759 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 1760 if (!host) 1761 goto err; 1762 1763 intel_dsi->dsi_hosts[port] = host; 1764 } 1765 1766 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 1767 DRM_DEBUG_KMS("no device found\n"); 1768 goto err; 1769 } 1770 1771 icl_dphy_param_init(intel_dsi); 1772 1773 icl_dsi_add_properties(intel_connector); 1774 return; 1775 1776 err: 1777 drm_encoder_cleanup(&encoder->base); 1778 kfree(intel_dsi); 1779 kfree(intel_connector); 1780 } 1781