1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/display/drm_dsc_helper.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_mipi_dsi.h> 31 32 #include "icl_dsi.h" 33 #include "icl_dsi_regs.h" 34 #include "intel_atomic.h" 35 #include "intel_backlight.h" 36 #include "intel_combo_phy.h" 37 #include "intel_combo_phy_regs.h" 38 #include "intel_connector.h" 39 #include "intel_crtc.h" 40 #include "intel_ddi.h" 41 #include "intel_de.h" 42 #include "intel_dsi.h" 43 #include "intel_dsi_vbt.h" 44 #include "intel_panel.h" 45 #include "intel_vdsc.h" 46 #include "skl_scaler.h" 47 #include "skl_universal_plane.h" 48 49 static int header_credits_available(struct drm_i915_private *dev_priv, 50 enum transcoder dsi_trans) 51 { 52 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 53 >> FREE_HEADER_CREDIT_SHIFT; 54 } 55 56 static int payload_credits_available(struct drm_i915_private *dev_priv, 57 enum transcoder dsi_trans) 58 { 59 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 60 >> FREE_PLOAD_CREDIT_SHIFT; 61 } 62 63 static bool wait_for_header_credits(struct drm_i915_private *dev_priv, 64 enum transcoder dsi_trans, int hdr_credit) 65 { 66 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= 67 hdr_credit, 100)) { 68 drm_err(&dev_priv->drm, "DSI header credits not released\n"); 69 return false; 70 } 71 72 return true; 73 } 74 75 static bool wait_for_payload_credits(struct drm_i915_private *dev_priv, 76 enum transcoder dsi_trans, int payld_credit) 77 { 78 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= 79 payld_credit, 100)) { 80 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); 81 return false; 82 } 83 84 return true; 85 } 86 87 static enum transcoder dsi_port_to_transcoder(enum port port) 88 { 89 if (port == PORT_A) 90 return TRANSCODER_DSI_0; 91 else 92 return TRANSCODER_DSI_1; 93 } 94 95 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 96 { 97 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 98 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 99 struct mipi_dsi_device *dsi; 100 enum port port; 101 enum transcoder dsi_trans; 102 int ret; 103 104 /* wait for header/payload credits to be released */ 105 for_each_dsi_port(port, intel_dsi->ports) { 106 dsi_trans = dsi_port_to_transcoder(port); 107 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 108 wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT); 109 } 110 111 /* send nop DCS command */ 112 for_each_dsi_port(port, intel_dsi->ports) { 113 dsi = intel_dsi->dsi_hosts[port]->device; 114 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 115 dsi->channel = 0; 116 ret = mipi_dsi_dcs_nop(dsi); 117 if (ret < 0) 118 drm_err(&dev_priv->drm, 119 "error sending DCS NOP command\n"); 120 } 121 122 /* wait for header credits to be released */ 123 for_each_dsi_port(port, intel_dsi->ports) { 124 dsi_trans = dsi_port_to_transcoder(port); 125 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 126 } 127 128 /* wait for LP TX in progress bit to be cleared */ 129 for_each_dsi_port(port, intel_dsi->ports) { 130 dsi_trans = dsi_port_to_transcoder(port); 131 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 132 LPTX_IN_PROGRESS), 20)) 133 drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); 134 } 135 } 136 137 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 138 const struct mipi_dsi_packet *packet) 139 { 140 struct intel_dsi *intel_dsi = host->intel_dsi; 141 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 142 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 143 const u8 *data = packet->payload; 144 u32 len = packet->payload_length; 145 int i, j; 146 147 /* payload queue can accept *256 bytes*, check limit */ 148 if (len > MAX_PLOAD_CREDIT * 4) { 149 drm_err(&i915->drm, "payload size exceeds max queue limit\n"); 150 return -EINVAL; 151 } 152 153 for (i = 0; i < len; i += 4) { 154 u32 tmp = 0; 155 156 if (!wait_for_payload_credits(i915, dsi_trans, 1)) 157 return -EBUSY; 158 159 for (j = 0; j < min_t(u32, len - i, 4); j++) 160 tmp |= *data++ << 8 * j; 161 162 intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp); 163 } 164 165 return 0; 166 } 167 168 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 169 const struct mipi_dsi_packet *packet, 170 bool enable_lpdt) 171 { 172 struct intel_dsi *intel_dsi = host->intel_dsi; 173 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 174 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 175 u32 tmp; 176 177 if (!wait_for_header_credits(dev_priv, dsi_trans, 1)) 178 return -EBUSY; 179 180 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); 181 182 if (packet->payload) 183 tmp |= PAYLOAD_PRESENT; 184 else 185 tmp &= ~PAYLOAD_PRESENT; 186 187 tmp &= ~VBLANK_FENCE; 188 189 if (enable_lpdt) 190 tmp |= LP_DATA_TRANSFER; 191 else 192 tmp &= ~LP_DATA_TRANSFER; 193 194 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 195 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); 196 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); 197 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); 198 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); 199 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); 200 201 return 0; 202 } 203 204 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 205 { 206 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 207 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 208 u32 tmp, mode_flags; 209 enum port port; 210 211 mode_flags = crtc_state->mode_flags; 212 213 /* 214 * case 1 also covers dual link 215 * In case of dual link, frame update should be set on 216 * DSI_0 217 */ 218 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 219 port = PORT_A; 220 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 221 port = PORT_B; 222 else 223 return; 224 225 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 226 tmp |= DSI_FRAME_UPDATE_REQUEST; 227 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 228 } 229 230 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 231 { 232 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 233 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 234 enum phy phy; 235 u32 tmp; 236 int lane; 237 238 for_each_dsi_phy(phy, intel_dsi->phys) { 239 /* 240 * Program voltage swing and pre-emphasis level values as per 241 * table in BSPEC under DDI buffer programing 242 */ 243 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 244 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 245 tmp |= SCALING_MODE_SEL(0x2); 246 tmp |= TAP2_DISABLE | TAP3_DISABLE; 247 tmp |= RTERM_SELECT(0x6); 248 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 249 250 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 251 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 252 tmp |= SCALING_MODE_SEL(0x2); 253 tmp |= TAP2_DISABLE | TAP3_DISABLE; 254 tmp |= RTERM_SELECT(0x6); 255 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 256 257 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 258 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 259 RCOMP_SCALAR_MASK); 260 tmp |= SWING_SEL_UPPER(0x2); 261 tmp |= SWING_SEL_LOWER(0x2); 262 tmp |= RCOMP_SCALAR(0x98); 263 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 264 265 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 266 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 267 RCOMP_SCALAR_MASK); 268 tmp |= SWING_SEL_UPPER(0x2); 269 tmp |= SWING_SEL_LOWER(0x2); 270 tmp |= RCOMP_SCALAR(0x98); 271 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 272 273 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 274 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 275 CURSOR_COEFF_MASK); 276 tmp |= POST_CURSOR_1(0x0); 277 tmp |= POST_CURSOR_2(0x0); 278 tmp |= CURSOR_COEFF(0x3f); 279 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 280 281 for (lane = 0; lane <= 3; lane++) { 282 /* Bspec: must not use GRP register for write */ 283 tmp = intel_de_read(dev_priv, 284 ICL_PORT_TX_DW4_LN(lane, phy)); 285 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 286 CURSOR_COEFF_MASK); 287 tmp |= POST_CURSOR_1(0x0); 288 tmp |= POST_CURSOR_2(0x0); 289 tmp |= CURSOR_COEFF(0x3f); 290 intel_de_write(dev_priv, 291 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 292 } 293 } 294 } 295 296 static void configure_dual_link_mode(struct intel_encoder *encoder, 297 const struct intel_crtc_state *pipe_config) 298 { 299 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 300 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 301 u32 dss_ctl1; 302 303 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); 304 dss_ctl1 |= SPLITTER_ENABLE; 305 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 306 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 307 308 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 309 const struct drm_display_mode *adjusted_mode = 310 &pipe_config->hw.adjusted_mode; 311 u32 dss_ctl2; 312 u16 hactive = adjusted_mode->crtc_hdisplay; 313 u16 dl_buffer_depth; 314 315 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 316 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 317 318 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 319 drm_err(&dev_priv->drm, 320 "DL buffer depth exceed max value\n"); 321 322 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 323 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 324 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); 325 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; 326 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 327 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); 328 } else { 329 /* Interleave */ 330 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 331 } 332 333 intel_de_write(dev_priv, DSS_CTL1, dss_ctl1); 334 } 335 336 /* aka DSI 8X clock */ 337 static int afe_clk(struct intel_encoder *encoder, 338 const struct intel_crtc_state *crtc_state) 339 { 340 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 341 int bpp; 342 343 if (crtc_state->dsc.compression_enable) 344 bpp = crtc_state->dsc.compressed_bpp; 345 else 346 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 347 348 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 349 } 350 351 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 352 const struct intel_crtc_state *crtc_state) 353 { 354 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 355 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 356 enum port port; 357 int afe_clk_khz; 358 int theo_word_clk, act_word_clk; 359 u32 esc_clk_div_m, esc_clk_div_m_phy; 360 361 afe_clk_khz = afe_clk(encoder, crtc_state); 362 363 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 364 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 365 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 366 esc_clk_div_m = act_word_clk * 8; 367 esc_clk_div_m_phy = (act_word_clk - 1) / 2; 368 } else { 369 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 370 } 371 372 for_each_dsi_port(port, intel_dsi->ports) { 373 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), 374 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 375 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); 376 } 377 378 for_each_dsi_port(port, intel_dsi->ports) { 379 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port), 380 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 381 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); 382 } 383 384 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 385 for_each_dsi_port(port, intel_dsi->ports) { 386 intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8), 387 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); 388 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8)); 389 } 390 } 391 } 392 393 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, 394 struct intel_dsi *intel_dsi) 395 { 396 enum port port; 397 398 for_each_dsi_port(port, intel_dsi->ports) { 399 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); 400 intel_dsi->io_wakeref[port] = 401 intel_display_power_get(dev_priv, 402 port == PORT_A ? 403 POWER_DOMAIN_PORT_DDI_IO_A : 404 POWER_DOMAIN_PORT_DDI_IO_B); 405 } 406 } 407 408 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 409 { 410 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 411 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 412 enum port port; 413 u32 tmp; 414 415 for_each_dsi_port(port, intel_dsi->ports) { 416 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 417 tmp |= COMBO_PHY_MODE_DSI; 418 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 419 } 420 421 get_dsi_io_power_domains(dev_priv, intel_dsi); 422 } 423 424 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 425 { 426 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 427 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 428 enum phy phy; 429 430 for_each_dsi_phy(phy, intel_dsi->phys) 431 intel_combo_phy_power_up_lanes(dev_priv, phy, true, 432 intel_dsi->lane_count, false); 433 } 434 435 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 436 { 437 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 438 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 439 enum phy phy; 440 u32 tmp; 441 int lane; 442 443 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 444 for_each_dsi_phy(phy, intel_dsi->phys) { 445 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 446 tmp &= ~LOADGEN_SELECT; 447 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 448 for (lane = 0; lane <= 3; lane++) { 449 tmp = intel_de_read(dev_priv, 450 ICL_PORT_TX_DW4_LN(lane, phy)); 451 tmp &= ~LOADGEN_SELECT; 452 if (lane != 2) 453 tmp |= LOADGEN_SELECT; 454 intel_de_write(dev_priv, 455 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 456 } 457 } 458 459 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 460 for_each_dsi_phy(phy, intel_dsi->phys) { 461 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 462 tmp &= ~FRC_LATENCY_OPTIM_MASK; 463 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 464 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 465 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 466 tmp &= ~FRC_LATENCY_OPTIM_MASK; 467 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 468 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 469 470 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 471 if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) { 472 tmp = intel_de_read(dev_priv, 473 ICL_PORT_PCS_DW1_AUX(phy)); 474 tmp &= ~LATENCY_OPTIM_MASK; 475 tmp |= LATENCY_OPTIM_VAL(0); 476 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), 477 tmp); 478 479 tmp = intel_de_read(dev_priv, 480 ICL_PORT_PCS_DW1_LN(0, phy)); 481 tmp &= ~LATENCY_OPTIM_MASK; 482 tmp |= LATENCY_OPTIM_VAL(0x1); 483 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), 484 tmp); 485 } 486 } 487 488 } 489 490 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 491 { 492 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 493 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 494 u32 tmp; 495 enum phy phy; 496 497 /* clear common keeper enable bit */ 498 for_each_dsi_phy(phy, intel_dsi->phys) { 499 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 500 tmp &= ~COMMON_KEEPER_EN; 501 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp); 502 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy)); 503 tmp &= ~COMMON_KEEPER_EN; 504 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp); 505 } 506 507 /* 508 * Set SUS Clock Config bitfield to 11b 509 * Note: loadgen select program is done 510 * as part of lane phy sequence configuration 511 */ 512 for_each_dsi_phy(phy, intel_dsi->phys) { 513 tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 514 tmp |= SUS_CLOCK_CONFIG; 515 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp); 516 } 517 518 /* Clear training enable to change swing values */ 519 for_each_dsi_phy(phy, intel_dsi->phys) { 520 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 521 tmp &= ~TX_TRAINING_EN; 522 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 523 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 524 tmp &= ~TX_TRAINING_EN; 525 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 526 } 527 528 /* Program swing and de-emphasis */ 529 dsi_program_swing_and_deemphasis(encoder); 530 531 /* Set training enable to trigger update */ 532 for_each_dsi_phy(phy, intel_dsi->phys) { 533 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 534 tmp |= TX_TRAINING_EN; 535 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 536 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 537 tmp |= TX_TRAINING_EN; 538 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 539 } 540 } 541 542 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 543 { 544 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 545 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 546 u32 tmp; 547 enum port port; 548 549 for_each_dsi_port(port, intel_dsi->ports) { 550 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 551 tmp |= DDI_BUF_CTL_ENABLE; 552 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 553 554 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 555 DDI_BUF_IS_IDLE), 556 500)) 557 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", 558 port_name(port)); 559 } 560 } 561 562 static void 563 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 564 const struct intel_crtc_state *crtc_state) 565 { 566 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 567 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 568 u32 tmp; 569 enum port port; 570 enum phy phy; 571 572 /* Program T-INIT master registers */ 573 for_each_dsi_port(port, intel_dsi->ports) { 574 tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port)); 575 tmp &= ~DSI_T_INIT_MASTER_MASK; 576 tmp |= intel_dsi->init_count; 577 intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp); 578 } 579 580 /* Program DPHY clock lanes timings */ 581 for_each_dsi_port(port, intel_dsi->ports) { 582 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port), 583 intel_dsi->dphy_reg); 584 585 /* shadow register inside display core */ 586 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port), 587 intel_dsi->dphy_reg); 588 } 589 590 /* Program DPHY data lanes timings */ 591 for_each_dsi_port(port, intel_dsi->ports) { 592 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port), 593 intel_dsi->dphy_data_lane_reg); 594 595 /* shadow register inside display core */ 596 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port), 597 intel_dsi->dphy_data_lane_reg); 598 } 599 600 /* 601 * If DSI link operating at or below an 800 MHz, 602 * TA_SURE should be override and programmed to 603 * a value '0' inside TA_PARAM_REGISTERS otherwise 604 * leave all fields at HW default values. 605 */ 606 if (DISPLAY_VER(dev_priv) == 11) { 607 if (afe_clk(encoder, crtc_state) <= 800000) { 608 for_each_dsi_port(port, intel_dsi->ports) { 609 tmp = intel_de_read(dev_priv, 610 DPHY_TA_TIMING_PARAM(port)); 611 tmp &= ~TA_SURE_MASK; 612 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 613 intel_de_write(dev_priv, 614 DPHY_TA_TIMING_PARAM(port), 615 tmp); 616 617 /* shadow register inside display core */ 618 tmp = intel_de_read(dev_priv, 619 DSI_TA_TIMING_PARAM(port)); 620 tmp &= ~TA_SURE_MASK; 621 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 622 intel_de_write(dev_priv, 623 DSI_TA_TIMING_PARAM(port), tmp); 624 } 625 } 626 } 627 628 if (IS_JSL_EHL(dev_priv)) { 629 for_each_dsi_phy(phy, intel_dsi->phys) { 630 tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy)); 631 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; 632 intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp); 633 } 634 } 635 } 636 637 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 638 { 639 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 640 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 641 u32 tmp; 642 enum phy phy; 643 644 mutex_lock(&dev_priv->dpll.lock); 645 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 646 for_each_dsi_phy(phy, intel_dsi->phys) 647 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 648 649 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 650 mutex_unlock(&dev_priv->dpll.lock); 651 } 652 653 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 654 { 655 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 656 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 657 u32 tmp; 658 enum phy phy; 659 660 mutex_lock(&dev_priv->dpll.lock); 661 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 662 for_each_dsi_phy(phy, intel_dsi->phys) 663 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 664 665 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 666 mutex_unlock(&dev_priv->dpll.lock); 667 } 668 669 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 670 { 671 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 672 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 673 bool clock_enabled = false; 674 enum phy phy; 675 u32 tmp; 676 677 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 678 679 for_each_dsi_phy(phy, intel_dsi->phys) { 680 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 681 clock_enabled = true; 682 } 683 684 return clock_enabled; 685 } 686 687 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 688 const struct intel_crtc_state *crtc_state) 689 { 690 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 691 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 692 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 693 enum phy phy; 694 u32 val; 695 696 mutex_lock(&dev_priv->dpll.lock); 697 698 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 699 for_each_dsi_phy(phy, intel_dsi->phys) { 700 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 701 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 702 } 703 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 704 705 for_each_dsi_phy(phy, intel_dsi->phys) { 706 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 707 } 708 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 709 710 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 711 712 mutex_unlock(&dev_priv->dpll.lock); 713 } 714 715 static void 716 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 717 const struct intel_crtc_state *pipe_config) 718 { 719 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 720 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 721 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 722 enum pipe pipe = crtc->pipe; 723 u32 tmp; 724 enum port port; 725 enum transcoder dsi_trans; 726 727 for_each_dsi_port(port, intel_dsi->ports) { 728 dsi_trans = dsi_port_to_transcoder(port); 729 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 730 731 if (intel_dsi->eotp_pkt) 732 tmp &= ~EOTP_DISABLED; 733 else 734 tmp |= EOTP_DISABLED; 735 736 /* enable link calibration if freq > 1.5Gbps */ 737 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 738 tmp &= ~LINK_CALIBRATION_MASK; 739 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 740 } 741 742 /* configure continuous clock */ 743 tmp &= ~CONTINUOUS_CLK_MASK; 744 if (intel_dsi->clock_stop) 745 tmp |= CLK_ENTER_LP_AFTER_DATA; 746 else 747 tmp |= CLK_HS_CONTINUOUS; 748 749 /* configure buffer threshold limit to minimum */ 750 tmp &= ~PIX_BUF_THRESHOLD_MASK; 751 tmp |= PIX_BUF_THRESHOLD_1_4; 752 753 /* set virtual channel to '0' */ 754 tmp &= ~PIX_VIRT_CHAN_MASK; 755 tmp |= PIX_VIRT_CHAN(0); 756 757 /* program BGR transmission */ 758 if (intel_dsi->bgr_enabled) 759 tmp |= BGR_TRANSMISSION; 760 761 /* select pixel format */ 762 tmp &= ~PIX_FMT_MASK; 763 if (pipe_config->dsc.compression_enable) { 764 tmp |= PIX_FMT_COMPRESSED; 765 } else { 766 switch (intel_dsi->pixel_format) { 767 default: 768 MISSING_CASE(intel_dsi->pixel_format); 769 fallthrough; 770 case MIPI_DSI_FMT_RGB565: 771 tmp |= PIX_FMT_RGB565; 772 break; 773 case MIPI_DSI_FMT_RGB666_PACKED: 774 tmp |= PIX_FMT_RGB666_PACKED; 775 break; 776 case MIPI_DSI_FMT_RGB666: 777 tmp |= PIX_FMT_RGB666_LOOSE; 778 break; 779 case MIPI_DSI_FMT_RGB888: 780 tmp |= PIX_FMT_RGB888; 781 break; 782 } 783 } 784 785 if (DISPLAY_VER(dev_priv) >= 12) { 786 if (is_vid_mode(intel_dsi)) 787 tmp |= BLANKING_PACKET_ENABLE; 788 } 789 790 /* program DSI operation mode */ 791 if (is_vid_mode(intel_dsi)) { 792 tmp &= ~OP_MODE_MASK; 793 switch (intel_dsi->video_mode) { 794 default: 795 MISSING_CASE(intel_dsi->video_mode); 796 fallthrough; 797 case NON_BURST_SYNC_EVENTS: 798 tmp |= VIDEO_MODE_SYNC_EVENT; 799 break; 800 case NON_BURST_SYNC_PULSE: 801 tmp |= VIDEO_MODE_SYNC_PULSE; 802 break; 803 } 804 } else { 805 /* 806 * FIXME: Retrieve this info from VBT. 807 * As per the spec when dsi transcoder is operating 808 * in TE GATE mode, TE comes from GPIO 809 * which is UTIL PIN for DSI 0. 810 * Also this GPIO would not be used for other 811 * purposes is an assumption. 812 */ 813 tmp &= ~OP_MODE_MASK; 814 tmp |= CMD_MODE_TE_GATE; 815 tmp |= TE_SOURCE_GPIO; 816 } 817 818 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 819 } 820 821 /* enable port sync mode if dual link */ 822 if (intel_dsi->dual_link) { 823 for_each_dsi_port(port, intel_dsi->ports) { 824 dsi_trans = dsi_port_to_transcoder(port); 825 tmp = intel_de_read(dev_priv, 826 TRANS_DDI_FUNC_CTL2(dsi_trans)); 827 tmp |= PORT_SYNC_MODE_ENABLE; 828 intel_de_write(dev_priv, 829 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 830 } 831 832 /* configure stream splitting */ 833 configure_dual_link_mode(encoder, pipe_config); 834 } 835 836 for_each_dsi_port(port, intel_dsi->ports) { 837 dsi_trans = dsi_port_to_transcoder(port); 838 839 /* select data lane width */ 840 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 841 tmp &= ~DDI_PORT_WIDTH_MASK; 842 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); 843 844 /* select input pipe */ 845 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 846 switch (pipe) { 847 default: 848 MISSING_CASE(pipe); 849 fallthrough; 850 case PIPE_A: 851 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 852 break; 853 case PIPE_B: 854 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 855 break; 856 case PIPE_C: 857 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 858 break; 859 case PIPE_D: 860 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 861 break; 862 } 863 864 /* enable DDI buffer */ 865 tmp |= TRANS_DDI_FUNC_ENABLE; 866 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 867 } 868 869 /* wait for link ready */ 870 for_each_dsi_port(port, intel_dsi->ports) { 871 dsi_trans = dsi_port_to_transcoder(port); 872 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) & 873 LINK_READY), 2500)) 874 drm_err(&dev_priv->drm, "DSI link not ready\n"); 875 } 876 } 877 878 static void 879 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 880 const struct intel_crtc_state *crtc_state) 881 { 882 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 883 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 884 const struct drm_display_mode *adjusted_mode = 885 &crtc_state->hw.adjusted_mode; 886 enum port port; 887 enum transcoder dsi_trans; 888 /* horizontal timings */ 889 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 890 u16 hback_porch; 891 /* vertical timings */ 892 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 893 int mul = 1, div = 1; 894 895 /* 896 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 897 * for slower link speed if DSC is enabled. 898 * 899 * The compression frequency ratio is the ratio between compressed and 900 * non-compressed link speeds, and simplifies down to the ratio between 901 * compressed and non-compressed bpp. 902 */ 903 if (crtc_state->dsc.compression_enable) { 904 mul = crtc_state->dsc.compressed_bpp; 905 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 906 } 907 908 hactive = adjusted_mode->crtc_hdisplay; 909 910 if (is_vid_mode(intel_dsi)) 911 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 912 else 913 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 914 915 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 916 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 917 hsync_size = hsync_end - hsync_start; 918 hback_porch = (adjusted_mode->crtc_htotal - 919 adjusted_mode->crtc_hsync_end); 920 vactive = adjusted_mode->crtc_vdisplay; 921 922 if (is_vid_mode(intel_dsi)) { 923 vtotal = adjusted_mode->crtc_vtotal; 924 } else { 925 int bpp, line_time_us, byte_clk_period_ns; 926 927 if (crtc_state->dsc.compression_enable) 928 bpp = crtc_state->dsc.compressed_bpp; 929 else 930 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 931 932 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 933 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 934 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 935 } 936 vsync_start = adjusted_mode->crtc_vsync_start; 937 vsync_end = adjusted_mode->crtc_vsync_end; 938 vsync_shift = hsync_start - htotal / 2; 939 940 if (intel_dsi->dual_link) { 941 hactive /= 2; 942 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 943 hactive += intel_dsi->pixel_overlap; 944 htotal /= 2; 945 } 946 947 /* minimum hactive as per bspec: 256 pixels */ 948 if (adjusted_mode->crtc_hdisplay < 256) 949 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); 950 951 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 952 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 953 drm_err(&dev_priv->drm, 954 "hactive pixels are not multiple of 4\n"); 955 956 /* program TRANS_HTOTAL register */ 957 for_each_dsi_port(port, intel_dsi->ports) { 958 dsi_trans = dsi_port_to_transcoder(port); 959 intel_de_write(dev_priv, HTOTAL(dsi_trans), 960 (hactive - 1) | ((htotal - 1) << 16)); 961 } 962 963 /* TRANS_HSYNC register to be programmed only for video mode */ 964 if (is_vid_mode(intel_dsi)) { 965 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { 966 /* BSPEC: hsync size should be atleast 16 pixels */ 967 if (hsync_size < 16) 968 drm_err(&dev_priv->drm, 969 "hsync size < 16 pixels\n"); 970 } 971 972 if (hback_porch < 16) 973 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); 974 975 if (intel_dsi->dual_link) { 976 hsync_start /= 2; 977 hsync_end /= 2; 978 } 979 980 for_each_dsi_port(port, intel_dsi->ports) { 981 dsi_trans = dsi_port_to_transcoder(port); 982 intel_de_write(dev_priv, HSYNC(dsi_trans), 983 (hsync_start - 1) | ((hsync_end - 1) << 16)); 984 } 985 } 986 987 /* program TRANS_VTOTAL register */ 988 for_each_dsi_port(port, intel_dsi->ports) { 989 dsi_trans = dsi_port_to_transcoder(port); 990 /* 991 * FIXME: Programing this by assuming progressive mode, since 992 * non-interlaced info from VBT is not saved inside 993 * struct drm_display_mode. 994 * For interlace mode: program required pixel minus 2 995 */ 996 intel_de_write(dev_priv, VTOTAL(dsi_trans), 997 (vactive - 1) | ((vtotal - 1) << 16)); 998 } 999 1000 if (vsync_end < vsync_start || vsync_end > vtotal) 1001 drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); 1002 1003 if (vsync_start < vactive) 1004 drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); 1005 1006 /* program TRANS_VSYNC register for video mode only */ 1007 if (is_vid_mode(intel_dsi)) { 1008 for_each_dsi_port(port, intel_dsi->ports) { 1009 dsi_trans = dsi_port_to_transcoder(port); 1010 intel_de_write(dev_priv, VSYNC(dsi_trans), 1011 (vsync_start - 1) | ((vsync_end - 1) << 16)); 1012 } 1013 } 1014 1015 /* 1016 * FIXME: It has to be programmed only for video modes and interlaced 1017 * modes. Put the check condition here once interlaced 1018 * info available as described above. 1019 * program TRANS_VSYNCSHIFT register 1020 */ 1021 if (is_vid_mode(intel_dsi)) { 1022 for_each_dsi_port(port, intel_dsi->ports) { 1023 dsi_trans = dsi_port_to_transcoder(port); 1024 intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans), 1025 vsync_shift); 1026 } 1027 } 1028 1029 /* program TRANS_VBLANK register, should be same as vtotal programmed */ 1030 if (DISPLAY_VER(dev_priv) >= 12) { 1031 for_each_dsi_port(port, intel_dsi->ports) { 1032 dsi_trans = dsi_port_to_transcoder(port); 1033 intel_de_write(dev_priv, VBLANK(dsi_trans), 1034 (vactive - 1) | ((vtotal - 1) << 16)); 1035 } 1036 } 1037 } 1038 1039 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1040 { 1041 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1042 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1043 enum port port; 1044 enum transcoder dsi_trans; 1045 u32 tmp; 1046 1047 for_each_dsi_port(port, intel_dsi->ports) { 1048 dsi_trans = dsi_port_to_transcoder(port); 1049 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1050 tmp |= PIPECONF_ENABLE; 1051 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1052 1053 /* wait for transcoder to be enabled */ 1054 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), 1055 PIPECONF_STATE_ENABLE, 10)) 1056 drm_err(&dev_priv->drm, 1057 "DSI transcoder not enabled\n"); 1058 } 1059 } 1060 1061 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1062 const struct intel_crtc_state *crtc_state) 1063 { 1064 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1065 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1066 enum port port; 1067 enum transcoder dsi_trans; 1068 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1069 1070 /* 1071 * escape clock count calculation: 1072 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1073 * UI (nsec) = (10^6)/Bitrate 1074 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1075 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1076 */ 1077 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1078 mul = 8 * 1000000; 1079 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1080 divisor); 1081 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1082 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1083 1084 for_each_dsi_port(port, intel_dsi->ports) { 1085 dsi_trans = dsi_port_to_transcoder(port); 1086 1087 /* program hst_tx_timeout */ 1088 tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans)); 1089 tmp &= ~HSTX_TIMEOUT_VALUE_MASK; 1090 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout); 1091 intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp); 1092 1093 /* FIXME: DSI_CALIB_TO */ 1094 1095 /* program lp_rx_host timeout */ 1096 tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans)); 1097 tmp &= ~LPRX_TIMEOUT_VALUE_MASK; 1098 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout); 1099 intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp); 1100 1101 /* FIXME: DSI_PWAIT_TO */ 1102 1103 /* program turn around timeout */ 1104 tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans)); 1105 tmp &= ~TA_TIMEOUT_VALUE_MASK; 1106 tmp |= TA_TIMEOUT_VALUE(ta_timeout); 1107 intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp); 1108 } 1109 } 1110 1111 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1112 bool enable) 1113 { 1114 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1115 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1116 u32 tmp; 1117 1118 /* 1119 * used as TE i/p for DSI0, 1120 * for dual link/DSI1 TE is from slave DSI1 1121 * through GPIO. 1122 */ 1123 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1124 return; 1125 1126 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL); 1127 1128 if (enable) { 1129 tmp |= UTIL_PIN_DIRECTION_INPUT; 1130 tmp |= UTIL_PIN_ENABLE; 1131 } else { 1132 tmp &= ~UTIL_PIN_ENABLE; 1133 } 1134 intel_de_write(dev_priv, UTIL_PIN_CTL, tmp); 1135 } 1136 1137 static void 1138 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1139 const struct intel_crtc_state *crtc_state) 1140 { 1141 /* step 4a: power up all lanes of the DDI used by DSI */ 1142 gen11_dsi_power_up_lanes(encoder); 1143 1144 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1145 gen11_dsi_config_phy_lanes_sequence(encoder); 1146 1147 /* step 4c: configure voltage swing and skew */ 1148 gen11_dsi_voltage_swing_program_seq(encoder); 1149 1150 /* enable DDI buffer */ 1151 gen11_dsi_enable_ddi_buffer(encoder); 1152 1153 /* setup D-PHY timings */ 1154 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1155 1156 /* Since transcoder is configured to take events from GPIO */ 1157 gen11_dsi_config_util_pin(encoder, true); 1158 1159 /* step 4h: setup DSI protocol timeouts */ 1160 gen11_dsi_setup_timeouts(encoder, crtc_state); 1161 1162 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1163 gen11_dsi_configure_transcoder(encoder, crtc_state); 1164 1165 /* Step 4l: Gate DDI clocks */ 1166 gen11_dsi_gate_clocks(encoder); 1167 } 1168 1169 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1170 { 1171 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1172 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1173 struct mipi_dsi_device *dsi; 1174 enum port port; 1175 enum transcoder dsi_trans; 1176 u32 tmp; 1177 int ret; 1178 1179 /* set maximum return packet size */ 1180 for_each_dsi_port(port, intel_dsi->ports) { 1181 dsi_trans = dsi_port_to_transcoder(port); 1182 1183 /* 1184 * FIXME: This uses the number of DW's currently in the payload 1185 * receive queue. This is probably not what we want here. 1186 */ 1187 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans)); 1188 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1189 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1190 tmp = tmp * 4; 1191 dsi = intel_dsi->dsi_hosts[port]->device; 1192 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1193 if (ret < 0) 1194 drm_err(&dev_priv->drm, 1195 "error setting max return pkt size%d\n", tmp); 1196 } 1197 1198 /* panel power on related mipi dsi vbt sequences */ 1199 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1200 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 1201 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1202 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1203 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1204 1205 /* ensure all panel commands dispatched before enabling transcoder */ 1206 wait_for_cmds_dispatched_to_panel(encoder); 1207 } 1208 1209 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1210 struct intel_encoder *encoder, 1211 const struct intel_crtc_state *crtc_state, 1212 const struct drm_connector_state *conn_state) 1213 { 1214 /* step2: enable IO power */ 1215 gen11_dsi_enable_io_power(encoder); 1216 1217 /* step3: enable DSI PLL */ 1218 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1219 } 1220 1221 static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1222 struct intel_encoder *encoder, 1223 const struct intel_crtc_state *pipe_config, 1224 const struct drm_connector_state *conn_state) 1225 { 1226 /* step3b */ 1227 gen11_dsi_map_pll(encoder, pipe_config); 1228 1229 /* step4: enable DSI port and DPHY */ 1230 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1231 1232 /* step5: program and powerup panel */ 1233 gen11_dsi_powerup_panel(encoder); 1234 1235 intel_dsc_dsi_pps_write(encoder, pipe_config); 1236 1237 /* step6c: configure transcoder timings */ 1238 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1239 } 1240 1241 /* 1242 * Wa_1409054076:icl,jsl,ehl 1243 * When pipe A is disabled and MIPI DSI is enabled on pipe B, 1244 * the AMT KVMR feature will incorrectly see pipe A as enabled. 1245 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave 1246 * it set while DSI is enabled on pipe B 1247 */ 1248 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, 1249 enum pipe pipe, bool enable) 1250 { 1251 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1252 1253 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) 1254 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1255 IGNORE_KVMR_PIPE_A, 1256 enable ? IGNORE_KVMR_PIPE_A : 0); 1257 } 1258 1259 /* 1260 * Wa_16012360555:adl-p 1261 * SW will have to program the "LP to HS Wakeup Guardband" 1262 * to account for the repeaters on the HS Request/Ready 1263 * PPI signaling between the Display engine and the DPHY. 1264 */ 1265 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) 1266 { 1267 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1268 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1269 enum port port; 1270 1271 if (DISPLAY_VER(i915) == 13) { 1272 for_each_dsi_port(port, intel_dsi->ports) 1273 intel_de_rmw(i915, TGL_DSI_CHKN_REG(port), 1274 TGL_DSI_CHKN_LSHS_GB_MASK, 1275 TGL_DSI_CHKN_LSHS_GB(4)); 1276 } 1277 } 1278 1279 static void gen11_dsi_enable(struct intel_atomic_state *state, 1280 struct intel_encoder *encoder, 1281 const struct intel_crtc_state *crtc_state, 1282 const struct drm_connector_state *conn_state) 1283 { 1284 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1285 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 1286 1287 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 1288 1289 /* Wa_1409054076:icl,jsl,ehl */ 1290 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); 1291 1292 /* Wa_16012360555:adl-p */ 1293 adlp_set_lp_hs_wakeup_gb(encoder); 1294 1295 /* step6d: enable dsi transcoder */ 1296 gen11_dsi_enable_transcoder(encoder); 1297 1298 /* step7: enable backlight */ 1299 intel_backlight_enable(crtc_state, conn_state); 1300 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1301 1302 intel_crtc_vblank_on(crtc_state); 1303 } 1304 1305 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1306 { 1307 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1308 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1309 enum port port; 1310 enum transcoder dsi_trans; 1311 u32 tmp; 1312 1313 for_each_dsi_port(port, intel_dsi->ports) { 1314 dsi_trans = dsi_port_to_transcoder(port); 1315 1316 /* disable transcoder */ 1317 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1318 tmp &= ~PIPECONF_ENABLE; 1319 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1320 1321 /* wait for transcoder to be disabled */ 1322 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), 1323 PIPECONF_STATE_ENABLE, 50)) 1324 drm_err(&dev_priv->drm, 1325 "DSI trancoder not disabled\n"); 1326 } 1327 } 1328 1329 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1330 { 1331 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1332 1333 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1334 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1335 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1336 1337 /* ensure cmds dispatched to panel */ 1338 wait_for_cmds_dispatched_to_panel(encoder); 1339 } 1340 1341 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1342 { 1343 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1344 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1345 enum port port; 1346 enum transcoder dsi_trans; 1347 u32 tmp; 1348 1349 /* disable periodic update mode */ 1350 if (is_cmd_mode(intel_dsi)) { 1351 for_each_dsi_port(port, intel_dsi->ports) { 1352 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 1353 tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE; 1354 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 1355 } 1356 } 1357 1358 /* put dsi link in ULPS */ 1359 for_each_dsi_port(port, intel_dsi->ports) { 1360 dsi_trans = dsi_port_to_transcoder(port); 1361 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)); 1362 tmp |= LINK_ENTER_ULPS; 1363 tmp &= ~LINK_ULPS_TYPE_LP11; 1364 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp); 1365 1366 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 1367 LINK_IN_ULPS), 1368 10)) 1369 drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); 1370 } 1371 1372 /* disable ddi function */ 1373 for_each_dsi_port(port, intel_dsi->ports) { 1374 dsi_trans = dsi_port_to_transcoder(port); 1375 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1376 tmp &= ~TRANS_DDI_FUNC_ENABLE; 1377 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 1378 } 1379 1380 /* disable port sync mode if dual link */ 1381 if (intel_dsi->dual_link) { 1382 for_each_dsi_port(port, intel_dsi->ports) { 1383 dsi_trans = dsi_port_to_transcoder(port); 1384 tmp = intel_de_read(dev_priv, 1385 TRANS_DDI_FUNC_CTL2(dsi_trans)); 1386 tmp &= ~PORT_SYNC_MODE_ENABLE; 1387 intel_de_write(dev_priv, 1388 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 1389 } 1390 } 1391 } 1392 1393 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1394 { 1395 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1396 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1397 u32 tmp; 1398 enum port port; 1399 1400 gen11_dsi_ungate_clocks(encoder); 1401 for_each_dsi_port(port, intel_dsi->ports) { 1402 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1403 tmp &= ~DDI_BUF_CTL_ENABLE; 1404 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 1405 1406 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1407 DDI_BUF_IS_IDLE), 1408 8)) 1409 drm_err(&dev_priv->drm, 1410 "DDI port:%c buffer not idle\n", 1411 port_name(port)); 1412 } 1413 gen11_dsi_gate_clocks(encoder); 1414 } 1415 1416 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1417 { 1418 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1419 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1420 enum port port; 1421 u32 tmp; 1422 1423 for_each_dsi_port(port, intel_dsi->ports) { 1424 intel_wakeref_t wakeref; 1425 1426 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1427 intel_display_power_put(dev_priv, 1428 port == PORT_A ? 1429 POWER_DOMAIN_PORT_DDI_IO_A : 1430 POWER_DOMAIN_PORT_DDI_IO_B, 1431 wakeref); 1432 } 1433 1434 /* set mode to DDI */ 1435 for_each_dsi_port(port, intel_dsi->ports) { 1436 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 1437 tmp &= ~COMBO_PHY_MODE_DSI; 1438 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 1439 } 1440 } 1441 1442 static void gen11_dsi_disable(struct intel_atomic_state *state, 1443 struct intel_encoder *encoder, 1444 const struct intel_crtc_state *old_crtc_state, 1445 const struct drm_connector_state *old_conn_state) 1446 { 1447 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1448 struct intel_crtc *crtc = to_intel_crtc(old_conn_state->crtc); 1449 1450 /* step1: turn off backlight */ 1451 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1452 intel_backlight_disable(old_conn_state); 1453 1454 /* step2d,e: disable transcoder and wait */ 1455 gen11_dsi_disable_transcoder(encoder); 1456 1457 /* Wa_1409054076:icl,jsl,ehl */ 1458 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); 1459 1460 /* step2f,g: powerdown panel */ 1461 gen11_dsi_powerdown_panel(encoder); 1462 1463 /* step2h,i,j: deconfig trancoder */ 1464 gen11_dsi_deconfigure_trancoder(encoder); 1465 1466 /* step3: disable port */ 1467 gen11_dsi_disable_port(encoder); 1468 1469 gen11_dsi_config_util_pin(encoder, false); 1470 1471 /* step4: disable IO power */ 1472 gen11_dsi_disable_io_power(encoder); 1473 } 1474 1475 static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1476 struct intel_encoder *encoder, 1477 const struct intel_crtc_state *old_crtc_state, 1478 const struct drm_connector_state *old_conn_state) 1479 { 1480 intel_crtc_vblank_off(old_crtc_state); 1481 1482 intel_dsc_disable(old_crtc_state); 1483 1484 skl_scaler_disable(old_crtc_state); 1485 } 1486 1487 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1488 struct drm_display_mode *mode) 1489 { 1490 /* FIXME: DSC? */ 1491 return intel_dsi_mode_valid(connector, mode); 1492 } 1493 1494 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1495 struct intel_crtc_state *pipe_config) 1496 { 1497 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1498 struct drm_display_mode *adjusted_mode = 1499 &pipe_config->hw.adjusted_mode; 1500 1501 if (pipe_config->dsc.compressed_bpp) { 1502 int div = pipe_config->dsc.compressed_bpp; 1503 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1504 1505 adjusted_mode->crtc_htotal = 1506 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1507 adjusted_mode->crtc_hsync_start = 1508 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1509 adjusted_mode->crtc_hsync_end = 1510 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1511 } 1512 1513 if (intel_dsi->dual_link) { 1514 adjusted_mode->crtc_hdisplay *= 2; 1515 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1516 adjusted_mode->crtc_hdisplay -= 1517 intel_dsi->pixel_overlap; 1518 adjusted_mode->crtc_htotal *= 2; 1519 } 1520 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1521 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1522 1523 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1524 if (intel_dsi->dual_link) { 1525 adjusted_mode->crtc_hsync_start *= 2; 1526 adjusted_mode->crtc_hsync_end *= 2; 1527 } 1528 } 1529 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1530 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1531 } 1532 1533 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1534 { 1535 struct drm_device *dev = intel_dsi->base.base.dev; 1536 struct drm_i915_private *dev_priv = to_i915(dev); 1537 enum transcoder dsi_trans; 1538 u32 val; 1539 1540 if (intel_dsi->ports == BIT(PORT_B)) 1541 dsi_trans = TRANSCODER_DSI_1; 1542 else 1543 dsi_trans = TRANSCODER_DSI_0; 1544 1545 val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 1546 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1547 } 1548 1549 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1550 struct intel_crtc_state *pipe_config) 1551 { 1552 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1553 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1554 I915_MODE_FLAG_DSI_USE_TE0; 1555 else if (intel_dsi->ports == BIT(PORT_B)) 1556 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1557 else 1558 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1559 } 1560 1561 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1562 struct intel_crtc_state *pipe_config) 1563 { 1564 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1565 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1566 1567 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1568 1569 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1570 if (intel_dsi->dual_link) 1571 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1572 1573 gen11_dsi_get_timings(encoder, pipe_config); 1574 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1575 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1576 1577 /* Get the details on which TE should be enabled */ 1578 if (is_cmd_mode(intel_dsi)) 1579 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1580 1581 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1582 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1583 } 1584 1585 static void gen11_dsi_sync_state(struct intel_encoder *encoder, 1586 const struct intel_crtc_state *crtc_state) 1587 { 1588 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1589 struct intel_crtc *intel_crtc; 1590 enum pipe pipe; 1591 1592 if (!crtc_state) 1593 return; 1594 1595 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1596 pipe = intel_crtc->pipe; 1597 1598 /* wa verify 1409054076:icl,jsl,ehl */ 1599 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && 1600 !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A)) 1601 drm_dbg_kms(&dev_priv->drm, 1602 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n", 1603 encoder->base.base.id, 1604 encoder->base.name); 1605 } 1606 1607 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1608 struct intel_crtc_state *crtc_state) 1609 { 1610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1611 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1612 int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10; 1613 bool use_dsc; 1614 int ret; 1615 1616 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1617 if (!use_dsc) 1618 return 0; 1619 1620 if (crtc_state->pipe_bpp < 8 * 3) 1621 return -EINVAL; 1622 1623 /* FIXME: split only when necessary */ 1624 if (crtc_state->dsc.slice_count > 1) 1625 crtc_state->dsc.dsc_split = true; 1626 1627 vdsc_cfg->convert_rgb = true; 1628 1629 /* FIXME: initialize from VBT */ 1630 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1631 1632 ret = intel_dsc_compute_params(crtc_state); 1633 if (ret) 1634 return ret; 1635 1636 /* DSI specific sanity checks on the common code */ 1637 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); 1638 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); 1639 drm_WARN_ON(&dev_priv->drm, 1640 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1641 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); 1642 drm_WARN_ON(&dev_priv->drm, 1643 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1644 1645 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1646 if (ret) 1647 return ret; 1648 1649 crtc_state->dsc.compression_enable = true; 1650 1651 return 0; 1652 } 1653 1654 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1655 struct intel_crtc_state *pipe_config, 1656 struct drm_connector_state *conn_state) 1657 { 1658 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1659 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 1660 base); 1661 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1662 struct drm_display_mode *adjusted_mode = 1663 &pipe_config->hw.adjusted_mode; 1664 int ret; 1665 1666 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1667 1668 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 1669 if (ret) 1670 return ret; 1671 1672 ret = intel_panel_fitting(pipe_config, conn_state); 1673 if (ret) 1674 return ret; 1675 1676 adjusted_mode->flags = 0; 1677 1678 /* Dual link goes to trancoder DSI'0' */ 1679 if (intel_dsi->ports == BIT(PORT_B)) 1680 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1681 else 1682 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1683 1684 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1685 pipe_config->pipe_bpp = 24; 1686 else 1687 pipe_config->pipe_bpp = 18; 1688 1689 pipe_config->clock_set = true; 1690 1691 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1692 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n"); 1693 1694 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1695 1696 /* 1697 * In case of TE GATE cmd mode, we 1698 * receive TE from the slave if 1699 * dual link is enabled 1700 */ 1701 if (is_cmd_mode(intel_dsi)) 1702 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1703 1704 return 0; 1705 } 1706 1707 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1708 struct intel_crtc_state *crtc_state) 1709 { 1710 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1711 1712 get_dsi_io_power_domains(i915, 1713 enc_to_intel_dsi(encoder)); 1714 } 1715 1716 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1717 enum pipe *pipe) 1718 { 1719 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1720 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1721 enum transcoder dsi_trans; 1722 intel_wakeref_t wakeref; 1723 enum port port; 1724 bool ret = false; 1725 u32 tmp; 1726 1727 wakeref = intel_display_power_get_if_enabled(dev_priv, 1728 encoder->power_domain); 1729 if (!wakeref) 1730 return false; 1731 1732 for_each_dsi_port(port, intel_dsi->ports) { 1733 dsi_trans = dsi_port_to_transcoder(port); 1734 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1735 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1736 case TRANS_DDI_EDP_INPUT_A_ON: 1737 *pipe = PIPE_A; 1738 break; 1739 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1740 *pipe = PIPE_B; 1741 break; 1742 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1743 *pipe = PIPE_C; 1744 break; 1745 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1746 *pipe = PIPE_D; 1747 break; 1748 default: 1749 drm_err(&dev_priv->drm, "Invalid PIPE input\n"); 1750 goto out; 1751 } 1752 1753 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1754 ret = tmp & PIPECONF_ENABLE; 1755 } 1756 out: 1757 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1758 return ret; 1759 } 1760 1761 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1762 struct intel_crtc_state *crtc_state) 1763 { 1764 if (crtc_state->dsc.compression_enable) { 1765 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1766 crtc_state->uapi.mode_changed = true; 1767 1768 return false; 1769 } 1770 1771 return true; 1772 } 1773 1774 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1775 { 1776 intel_encoder_destroy(encoder); 1777 } 1778 1779 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1780 .destroy = gen11_dsi_encoder_destroy, 1781 }; 1782 1783 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1784 .detect = intel_panel_detect, 1785 .late_register = intel_connector_register, 1786 .early_unregister = intel_connector_unregister, 1787 .destroy = intel_connector_destroy, 1788 .fill_modes = drm_helper_probe_single_connector_modes, 1789 .atomic_get_property = intel_digital_connector_atomic_get_property, 1790 .atomic_set_property = intel_digital_connector_atomic_set_property, 1791 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1792 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1793 }; 1794 1795 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1796 .get_modes = intel_dsi_get_modes, 1797 .mode_valid = gen11_dsi_mode_valid, 1798 .atomic_check = intel_digital_connector_atomic_check, 1799 }; 1800 1801 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1802 struct mipi_dsi_device *dsi) 1803 { 1804 return 0; 1805 } 1806 1807 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1808 struct mipi_dsi_device *dsi) 1809 { 1810 return 0; 1811 } 1812 1813 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1814 const struct mipi_dsi_msg *msg) 1815 { 1816 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1817 struct mipi_dsi_packet dsi_pkt; 1818 ssize_t ret; 1819 bool enable_lpdt = false; 1820 1821 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1822 if (ret < 0) 1823 return ret; 1824 1825 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1826 enable_lpdt = true; 1827 1828 /* only long packet contains payload */ 1829 if (mipi_dsi_packet_format_is_long(msg->type)) { 1830 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt); 1831 if (ret < 0) 1832 return ret; 1833 } 1834 1835 /* send packet header */ 1836 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt); 1837 if (ret < 0) 1838 return ret; 1839 1840 //TODO: add payload receive code if needed 1841 1842 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1843 1844 return ret; 1845 } 1846 1847 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1848 .attach = gen11_dsi_host_attach, 1849 .detach = gen11_dsi_host_detach, 1850 .transfer = gen11_dsi_host_transfer, 1851 }; 1852 1853 #define ICL_PREPARE_CNT_MAX 0x7 1854 #define ICL_CLK_ZERO_CNT_MAX 0xf 1855 #define ICL_TRAIL_CNT_MAX 0x7 1856 #define ICL_TCLK_PRE_CNT_MAX 0x3 1857 #define ICL_TCLK_POST_CNT_MAX 0x7 1858 #define ICL_HS_ZERO_CNT_MAX 0xf 1859 #define ICL_EXIT_ZERO_CNT_MAX 0x7 1860 1861 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1862 { 1863 struct drm_device *dev = intel_dsi->base.base.dev; 1864 struct drm_i915_private *dev_priv = to_i915(dev); 1865 struct intel_connector *connector = intel_dsi->attached_connector; 1866 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1867 u32 tlpx_ns; 1868 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1869 u32 ths_prepare_ns, tclk_trail_ns; 1870 u32 hs_zero_cnt; 1871 u32 tclk_pre_cnt, tclk_post_cnt; 1872 1873 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1874 1875 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1876 ths_prepare_ns = max(mipi_config->ths_prepare, 1877 mipi_config->tclk_prepare); 1878 1879 /* 1880 * prepare cnt in escape clocks 1881 * this field represents a hexadecimal value with a precision 1882 * of 1.2 – i.e. the most significant bit is the integer 1883 * and the least significant 2 bits are fraction bits. 1884 * so, the field can represent a range of 0.25 to 1.75 1885 */ 1886 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1887 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1888 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", 1889 prepare_cnt); 1890 prepare_cnt = ICL_PREPARE_CNT_MAX; 1891 } 1892 1893 /* clk zero count in escape clocks */ 1894 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1895 ths_prepare_ns, tlpx_ns); 1896 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1897 drm_dbg_kms(&dev_priv->drm, 1898 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1899 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1900 } 1901 1902 /* trail cnt in escape clocks*/ 1903 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1904 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1905 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", 1906 trail_cnt); 1907 trail_cnt = ICL_TRAIL_CNT_MAX; 1908 } 1909 1910 /* tclk pre count in escape clocks */ 1911 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1912 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1913 drm_dbg_kms(&dev_priv->drm, 1914 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1915 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1916 } 1917 1918 /* tclk post count in escape clocks */ 1919 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); 1920 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { 1921 drm_dbg_kms(&dev_priv->drm, 1922 "tclk_post_cnt out of range (%d)\n", 1923 tclk_post_cnt); 1924 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; 1925 } 1926 1927 /* hs zero cnt in escape clocks */ 1928 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1929 ths_prepare_ns, tlpx_ns); 1930 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1931 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", 1932 hs_zero_cnt); 1933 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1934 } 1935 1936 /* hs exit zero cnt in escape clocks */ 1937 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1938 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1939 drm_dbg_kms(&dev_priv->drm, 1940 "exit_zero_cnt out of range (%d)\n", 1941 exit_zero_cnt); 1942 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1943 } 1944 1945 /* clock lane dphy timings */ 1946 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1947 CLK_PREPARE(prepare_cnt) | 1948 CLK_ZERO_OVERRIDE | 1949 CLK_ZERO(clk_zero_cnt) | 1950 CLK_PRE_OVERRIDE | 1951 CLK_PRE(tclk_pre_cnt) | 1952 CLK_POST_OVERRIDE | 1953 CLK_POST(tclk_post_cnt) | 1954 CLK_TRAIL_OVERRIDE | 1955 CLK_TRAIL(trail_cnt)); 1956 1957 /* data lanes dphy timings */ 1958 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1959 HS_PREPARE(prepare_cnt) | 1960 HS_ZERO_OVERRIDE | 1961 HS_ZERO(hs_zero_cnt) | 1962 HS_TRAIL_OVERRIDE | 1963 HS_TRAIL(trail_cnt) | 1964 HS_EXIT_OVERRIDE | 1965 HS_EXIT(exit_zero_cnt)); 1966 1967 intel_dsi_log_params(intel_dsi); 1968 } 1969 1970 static void icl_dsi_add_properties(struct intel_connector *connector) 1971 { 1972 const struct drm_display_mode *fixed_mode = 1973 intel_panel_preferred_fixed_mode(connector); 1974 u32 allowed_scalers; 1975 1976 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | 1977 BIT(DRM_MODE_SCALE_FULLSCREEN) | 1978 BIT(DRM_MODE_SCALE_CENTER); 1979 1980 drm_connector_attach_scaling_mode_property(&connector->base, 1981 allowed_scalers); 1982 1983 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1984 1985 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1986 intel_dsi_get_panel_orientation(connector), 1987 fixed_mode->hdisplay, 1988 fixed_mode->vdisplay); 1989 } 1990 1991 void icl_dsi_init(struct drm_i915_private *dev_priv) 1992 { 1993 struct drm_device *dev = &dev_priv->drm; 1994 struct intel_dsi *intel_dsi; 1995 struct intel_encoder *encoder; 1996 struct intel_connector *intel_connector; 1997 struct drm_connector *connector; 1998 enum port port; 1999 2000 if (!intel_bios_is_dsi_present(dev_priv, &port)) 2001 return; 2002 2003 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 2004 if (!intel_dsi) 2005 return; 2006 2007 intel_connector = intel_connector_alloc(); 2008 if (!intel_connector) { 2009 kfree(intel_dsi); 2010 return; 2011 } 2012 2013 encoder = &intel_dsi->base; 2014 intel_dsi->attached_connector = intel_connector; 2015 connector = &intel_connector->base; 2016 2017 /* register DSI encoder with DRM subsystem */ 2018 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs, 2019 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 2020 2021 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 2022 encoder->pre_enable = gen11_dsi_pre_enable; 2023 encoder->enable = gen11_dsi_enable; 2024 encoder->disable = gen11_dsi_disable; 2025 encoder->post_disable = gen11_dsi_post_disable; 2026 encoder->port = port; 2027 encoder->get_config = gen11_dsi_get_config; 2028 encoder->sync_state = gen11_dsi_sync_state; 2029 encoder->update_pipe = intel_backlight_update; 2030 encoder->compute_config = gen11_dsi_compute_config; 2031 encoder->get_hw_state = gen11_dsi_get_hw_state; 2032 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 2033 encoder->type = INTEL_OUTPUT_DSI; 2034 encoder->cloneable = 0; 2035 encoder->pipe_mask = ~0; 2036 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 2037 encoder->get_power_domains = gen11_dsi_get_power_domains; 2038 encoder->disable_clock = gen11_dsi_gate_clocks; 2039 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 2040 2041 /* register DSI connector with DRM subsystem */ 2042 drm_connector_init(dev, connector, &gen11_dsi_connector_funcs, 2043 DRM_MODE_CONNECTOR_DSI); 2044 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 2045 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 2046 connector->interlace_allowed = false; 2047 connector->doublescan_allowed = false; 2048 intel_connector->get_hw_state = intel_connector_get_hw_state; 2049 2050 /* attach connector to encoder */ 2051 intel_connector_attach_encoder(intel_connector, encoder); 2052 2053 intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL, NULL); 2054 2055 mutex_lock(&dev->mode_config.mutex); 2056 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 2057 mutex_unlock(&dev->mode_config.mutex); 2058 2059 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2060 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); 2061 goto err; 2062 } 2063 2064 intel_panel_init(intel_connector); 2065 2066 intel_backlight_setup(intel_connector, INVALID_PIPE); 2067 2068 if (intel_connector->panel.vbt.dsi.config->dual_link) 2069 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 2070 else 2071 intel_dsi->ports = BIT(port); 2072 2073 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) 2074 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; 2075 2076 intel_dsi->dcs_backlight_ports = intel_connector->panel.vbt.dsi.bl_ports; 2077 2078 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) 2079 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; 2080 2081 intel_dsi->dcs_cabc_ports = intel_connector->panel.vbt.dsi.cabc_ports; 2082 2083 for_each_dsi_port(port, intel_dsi->ports) { 2084 struct intel_dsi_host *host; 2085 2086 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2087 if (!host) 2088 goto err; 2089 2090 intel_dsi->dsi_hosts[port] = host; 2091 } 2092 2093 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2094 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 2095 goto err; 2096 } 2097 2098 icl_dphy_param_init(intel_dsi); 2099 2100 icl_dsi_add_properties(intel_connector); 2101 return; 2102 2103 err: 2104 drm_connector_cleanup(connector); 2105 drm_encoder_cleanup(&encoder->base); 2106 kfree(intel_dsi); 2107 kfree(intel_connector); 2108 } 2109