1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_mipi_dsi.h> 30 31 #include "icl_dsi.h" 32 #include "icl_dsi_regs.h" 33 #include "intel_atomic.h" 34 #include "intel_backlight.h" 35 #include "intel_combo_phy.h" 36 #include "intel_combo_phy_regs.h" 37 #include "intel_connector.h" 38 #include "intel_crtc.h" 39 #include "intel_ddi.h" 40 #include "intel_de.h" 41 #include "intel_dsi.h" 42 #include "intel_dsi_vbt.h" 43 #include "intel_panel.h" 44 #include "intel_vdsc.h" 45 #include "skl_scaler.h" 46 #include "skl_universal_plane.h" 47 48 static int header_credits_available(struct drm_i915_private *dev_priv, 49 enum transcoder dsi_trans) 50 { 51 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 52 >> FREE_HEADER_CREDIT_SHIFT; 53 } 54 55 static int payload_credits_available(struct drm_i915_private *dev_priv, 56 enum transcoder dsi_trans) 57 { 58 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 59 >> FREE_PLOAD_CREDIT_SHIFT; 60 } 61 62 static bool wait_for_header_credits(struct drm_i915_private *dev_priv, 63 enum transcoder dsi_trans, int hdr_credit) 64 { 65 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= 66 hdr_credit, 100)) { 67 drm_err(&dev_priv->drm, "DSI header credits not released\n"); 68 return false; 69 } 70 71 return true; 72 } 73 74 static bool wait_for_payload_credits(struct drm_i915_private *dev_priv, 75 enum transcoder dsi_trans, int payld_credit) 76 { 77 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= 78 payld_credit, 100)) { 79 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); 80 return false; 81 } 82 83 return true; 84 } 85 86 static enum transcoder dsi_port_to_transcoder(enum port port) 87 { 88 if (port == PORT_A) 89 return TRANSCODER_DSI_0; 90 else 91 return TRANSCODER_DSI_1; 92 } 93 94 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 95 { 96 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 97 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 98 struct mipi_dsi_device *dsi; 99 enum port port; 100 enum transcoder dsi_trans; 101 int ret; 102 103 /* wait for header/payload credits to be released */ 104 for_each_dsi_port(port, intel_dsi->ports) { 105 dsi_trans = dsi_port_to_transcoder(port); 106 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 107 wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT); 108 } 109 110 /* send nop DCS command */ 111 for_each_dsi_port(port, intel_dsi->ports) { 112 dsi = intel_dsi->dsi_hosts[port]->device; 113 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 114 dsi->channel = 0; 115 ret = mipi_dsi_dcs_nop(dsi); 116 if (ret < 0) 117 drm_err(&dev_priv->drm, 118 "error sending DCS NOP command\n"); 119 } 120 121 /* wait for header credits to be released */ 122 for_each_dsi_port(port, intel_dsi->ports) { 123 dsi_trans = dsi_port_to_transcoder(port); 124 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 125 } 126 127 /* wait for LP TX in progress bit to be cleared */ 128 for_each_dsi_port(port, intel_dsi->ports) { 129 dsi_trans = dsi_port_to_transcoder(port); 130 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 131 LPTX_IN_PROGRESS), 20)) 132 drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); 133 } 134 } 135 136 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 137 const struct mipi_dsi_packet *packet) 138 { 139 struct intel_dsi *intel_dsi = host->intel_dsi; 140 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 141 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 142 const u8 *data = packet->payload; 143 u32 len = packet->payload_length; 144 int i, j; 145 146 /* payload queue can accept *256 bytes*, check limit */ 147 if (len > MAX_PLOAD_CREDIT * 4) { 148 drm_err(&i915->drm, "payload size exceeds max queue limit\n"); 149 return -EINVAL; 150 } 151 152 for (i = 0; i < len; i += 4) { 153 u32 tmp = 0; 154 155 if (!wait_for_payload_credits(i915, dsi_trans, 1)) 156 return -EBUSY; 157 158 for (j = 0; j < min_t(u32, len - i, 4); j++) 159 tmp |= *data++ << 8 * j; 160 161 intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp); 162 } 163 164 return 0; 165 } 166 167 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 168 const struct mipi_dsi_packet *packet, 169 bool enable_lpdt) 170 { 171 struct intel_dsi *intel_dsi = host->intel_dsi; 172 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 173 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 174 u32 tmp; 175 176 if (!wait_for_header_credits(dev_priv, dsi_trans, 1)) 177 return -EBUSY; 178 179 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); 180 181 if (packet->payload) 182 tmp |= PAYLOAD_PRESENT; 183 else 184 tmp &= ~PAYLOAD_PRESENT; 185 186 tmp &= ~VBLANK_FENCE; 187 188 if (enable_lpdt) 189 tmp |= LP_DATA_TRANSFER; 190 else 191 tmp &= ~LP_DATA_TRANSFER; 192 193 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 194 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); 195 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); 196 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); 197 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); 198 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); 199 200 return 0; 201 } 202 203 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 204 { 205 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 206 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 207 u32 tmp, mode_flags; 208 enum port port; 209 210 mode_flags = crtc_state->mode_flags; 211 212 /* 213 * case 1 also covers dual link 214 * In case of dual link, frame update should be set on 215 * DSI_0 216 */ 217 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 218 port = PORT_A; 219 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 220 port = PORT_B; 221 else 222 return; 223 224 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 225 tmp |= DSI_FRAME_UPDATE_REQUEST; 226 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 227 } 228 229 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 230 { 231 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 232 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 233 enum phy phy; 234 u32 tmp; 235 int lane; 236 237 for_each_dsi_phy(phy, intel_dsi->phys) { 238 /* 239 * Program voltage swing and pre-emphasis level values as per 240 * table in BSPEC under DDI buffer programing 241 */ 242 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 243 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 244 tmp |= SCALING_MODE_SEL(0x2); 245 tmp |= TAP2_DISABLE | TAP3_DISABLE; 246 tmp |= RTERM_SELECT(0x6); 247 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 248 249 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 250 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 251 tmp |= SCALING_MODE_SEL(0x2); 252 tmp |= TAP2_DISABLE | TAP3_DISABLE; 253 tmp |= RTERM_SELECT(0x6); 254 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 255 256 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 257 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 258 RCOMP_SCALAR_MASK); 259 tmp |= SWING_SEL_UPPER(0x2); 260 tmp |= SWING_SEL_LOWER(0x2); 261 tmp |= RCOMP_SCALAR(0x98); 262 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 263 264 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 265 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 266 RCOMP_SCALAR_MASK); 267 tmp |= SWING_SEL_UPPER(0x2); 268 tmp |= SWING_SEL_LOWER(0x2); 269 tmp |= RCOMP_SCALAR(0x98); 270 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 271 272 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 273 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 274 CURSOR_COEFF_MASK); 275 tmp |= POST_CURSOR_1(0x0); 276 tmp |= POST_CURSOR_2(0x0); 277 tmp |= CURSOR_COEFF(0x3f); 278 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 279 280 for (lane = 0; lane <= 3; lane++) { 281 /* Bspec: must not use GRP register for write */ 282 tmp = intel_de_read(dev_priv, 283 ICL_PORT_TX_DW4_LN(lane, phy)); 284 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 285 CURSOR_COEFF_MASK); 286 tmp |= POST_CURSOR_1(0x0); 287 tmp |= POST_CURSOR_2(0x0); 288 tmp |= CURSOR_COEFF(0x3f); 289 intel_de_write(dev_priv, 290 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 291 } 292 } 293 } 294 295 static void configure_dual_link_mode(struct intel_encoder *encoder, 296 const struct intel_crtc_state *pipe_config) 297 { 298 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 299 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 300 u32 dss_ctl1; 301 302 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); 303 dss_ctl1 |= SPLITTER_ENABLE; 304 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 305 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 306 307 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 308 const struct drm_display_mode *adjusted_mode = 309 &pipe_config->hw.adjusted_mode; 310 u32 dss_ctl2; 311 u16 hactive = adjusted_mode->crtc_hdisplay; 312 u16 dl_buffer_depth; 313 314 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 315 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 316 317 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 318 drm_err(&dev_priv->drm, 319 "DL buffer depth exceed max value\n"); 320 321 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 322 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 323 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); 324 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; 325 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 326 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); 327 } else { 328 /* Interleave */ 329 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 330 } 331 332 intel_de_write(dev_priv, DSS_CTL1, dss_ctl1); 333 } 334 335 /* aka DSI 8X clock */ 336 static int afe_clk(struct intel_encoder *encoder, 337 const struct intel_crtc_state *crtc_state) 338 { 339 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 340 int bpp; 341 342 if (crtc_state->dsc.compression_enable) 343 bpp = crtc_state->dsc.compressed_bpp; 344 else 345 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 346 347 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 348 } 349 350 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 351 const struct intel_crtc_state *crtc_state) 352 { 353 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 354 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 355 enum port port; 356 int afe_clk_khz; 357 int theo_word_clk, act_word_clk; 358 u32 esc_clk_div_m, esc_clk_div_m_phy; 359 360 afe_clk_khz = afe_clk(encoder, crtc_state); 361 362 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 363 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 364 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 365 esc_clk_div_m = act_word_clk * 8; 366 esc_clk_div_m_phy = (act_word_clk - 1) / 2; 367 } else { 368 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 369 } 370 371 for_each_dsi_port(port, intel_dsi->ports) { 372 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), 373 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 374 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); 375 } 376 377 for_each_dsi_port(port, intel_dsi->ports) { 378 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port), 379 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 380 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); 381 } 382 383 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 384 for_each_dsi_port(port, intel_dsi->ports) { 385 intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8), 386 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); 387 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8)); 388 } 389 } 390 } 391 392 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, 393 struct intel_dsi *intel_dsi) 394 { 395 enum port port; 396 397 for_each_dsi_port(port, intel_dsi->ports) { 398 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); 399 intel_dsi->io_wakeref[port] = 400 intel_display_power_get(dev_priv, 401 port == PORT_A ? 402 POWER_DOMAIN_PORT_DDI_A_IO : 403 POWER_DOMAIN_PORT_DDI_B_IO); 404 } 405 } 406 407 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 408 { 409 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 410 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 411 enum port port; 412 u32 tmp; 413 414 for_each_dsi_port(port, intel_dsi->ports) { 415 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 416 tmp |= COMBO_PHY_MODE_DSI; 417 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 418 } 419 420 get_dsi_io_power_domains(dev_priv, intel_dsi); 421 } 422 423 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 424 { 425 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 426 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 427 enum phy phy; 428 429 for_each_dsi_phy(phy, intel_dsi->phys) 430 intel_combo_phy_power_up_lanes(dev_priv, phy, true, 431 intel_dsi->lane_count, false); 432 } 433 434 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 435 { 436 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 437 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 438 enum phy phy; 439 u32 tmp; 440 int lane; 441 442 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 443 for_each_dsi_phy(phy, intel_dsi->phys) { 444 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 445 tmp &= ~LOADGEN_SELECT; 446 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 447 for (lane = 0; lane <= 3; lane++) { 448 tmp = intel_de_read(dev_priv, 449 ICL_PORT_TX_DW4_LN(lane, phy)); 450 tmp &= ~LOADGEN_SELECT; 451 if (lane != 2) 452 tmp |= LOADGEN_SELECT; 453 intel_de_write(dev_priv, 454 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 455 } 456 } 457 458 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 459 for_each_dsi_phy(phy, intel_dsi->phys) { 460 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 461 tmp &= ~FRC_LATENCY_OPTIM_MASK; 462 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 463 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 464 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 465 tmp &= ~FRC_LATENCY_OPTIM_MASK; 466 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 467 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 468 469 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 470 if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) { 471 tmp = intel_de_read(dev_priv, 472 ICL_PORT_PCS_DW1_AUX(phy)); 473 tmp &= ~LATENCY_OPTIM_MASK; 474 tmp |= LATENCY_OPTIM_VAL(0); 475 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), 476 tmp); 477 478 tmp = intel_de_read(dev_priv, 479 ICL_PORT_PCS_DW1_LN(0, phy)); 480 tmp &= ~LATENCY_OPTIM_MASK; 481 tmp |= LATENCY_OPTIM_VAL(0x1); 482 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), 483 tmp); 484 } 485 } 486 487 } 488 489 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 490 { 491 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 492 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 493 u32 tmp; 494 enum phy phy; 495 496 /* clear common keeper enable bit */ 497 for_each_dsi_phy(phy, intel_dsi->phys) { 498 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 499 tmp &= ~COMMON_KEEPER_EN; 500 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp); 501 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy)); 502 tmp &= ~COMMON_KEEPER_EN; 503 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp); 504 } 505 506 /* 507 * Set SUS Clock Config bitfield to 11b 508 * Note: loadgen select program is done 509 * as part of lane phy sequence configuration 510 */ 511 for_each_dsi_phy(phy, intel_dsi->phys) { 512 tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 513 tmp |= SUS_CLOCK_CONFIG; 514 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp); 515 } 516 517 /* Clear training enable to change swing values */ 518 for_each_dsi_phy(phy, intel_dsi->phys) { 519 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 520 tmp &= ~TX_TRAINING_EN; 521 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 522 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 523 tmp &= ~TX_TRAINING_EN; 524 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 525 } 526 527 /* Program swing and de-emphasis */ 528 dsi_program_swing_and_deemphasis(encoder); 529 530 /* Set training enable to trigger update */ 531 for_each_dsi_phy(phy, intel_dsi->phys) { 532 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 533 tmp |= TX_TRAINING_EN; 534 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 535 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 536 tmp |= TX_TRAINING_EN; 537 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 538 } 539 } 540 541 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 542 { 543 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 544 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 545 u32 tmp; 546 enum port port; 547 548 for_each_dsi_port(port, intel_dsi->ports) { 549 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 550 tmp |= DDI_BUF_CTL_ENABLE; 551 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 552 553 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 554 DDI_BUF_IS_IDLE), 555 500)) 556 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", 557 port_name(port)); 558 } 559 } 560 561 static void 562 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 563 const struct intel_crtc_state *crtc_state) 564 { 565 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 566 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 567 u32 tmp; 568 enum port port; 569 enum phy phy; 570 571 /* Program T-INIT master registers */ 572 for_each_dsi_port(port, intel_dsi->ports) { 573 tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port)); 574 tmp &= ~DSI_T_INIT_MASTER_MASK; 575 tmp |= intel_dsi->init_count; 576 intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp); 577 } 578 579 /* Program DPHY clock lanes timings */ 580 for_each_dsi_port(port, intel_dsi->ports) { 581 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port), 582 intel_dsi->dphy_reg); 583 584 /* shadow register inside display core */ 585 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port), 586 intel_dsi->dphy_reg); 587 } 588 589 /* Program DPHY data lanes timings */ 590 for_each_dsi_port(port, intel_dsi->ports) { 591 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port), 592 intel_dsi->dphy_data_lane_reg); 593 594 /* shadow register inside display core */ 595 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port), 596 intel_dsi->dphy_data_lane_reg); 597 } 598 599 /* 600 * If DSI link operating at or below an 800 MHz, 601 * TA_SURE should be override and programmed to 602 * a value '0' inside TA_PARAM_REGISTERS otherwise 603 * leave all fields at HW default values. 604 */ 605 if (DISPLAY_VER(dev_priv) == 11) { 606 if (afe_clk(encoder, crtc_state) <= 800000) { 607 for_each_dsi_port(port, intel_dsi->ports) { 608 tmp = intel_de_read(dev_priv, 609 DPHY_TA_TIMING_PARAM(port)); 610 tmp &= ~TA_SURE_MASK; 611 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 612 intel_de_write(dev_priv, 613 DPHY_TA_TIMING_PARAM(port), 614 tmp); 615 616 /* shadow register inside display core */ 617 tmp = intel_de_read(dev_priv, 618 DSI_TA_TIMING_PARAM(port)); 619 tmp &= ~TA_SURE_MASK; 620 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 621 intel_de_write(dev_priv, 622 DSI_TA_TIMING_PARAM(port), tmp); 623 } 624 } 625 } 626 627 if (IS_JSL_EHL(dev_priv)) { 628 for_each_dsi_phy(phy, intel_dsi->phys) { 629 tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy)); 630 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; 631 intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp); 632 } 633 } 634 } 635 636 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 637 { 638 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 639 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 640 u32 tmp; 641 enum phy phy; 642 643 mutex_lock(&dev_priv->dpll.lock); 644 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 645 for_each_dsi_phy(phy, intel_dsi->phys) 646 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 647 648 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 649 mutex_unlock(&dev_priv->dpll.lock); 650 } 651 652 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 653 { 654 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 655 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 656 u32 tmp; 657 enum phy phy; 658 659 mutex_lock(&dev_priv->dpll.lock); 660 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 661 for_each_dsi_phy(phy, intel_dsi->phys) 662 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 663 664 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 665 mutex_unlock(&dev_priv->dpll.lock); 666 } 667 668 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 669 { 670 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 671 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 672 bool clock_enabled = false; 673 enum phy phy; 674 u32 tmp; 675 676 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 677 678 for_each_dsi_phy(phy, intel_dsi->phys) { 679 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 680 clock_enabled = true; 681 } 682 683 return clock_enabled; 684 } 685 686 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 687 const struct intel_crtc_state *crtc_state) 688 { 689 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 690 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 691 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 692 enum phy phy; 693 u32 val; 694 695 mutex_lock(&dev_priv->dpll.lock); 696 697 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 698 for_each_dsi_phy(phy, intel_dsi->phys) { 699 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 700 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 701 } 702 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 703 704 for_each_dsi_phy(phy, intel_dsi->phys) { 705 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 706 } 707 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 708 709 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 710 711 mutex_unlock(&dev_priv->dpll.lock); 712 } 713 714 static void 715 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 716 const struct intel_crtc_state *pipe_config) 717 { 718 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 719 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 720 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 721 enum pipe pipe = crtc->pipe; 722 u32 tmp; 723 enum port port; 724 enum transcoder dsi_trans; 725 726 for_each_dsi_port(port, intel_dsi->ports) { 727 dsi_trans = dsi_port_to_transcoder(port); 728 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 729 730 if (intel_dsi->eotp_pkt) 731 tmp &= ~EOTP_DISABLED; 732 else 733 tmp |= EOTP_DISABLED; 734 735 /* enable link calibration if freq > 1.5Gbps */ 736 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 737 tmp &= ~LINK_CALIBRATION_MASK; 738 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 739 } 740 741 /* configure continuous clock */ 742 tmp &= ~CONTINUOUS_CLK_MASK; 743 if (intel_dsi->clock_stop) 744 tmp |= CLK_ENTER_LP_AFTER_DATA; 745 else 746 tmp |= CLK_HS_CONTINUOUS; 747 748 /* configure buffer threshold limit to minimum */ 749 tmp &= ~PIX_BUF_THRESHOLD_MASK; 750 tmp |= PIX_BUF_THRESHOLD_1_4; 751 752 /* set virtual channel to '0' */ 753 tmp &= ~PIX_VIRT_CHAN_MASK; 754 tmp |= PIX_VIRT_CHAN(0); 755 756 /* program BGR transmission */ 757 if (intel_dsi->bgr_enabled) 758 tmp |= BGR_TRANSMISSION; 759 760 /* select pixel format */ 761 tmp &= ~PIX_FMT_MASK; 762 if (pipe_config->dsc.compression_enable) { 763 tmp |= PIX_FMT_COMPRESSED; 764 } else { 765 switch (intel_dsi->pixel_format) { 766 default: 767 MISSING_CASE(intel_dsi->pixel_format); 768 fallthrough; 769 case MIPI_DSI_FMT_RGB565: 770 tmp |= PIX_FMT_RGB565; 771 break; 772 case MIPI_DSI_FMT_RGB666_PACKED: 773 tmp |= PIX_FMT_RGB666_PACKED; 774 break; 775 case MIPI_DSI_FMT_RGB666: 776 tmp |= PIX_FMT_RGB666_LOOSE; 777 break; 778 case MIPI_DSI_FMT_RGB888: 779 tmp |= PIX_FMT_RGB888; 780 break; 781 } 782 } 783 784 if (DISPLAY_VER(dev_priv) >= 12) { 785 if (is_vid_mode(intel_dsi)) 786 tmp |= BLANKING_PACKET_ENABLE; 787 } 788 789 /* program DSI operation mode */ 790 if (is_vid_mode(intel_dsi)) { 791 tmp &= ~OP_MODE_MASK; 792 switch (intel_dsi->video_mode) { 793 default: 794 MISSING_CASE(intel_dsi->video_mode); 795 fallthrough; 796 case NON_BURST_SYNC_EVENTS: 797 tmp |= VIDEO_MODE_SYNC_EVENT; 798 break; 799 case NON_BURST_SYNC_PULSE: 800 tmp |= VIDEO_MODE_SYNC_PULSE; 801 break; 802 } 803 } else { 804 /* 805 * FIXME: Retrieve this info from VBT. 806 * As per the spec when dsi transcoder is operating 807 * in TE GATE mode, TE comes from GPIO 808 * which is UTIL PIN for DSI 0. 809 * Also this GPIO would not be used for other 810 * purposes is an assumption. 811 */ 812 tmp &= ~OP_MODE_MASK; 813 tmp |= CMD_MODE_TE_GATE; 814 tmp |= TE_SOURCE_GPIO; 815 } 816 817 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 818 } 819 820 /* enable port sync mode if dual link */ 821 if (intel_dsi->dual_link) { 822 for_each_dsi_port(port, intel_dsi->ports) { 823 dsi_trans = dsi_port_to_transcoder(port); 824 tmp = intel_de_read(dev_priv, 825 TRANS_DDI_FUNC_CTL2(dsi_trans)); 826 tmp |= PORT_SYNC_MODE_ENABLE; 827 intel_de_write(dev_priv, 828 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 829 } 830 831 /* configure stream splitting */ 832 configure_dual_link_mode(encoder, pipe_config); 833 } 834 835 for_each_dsi_port(port, intel_dsi->ports) { 836 dsi_trans = dsi_port_to_transcoder(port); 837 838 /* select data lane width */ 839 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 840 tmp &= ~DDI_PORT_WIDTH_MASK; 841 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); 842 843 /* select input pipe */ 844 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 845 switch (pipe) { 846 default: 847 MISSING_CASE(pipe); 848 fallthrough; 849 case PIPE_A: 850 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 851 break; 852 case PIPE_B: 853 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 854 break; 855 case PIPE_C: 856 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 857 break; 858 case PIPE_D: 859 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 860 break; 861 } 862 863 /* enable DDI buffer */ 864 tmp |= TRANS_DDI_FUNC_ENABLE; 865 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 866 } 867 868 /* wait for link ready */ 869 for_each_dsi_port(port, intel_dsi->ports) { 870 dsi_trans = dsi_port_to_transcoder(port); 871 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) & 872 LINK_READY), 2500)) 873 drm_err(&dev_priv->drm, "DSI link not ready\n"); 874 } 875 } 876 877 static void 878 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 879 const struct intel_crtc_state *crtc_state) 880 { 881 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 882 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 883 const struct drm_display_mode *adjusted_mode = 884 &crtc_state->hw.adjusted_mode; 885 enum port port; 886 enum transcoder dsi_trans; 887 /* horizontal timings */ 888 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 889 u16 hback_porch; 890 /* vertical timings */ 891 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 892 int mul = 1, div = 1; 893 894 /* 895 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 896 * for slower link speed if DSC is enabled. 897 * 898 * The compression frequency ratio is the ratio between compressed and 899 * non-compressed link speeds, and simplifies down to the ratio between 900 * compressed and non-compressed bpp. 901 */ 902 if (crtc_state->dsc.compression_enable) { 903 mul = crtc_state->dsc.compressed_bpp; 904 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 905 } 906 907 hactive = adjusted_mode->crtc_hdisplay; 908 909 if (is_vid_mode(intel_dsi)) 910 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 911 else 912 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 913 914 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 915 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 916 hsync_size = hsync_end - hsync_start; 917 hback_porch = (adjusted_mode->crtc_htotal - 918 adjusted_mode->crtc_hsync_end); 919 vactive = adjusted_mode->crtc_vdisplay; 920 921 if (is_vid_mode(intel_dsi)) { 922 vtotal = adjusted_mode->crtc_vtotal; 923 } else { 924 int bpp, line_time_us, byte_clk_period_ns; 925 926 if (crtc_state->dsc.compression_enable) 927 bpp = crtc_state->dsc.compressed_bpp; 928 else 929 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 930 931 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 932 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 933 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 934 } 935 vsync_start = adjusted_mode->crtc_vsync_start; 936 vsync_end = adjusted_mode->crtc_vsync_end; 937 vsync_shift = hsync_start - htotal / 2; 938 939 if (intel_dsi->dual_link) { 940 hactive /= 2; 941 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 942 hactive += intel_dsi->pixel_overlap; 943 htotal /= 2; 944 } 945 946 /* minimum hactive as per bspec: 256 pixels */ 947 if (adjusted_mode->crtc_hdisplay < 256) 948 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); 949 950 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 951 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 952 drm_err(&dev_priv->drm, 953 "hactive pixels are not multiple of 4\n"); 954 955 /* program TRANS_HTOTAL register */ 956 for_each_dsi_port(port, intel_dsi->ports) { 957 dsi_trans = dsi_port_to_transcoder(port); 958 intel_de_write(dev_priv, HTOTAL(dsi_trans), 959 (hactive - 1) | ((htotal - 1) << 16)); 960 } 961 962 /* TRANS_HSYNC register to be programmed only for video mode */ 963 if (is_vid_mode(intel_dsi)) { 964 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { 965 /* BSPEC: hsync size should be atleast 16 pixels */ 966 if (hsync_size < 16) 967 drm_err(&dev_priv->drm, 968 "hsync size < 16 pixels\n"); 969 } 970 971 if (hback_porch < 16) 972 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); 973 974 if (intel_dsi->dual_link) { 975 hsync_start /= 2; 976 hsync_end /= 2; 977 } 978 979 for_each_dsi_port(port, intel_dsi->ports) { 980 dsi_trans = dsi_port_to_transcoder(port); 981 intel_de_write(dev_priv, HSYNC(dsi_trans), 982 (hsync_start - 1) | ((hsync_end - 1) << 16)); 983 } 984 } 985 986 /* program TRANS_VTOTAL register */ 987 for_each_dsi_port(port, intel_dsi->ports) { 988 dsi_trans = dsi_port_to_transcoder(port); 989 /* 990 * FIXME: Programing this by assuming progressive mode, since 991 * non-interlaced info from VBT is not saved inside 992 * struct drm_display_mode. 993 * For interlace mode: program required pixel minus 2 994 */ 995 intel_de_write(dev_priv, VTOTAL(dsi_trans), 996 (vactive - 1) | ((vtotal - 1) << 16)); 997 } 998 999 if (vsync_end < vsync_start || vsync_end > vtotal) 1000 drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); 1001 1002 if (vsync_start < vactive) 1003 drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); 1004 1005 /* program TRANS_VSYNC register for video mode only */ 1006 if (is_vid_mode(intel_dsi)) { 1007 for_each_dsi_port(port, intel_dsi->ports) { 1008 dsi_trans = dsi_port_to_transcoder(port); 1009 intel_de_write(dev_priv, VSYNC(dsi_trans), 1010 (vsync_start - 1) | ((vsync_end - 1) << 16)); 1011 } 1012 } 1013 1014 /* 1015 * FIXME: It has to be programmed only for video modes and interlaced 1016 * modes. Put the check condition here once interlaced 1017 * info available as described above. 1018 * program TRANS_VSYNCSHIFT register 1019 */ 1020 if (is_vid_mode(intel_dsi)) { 1021 for_each_dsi_port(port, intel_dsi->ports) { 1022 dsi_trans = dsi_port_to_transcoder(port); 1023 intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans), 1024 vsync_shift); 1025 } 1026 } 1027 1028 /* program TRANS_VBLANK register, should be same as vtotal programmed */ 1029 if (DISPLAY_VER(dev_priv) >= 12) { 1030 for_each_dsi_port(port, intel_dsi->ports) { 1031 dsi_trans = dsi_port_to_transcoder(port); 1032 intel_de_write(dev_priv, VBLANK(dsi_trans), 1033 (vactive - 1) | ((vtotal - 1) << 16)); 1034 } 1035 } 1036 } 1037 1038 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1039 { 1040 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1041 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1042 enum port port; 1043 enum transcoder dsi_trans; 1044 u32 tmp; 1045 1046 for_each_dsi_port(port, intel_dsi->ports) { 1047 dsi_trans = dsi_port_to_transcoder(port); 1048 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1049 tmp |= PIPECONF_ENABLE; 1050 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1051 1052 /* wait for transcoder to be enabled */ 1053 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), 1054 PIPECONF_STATE_ENABLE, 10)) 1055 drm_err(&dev_priv->drm, 1056 "DSI transcoder not enabled\n"); 1057 } 1058 } 1059 1060 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1061 const struct intel_crtc_state *crtc_state) 1062 { 1063 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1064 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1065 enum port port; 1066 enum transcoder dsi_trans; 1067 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1068 1069 /* 1070 * escape clock count calculation: 1071 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1072 * UI (nsec) = (10^6)/Bitrate 1073 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1074 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1075 */ 1076 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1077 mul = 8 * 1000000; 1078 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1079 divisor); 1080 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1081 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1082 1083 for_each_dsi_port(port, intel_dsi->ports) { 1084 dsi_trans = dsi_port_to_transcoder(port); 1085 1086 /* program hst_tx_timeout */ 1087 tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans)); 1088 tmp &= ~HSTX_TIMEOUT_VALUE_MASK; 1089 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout); 1090 intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp); 1091 1092 /* FIXME: DSI_CALIB_TO */ 1093 1094 /* program lp_rx_host timeout */ 1095 tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans)); 1096 tmp &= ~LPRX_TIMEOUT_VALUE_MASK; 1097 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout); 1098 intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp); 1099 1100 /* FIXME: DSI_PWAIT_TO */ 1101 1102 /* program turn around timeout */ 1103 tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans)); 1104 tmp &= ~TA_TIMEOUT_VALUE_MASK; 1105 tmp |= TA_TIMEOUT_VALUE(ta_timeout); 1106 intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp); 1107 } 1108 } 1109 1110 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1111 bool enable) 1112 { 1113 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1114 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1115 u32 tmp; 1116 1117 /* 1118 * used as TE i/p for DSI0, 1119 * for dual link/DSI1 TE is from slave DSI1 1120 * through GPIO. 1121 */ 1122 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1123 return; 1124 1125 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL); 1126 1127 if (enable) { 1128 tmp |= UTIL_PIN_DIRECTION_INPUT; 1129 tmp |= UTIL_PIN_ENABLE; 1130 } else { 1131 tmp &= ~UTIL_PIN_ENABLE; 1132 } 1133 intel_de_write(dev_priv, UTIL_PIN_CTL, tmp); 1134 } 1135 1136 static void 1137 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1138 const struct intel_crtc_state *crtc_state) 1139 { 1140 /* step 4a: power up all lanes of the DDI used by DSI */ 1141 gen11_dsi_power_up_lanes(encoder); 1142 1143 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1144 gen11_dsi_config_phy_lanes_sequence(encoder); 1145 1146 /* step 4c: configure voltage swing and skew */ 1147 gen11_dsi_voltage_swing_program_seq(encoder); 1148 1149 /* enable DDI buffer */ 1150 gen11_dsi_enable_ddi_buffer(encoder); 1151 1152 /* setup D-PHY timings */ 1153 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1154 1155 /* Since transcoder is configured to take events from GPIO */ 1156 gen11_dsi_config_util_pin(encoder, true); 1157 1158 /* step 4h: setup DSI protocol timeouts */ 1159 gen11_dsi_setup_timeouts(encoder, crtc_state); 1160 1161 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1162 gen11_dsi_configure_transcoder(encoder, crtc_state); 1163 1164 /* Step 4l: Gate DDI clocks */ 1165 gen11_dsi_gate_clocks(encoder); 1166 } 1167 1168 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1169 { 1170 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1171 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1172 struct mipi_dsi_device *dsi; 1173 enum port port; 1174 enum transcoder dsi_trans; 1175 u32 tmp; 1176 int ret; 1177 1178 /* set maximum return packet size */ 1179 for_each_dsi_port(port, intel_dsi->ports) { 1180 dsi_trans = dsi_port_to_transcoder(port); 1181 1182 /* 1183 * FIXME: This uses the number of DW's currently in the payload 1184 * receive queue. This is probably not what we want here. 1185 */ 1186 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans)); 1187 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1188 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1189 tmp = tmp * 4; 1190 dsi = intel_dsi->dsi_hosts[port]->device; 1191 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1192 if (ret < 0) 1193 drm_err(&dev_priv->drm, 1194 "error setting max return pkt size%d\n", tmp); 1195 } 1196 1197 /* panel power on related mipi dsi vbt sequences */ 1198 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1199 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 1200 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1201 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1202 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1203 1204 /* ensure all panel commands dispatched before enabling transcoder */ 1205 wait_for_cmds_dispatched_to_panel(encoder); 1206 } 1207 1208 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1209 struct intel_encoder *encoder, 1210 const struct intel_crtc_state *crtc_state, 1211 const struct drm_connector_state *conn_state) 1212 { 1213 /* step2: enable IO power */ 1214 gen11_dsi_enable_io_power(encoder); 1215 1216 /* step3: enable DSI PLL */ 1217 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1218 } 1219 1220 static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1221 struct intel_encoder *encoder, 1222 const struct intel_crtc_state *pipe_config, 1223 const struct drm_connector_state *conn_state) 1224 { 1225 /* step3b */ 1226 gen11_dsi_map_pll(encoder, pipe_config); 1227 1228 /* step4: enable DSI port and DPHY */ 1229 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1230 1231 /* step5: program and powerup panel */ 1232 gen11_dsi_powerup_panel(encoder); 1233 1234 intel_dsc_dsi_pps_write(encoder, pipe_config); 1235 1236 /* step6c: configure transcoder timings */ 1237 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1238 } 1239 1240 /* 1241 * Wa_1409054076:icl,jsl,ehl 1242 * When pipe A is disabled and MIPI DSI is enabled on pipe B, 1243 * the AMT KVMR feature will incorrectly see pipe A as enabled. 1244 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave 1245 * it set while DSI is enabled on pipe B 1246 */ 1247 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, 1248 enum pipe pipe, bool enable) 1249 { 1250 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1251 1252 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) 1253 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1254 IGNORE_KVMR_PIPE_A, 1255 enable ? IGNORE_KVMR_PIPE_A : 0); 1256 } 1257 1258 /* 1259 * Wa_16012360555:adl-p 1260 * SW will have to program the "LP to HS Wakeup Guardband" 1261 * to account for the repeaters on the HS Request/Ready 1262 * PPI signaling between the Display engine and the DPHY. 1263 */ 1264 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) 1265 { 1266 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1267 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1268 enum port port; 1269 1270 if (DISPLAY_VER(i915) == 13) { 1271 for_each_dsi_port(port, intel_dsi->ports) 1272 intel_de_rmw(i915, TGL_DSI_CHKN_REG(port), 1273 TGL_DSI_CHKN_LSHS_GB_MASK, 1274 TGL_DSI_CHKN_LSHS_GB(4)); 1275 } 1276 } 1277 1278 static void gen11_dsi_enable(struct intel_atomic_state *state, 1279 struct intel_encoder *encoder, 1280 const struct intel_crtc_state *crtc_state, 1281 const struct drm_connector_state *conn_state) 1282 { 1283 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1284 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 1285 1286 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 1287 1288 /* Wa_1409054076:icl,jsl,ehl */ 1289 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); 1290 1291 /* Wa_16012360555:adl-p */ 1292 adlp_set_lp_hs_wakeup_gb(encoder); 1293 1294 /* step6d: enable dsi transcoder */ 1295 gen11_dsi_enable_transcoder(encoder); 1296 1297 /* step7: enable backlight */ 1298 intel_backlight_enable(crtc_state, conn_state); 1299 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1300 1301 intel_crtc_vblank_on(crtc_state); 1302 } 1303 1304 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1305 { 1306 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1307 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1308 enum port port; 1309 enum transcoder dsi_trans; 1310 u32 tmp; 1311 1312 for_each_dsi_port(port, intel_dsi->ports) { 1313 dsi_trans = dsi_port_to_transcoder(port); 1314 1315 /* disable transcoder */ 1316 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1317 tmp &= ~PIPECONF_ENABLE; 1318 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1319 1320 /* wait for transcoder to be disabled */ 1321 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), 1322 PIPECONF_STATE_ENABLE, 50)) 1323 drm_err(&dev_priv->drm, 1324 "DSI trancoder not disabled\n"); 1325 } 1326 } 1327 1328 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1329 { 1330 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1331 1332 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1333 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1334 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1335 1336 /* ensure cmds dispatched to panel */ 1337 wait_for_cmds_dispatched_to_panel(encoder); 1338 } 1339 1340 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1341 { 1342 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1343 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1344 enum port port; 1345 enum transcoder dsi_trans; 1346 u32 tmp; 1347 1348 /* disable periodic update mode */ 1349 if (is_cmd_mode(intel_dsi)) { 1350 for_each_dsi_port(port, intel_dsi->ports) { 1351 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 1352 tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE; 1353 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 1354 } 1355 } 1356 1357 /* put dsi link in ULPS */ 1358 for_each_dsi_port(port, intel_dsi->ports) { 1359 dsi_trans = dsi_port_to_transcoder(port); 1360 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)); 1361 tmp |= LINK_ENTER_ULPS; 1362 tmp &= ~LINK_ULPS_TYPE_LP11; 1363 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp); 1364 1365 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 1366 LINK_IN_ULPS), 1367 10)) 1368 drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); 1369 } 1370 1371 /* disable ddi function */ 1372 for_each_dsi_port(port, intel_dsi->ports) { 1373 dsi_trans = dsi_port_to_transcoder(port); 1374 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1375 tmp &= ~TRANS_DDI_FUNC_ENABLE; 1376 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 1377 } 1378 1379 /* disable port sync mode if dual link */ 1380 if (intel_dsi->dual_link) { 1381 for_each_dsi_port(port, intel_dsi->ports) { 1382 dsi_trans = dsi_port_to_transcoder(port); 1383 tmp = intel_de_read(dev_priv, 1384 TRANS_DDI_FUNC_CTL2(dsi_trans)); 1385 tmp &= ~PORT_SYNC_MODE_ENABLE; 1386 intel_de_write(dev_priv, 1387 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 1388 } 1389 } 1390 } 1391 1392 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1393 { 1394 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1395 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1396 u32 tmp; 1397 enum port port; 1398 1399 gen11_dsi_ungate_clocks(encoder); 1400 for_each_dsi_port(port, intel_dsi->ports) { 1401 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1402 tmp &= ~DDI_BUF_CTL_ENABLE; 1403 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 1404 1405 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1406 DDI_BUF_IS_IDLE), 1407 8)) 1408 drm_err(&dev_priv->drm, 1409 "DDI port:%c buffer not idle\n", 1410 port_name(port)); 1411 } 1412 gen11_dsi_gate_clocks(encoder); 1413 } 1414 1415 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1416 { 1417 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1418 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1419 enum port port; 1420 u32 tmp; 1421 1422 for_each_dsi_port(port, intel_dsi->ports) { 1423 intel_wakeref_t wakeref; 1424 1425 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1426 intel_display_power_put(dev_priv, 1427 port == PORT_A ? 1428 POWER_DOMAIN_PORT_DDI_A_IO : 1429 POWER_DOMAIN_PORT_DDI_B_IO, 1430 wakeref); 1431 } 1432 1433 /* set mode to DDI */ 1434 for_each_dsi_port(port, intel_dsi->ports) { 1435 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 1436 tmp &= ~COMBO_PHY_MODE_DSI; 1437 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 1438 } 1439 } 1440 1441 static void gen11_dsi_disable(struct intel_atomic_state *state, 1442 struct intel_encoder *encoder, 1443 const struct intel_crtc_state *old_crtc_state, 1444 const struct drm_connector_state *old_conn_state) 1445 { 1446 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1447 struct intel_crtc *crtc = to_intel_crtc(old_conn_state->crtc); 1448 1449 /* step1: turn off backlight */ 1450 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1451 intel_backlight_disable(old_conn_state); 1452 1453 /* step2d,e: disable transcoder and wait */ 1454 gen11_dsi_disable_transcoder(encoder); 1455 1456 /* Wa_1409054076:icl,jsl,ehl */ 1457 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); 1458 1459 /* step2f,g: powerdown panel */ 1460 gen11_dsi_powerdown_panel(encoder); 1461 1462 /* step2h,i,j: deconfig trancoder */ 1463 gen11_dsi_deconfigure_trancoder(encoder); 1464 1465 /* step3: disable port */ 1466 gen11_dsi_disable_port(encoder); 1467 1468 gen11_dsi_config_util_pin(encoder, false); 1469 1470 /* step4: disable IO power */ 1471 gen11_dsi_disable_io_power(encoder); 1472 } 1473 1474 static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1475 struct intel_encoder *encoder, 1476 const struct intel_crtc_state *old_crtc_state, 1477 const struct drm_connector_state *old_conn_state) 1478 { 1479 intel_crtc_vblank_off(old_crtc_state); 1480 1481 intel_dsc_disable(old_crtc_state); 1482 1483 skl_scaler_disable(old_crtc_state); 1484 } 1485 1486 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1487 struct drm_display_mode *mode) 1488 { 1489 /* FIXME: DSC? */ 1490 return intel_dsi_mode_valid(connector, mode); 1491 } 1492 1493 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1494 struct intel_crtc_state *pipe_config) 1495 { 1496 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1497 struct drm_display_mode *adjusted_mode = 1498 &pipe_config->hw.adjusted_mode; 1499 1500 if (pipe_config->dsc.compressed_bpp) { 1501 int div = pipe_config->dsc.compressed_bpp; 1502 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1503 1504 adjusted_mode->crtc_htotal = 1505 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1506 adjusted_mode->crtc_hsync_start = 1507 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1508 adjusted_mode->crtc_hsync_end = 1509 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1510 } 1511 1512 if (intel_dsi->dual_link) { 1513 adjusted_mode->crtc_hdisplay *= 2; 1514 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1515 adjusted_mode->crtc_hdisplay -= 1516 intel_dsi->pixel_overlap; 1517 adjusted_mode->crtc_htotal *= 2; 1518 } 1519 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1520 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1521 1522 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1523 if (intel_dsi->dual_link) { 1524 adjusted_mode->crtc_hsync_start *= 2; 1525 adjusted_mode->crtc_hsync_end *= 2; 1526 } 1527 } 1528 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1529 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1530 } 1531 1532 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1533 { 1534 struct drm_device *dev = intel_dsi->base.base.dev; 1535 struct drm_i915_private *dev_priv = to_i915(dev); 1536 enum transcoder dsi_trans; 1537 u32 val; 1538 1539 if (intel_dsi->ports == BIT(PORT_B)) 1540 dsi_trans = TRANSCODER_DSI_1; 1541 else 1542 dsi_trans = TRANSCODER_DSI_0; 1543 1544 val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 1545 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1546 } 1547 1548 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1549 struct intel_crtc_state *pipe_config) 1550 { 1551 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1552 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1553 I915_MODE_FLAG_DSI_USE_TE0; 1554 else if (intel_dsi->ports == BIT(PORT_B)) 1555 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1556 else 1557 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1558 } 1559 1560 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1561 struct intel_crtc_state *pipe_config) 1562 { 1563 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1564 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1565 1566 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1567 1568 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1569 if (intel_dsi->dual_link) 1570 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1571 1572 gen11_dsi_get_timings(encoder, pipe_config); 1573 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1574 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1575 1576 /* Get the details on which TE should be enabled */ 1577 if (is_cmd_mode(intel_dsi)) 1578 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1579 1580 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1581 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1582 } 1583 1584 static void gen11_dsi_sync_state(struct intel_encoder *encoder, 1585 const struct intel_crtc_state *crtc_state) 1586 { 1587 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1588 struct intel_crtc *intel_crtc; 1589 enum pipe pipe; 1590 1591 if (!crtc_state) 1592 return; 1593 1594 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1595 pipe = intel_crtc->pipe; 1596 1597 /* wa verify 1409054076:icl,jsl,ehl */ 1598 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && 1599 !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A)) 1600 drm_dbg_kms(&dev_priv->drm, 1601 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n", 1602 encoder->base.base.id, 1603 encoder->base.name); 1604 } 1605 1606 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1607 struct intel_crtc_state *crtc_state) 1608 { 1609 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1610 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1611 int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10; 1612 bool use_dsc; 1613 int ret; 1614 1615 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1616 if (!use_dsc) 1617 return 0; 1618 1619 if (crtc_state->pipe_bpp < 8 * 3) 1620 return -EINVAL; 1621 1622 /* FIXME: split only when necessary */ 1623 if (crtc_state->dsc.slice_count > 1) 1624 crtc_state->dsc.dsc_split = true; 1625 1626 vdsc_cfg->convert_rgb = true; 1627 1628 /* FIXME: initialize from VBT */ 1629 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1630 1631 ret = intel_dsc_compute_params(crtc_state); 1632 if (ret) 1633 return ret; 1634 1635 /* DSI specific sanity checks on the common code */ 1636 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); 1637 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); 1638 drm_WARN_ON(&dev_priv->drm, 1639 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1640 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); 1641 drm_WARN_ON(&dev_priv->drm, 1642 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1643 1644 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1645 if (ret) 1646 return ret; 1647 1648 crtc_state->dsc.compression_enable = true; 1649 1650 return 0; 1651 } 1652 1653 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1654 struct intel_crtc_state *pipe_config, 1655 struct drm_connector_state *conn_state) 1656 { 1657 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1658 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 1659 base); 1660 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1661 struct drm_display_mode *adjusted_mode = 1662 &pipe_config->hw.adjusted_mode; 1663 int ret; 1664 1665 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1666 1667 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 1668 if (ret) 1669 return ret; 1670 1671 ret = intel_panel_fitting(pipe_config, conn_state); 1672 if (ret) 1673 return ret; 1674 1675 adjusted_mode->flags = 0; 1676 1677 /* Dual link goes to trancoder DSI'0' */ 1678 if (intel_dsi->ports == BIT(PORT_B)) 1679 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1680 else 1681 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1682 1683 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1684 pipe_config->pipe_bpp = 24; 1685 else 1686 pipe_config->pipe_bpp = 18; 1687 1688 pipe_config->clock_set = true; 1689 1690 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1691 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n"); 1692 1693 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1694 1695 /* 1696 * In case of TE GATE cmd mode, we 1697 * receive TE from the slave if 1698 * dual link is enabled 1699 */ 1700 if (is_cmd_mode(intel_dsi)) 1701 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1702 1703 return 0; 1704 } 1705 1706 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1707 struct intel_crtc_state *crtc_state) 1708 { 1709 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1710 1711 get_dsi_io_power_domains(i915, 1712 enc_to_intel_dsi(encoder)); 1713 } 1714 1715 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1716 enum pipe *pipe) 1717 { 1718 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1719 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1720 enum transcoder dsi_trans; 1721 intel_wakeref_t wakeref; 1722 enum port port; 1723 bool ret = false; 1724 u32 tmp; 1725 1726 wakeref = intel_display_power_get_if_enabled(dev_priv, 1727 encoder->power_domain); 1728 if (!wakeref) 1729 return false; 1730 1731 for_each_dsi_port(port, intel_dsi->ports) { 1732 dsi_trans = dsi_port_to_transcoder(port); 1733 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1734 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1735 case TRANS_DDI_EDP_INPUT_A_ON: 1736 *pipe = PIPE_A; 1737 break; 1738 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1739 *pipe = PIPE_B; 1740 break; 1741 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1742 *pipe = PIPE_C; 1743 break; 1744 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1745 *pipe = PIPE_D; 1746 break; 1747 default: 1748 drm_err(&dev_priv->drm, "Invalid PIPE input\n"); 1749 goto out; 1750 } 1751 1752 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1753 ret = tmp & PIPECONF_ENABLE; 1754 } 1755 out: 1756 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1757 return ret; 1758 } 1759 1760 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1761 struct intel_crtc_state *crtc_state) 1762 { 1763 if (crtc_state->dsc.compression_enable) { 1764 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1765 crtc_state->uapi.mode_changed = true; 1766 1767 return false; 1768 } 1769 1770 return true; 1771 } 1772 1773 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1774 { 1775 intel_encoder_destroy(encoder); 1776 } 1777 1778 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1779 .destroy = gen11_dsi_encoder_destroy, 1780 }; 1781 1782 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1783 .detect = intel_panel_detect, 1784 .late_register = intel_connector_register, 1785 .early_unregister = intel_connector_unregister, 1786 .destroy = intel_connector_destroy, 1787 .fill_modes = drm_helper_probe_single_connector_modes, 1788 .atomic_get_property = intel_digital_connector_atomic_get_property, 1789 .atomic_set_property = intel_digital_connector_atomic_set_property, 1790 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1791 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1792 }; 1793 1794 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1795 .get_modes = intel_dsi_get_modes, 1796 .mode_valid = gen11_dsi_mode_valid, 1797 .atomic_check = intel_digital_connector_atomic_check, 1798 }; 1799 1800 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1801 struct mipi_dsi_device *dsi) 1802 { 1803 return 0; 1804 } 1805 1806 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1807 struct mipi_dsi_device *dsi) 1808 { 1809 return 0; 1810 } 1811 1812 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1813 const struct mipi_dsi_msg *msg) 1814 { 1815 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1816 struct mipi_dsi_packet dsi_pkt; 1817 ssize_t ret; 1818 bool enable_lpdt = false; 1819 1820 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1821 if (ret < 0) 1822 return ret; 1823 1824 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1825 enable_lpdt = true; 1826 1827 /* only long packet contains payload */ 1828 if (mipi_dsi_packet_format_is_long(msg->type)) { 1829 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt); 1830 if (ret < 0) 1831 return ret; 1832 } 1833 1834 /* send packet header */ 1835 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt); 1836 if (ret < 0) 1837 return ret; 1838 1839 //TODO: add payload receive code if needed 1840 1841 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1842 1843 return ret; 1844 } 1845 1846 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1847 .attach = gen11_dsi_host_attach, 1848 .detach = gen11_dsi_host_detach, 1849 .transfer = gen11_dsi_host_transfer, 1850 }; 1851 1852 #define ICL_PREPARE_CNT_MAX 0x7 1853 #define ICL_CLK_ZERO_CNT_MAX 0xf 1854 #define ICL_TRAIL_CNT_MAX 0x7 1855 #define ICL_TCLK_PRE_CNT_MAX 0x3 1856 #define ICL_TCLK_POST_CNT_MAX 0x7 1857 #define ICL_HS_ZERO_CNT_MAX 0xf 1858 #define ICL_EXIT_ZERO_CNT_MAX 0x7 1859 1860 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1861 { 1862 struct drm_device *dev = intel_dsi->base.base.dev; 1863 struct drm_i915_private *dev_priv = to_i915(dev); 1864 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 1865 u32 tlpx_ns; 1866 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1867 u32 ths_prepare_ns, tclk_trail_ns; 1868 u32 hs_zero_cnt; 1869 u32 tclk_pre_cnt, tclk_post_cnt; 1870 1871 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1872 1873 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1874 ths_prepare_ns = max(mipi_config->ths_prepare, 1875 mipi_config->tclk_prepare); 1876 1877 /* 1878 * prepare cnt in escape clocks 1879 * this field represents a hexadecimal value with a precision 1880 * of 1.2 – i.e. the most significant bit is the integer 1881 * and the least significant 2 bits are fraction bits. 1882 * so, the field can represent a range of 0.25 to 1.75 1883 */ 1884 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1885 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1886 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", 1887 prepare_cnt); 1888 prepare_cnt = ICL_PREPARE_CNT_MAX; 1889 } 1890 1891 /* clk zero count in escape clocks */ 1892 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1893 ths_prepare_ns, tlpx_ns); 1894 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1895 drm_dbg_kms(&dev_priv->drm, 1896 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1897 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1898 } 1899 1900 /* trail cnt in escape clocks*/ 1901 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1902 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1903 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", 1904 trail_cnt); 1905 trail_cnt = ICL_TRAIL_CNT_MAX; 1906 } 1907 1908 /* tclk pre count in escape clocks */ 1909 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1910 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1911 drm_dbg_kms(&dev_priv->drm, 1912 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1913 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1914 } 1915 1916 /* tclk post count in escape clocks */ 1917 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); 1918 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { 1919 drm_dbg_kms(&dev_priv->drm, 1920 "tclk_post_cnt out of range (%d)\n", 1921 tclk_post_cnt); 1922 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; 1923 } 1924 1925 /* hs zero cnt in escape clocks */ 1926 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1927 ths_prepare_ns, tlpx_ns); 1928 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1929 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", 1930 hs_zero_cnt); 1931 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1932 } 1933 1934 /* hs exit zero cnt in escape clocks */ 1935 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1936 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1937 drm_dbg_kms(&dev_priv->drm, 1938 "exit_zero_cnt out of range (%d)\n", 1939 exit_zero_cnt); 1940 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1941 } 1942 1943 /* clock lane dphy timings */ 1944 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1945 CLK_PREPARE(prepare_cnt) | 1946 CLK_ZERO_OVERRIDE | 1947 CLK_ZERO(clk_zero_cnt) | 1948 CLK_PRE_OVERRIDE | 1949 CLK_PRE(tclk_pre_cnt) | 1950 CLK_POST_OVERRIDE | 1951 CLK_POST(tclk_post_cnt) | 1952 CLK_TRAIL_OVERRIDE | 1953 CLK_TRAIL(trail_cnt)); 1954 1955 /* data lanes dphy timings */ 1956 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1957 HS_PREPARE(prepare_cnt) | 1958 HS_ZERO_OVERRIDE | 1959 HS_ZERO(hs_zero_cnt) | 1960 HS_TRAIL_OVERRIDE | 1961 HS_TRAIL(trail_cnt) | 1962 HS_EXIT_OVERRIDE | 1963 HS_EXIT(exit_zero_cnt)); 1964 1965 intel_dsi_log_params(intel_dsi); 1966 } 1967 1968 static void icl_dsi_add_properties(struct intel_connector *connector) 1969 { 1970 u32 allowed_scalers; 1971 1972 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | 1973 BIT(DRM_MODE_SCALE_FULLSCREEN) | 1974 BIT(DRM_MODE_SCALE_CENTER); 1975 1976 drm_connector_attach_scaling_mode_property(&connector->base, 1977 allowed_scalers); 1978 1979 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1980 1981 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1982 intel_dsi_get_panel_orientation(connector), 1983 connector->panel.fixed_mode->hdisplay, 1984 connector->panel.fixed_mode->vdisplay); 1985 } 1986 1987 void icl_dsi_init(struct drm_i915_private *dev_priv) 1988 { 1989 struct drm_device *dev = &dev_priv->drm; 1990 struct intel_dsi *intel_dsi; 1991 struct intel_encoder *encoder; 1992 struct intel_connector *intel_connector; 1993 struct drm_connector *connector; 1994 struct drm_display_mode *fixed_mode; 1995 enum port port; 1996 1997 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1998 return; 1999 2000 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 2001 if (!intel_dsi) 2002 return; 2003 2004 intel_connector = intel_connector_alloc(); 2005 if (!intel_connector) { 2006 kfree(intel_dsi); 2007 return; 2008 } 2009 2010 encoder = &intel_dsi->base; 2011 intel_dsi->attached_connector = intel_connector; 2012 connector = &intel_connector->base; 2013 2014 /* register DSI encoder with DRM subsystem */ 2015 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs, 2016 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 2017 2018 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 2019 encoder->pre_enable = gen11_dsi_pre_enable; 2020 encoder->enable = gen11_dsi_enable; 2021 encoder->disable = gen11_dsi_disable; 2022 encoder->post_disable = gen11_dsi_post_disable; 2023 encoder->port = port; 2024 encoder->get_config = gen11_dsi_get_config; 2025 encoder->sync_state = gen11_dsi_sync_state; 2026 encoder->update_pipe = intel_backlight_update; 2027 encoder->compute_config = gen11_dsi_compute_config; 2028 encoder->get_hw_state = gen11_dsi_get_hw_state; 2029 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 2030 encoder->type = INTEL_OUTPUT_DSI; 2031 encoder->cloneable = 0; 2032 encoder->pipe_mask = ~0; 2033 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 2034 encoder->get_power_domains = gen11_dsi_get_power_domains; 2035 encoder->disable_clock = gen11_dsi_gate_clocks; 2036 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 2037 2038 /* register DSI connector with DRM subsystem */ 2039 drm_connector_init(dev, connector, &gen11_dsi_connector_funcs, 2040 DRM_MODE_CONNECTOR_DSI); 2041 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 2042 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 2043 connector->interlace_allowed = false; 2044 connector->doublescan_allowed = false; 2045 intel_connector->get_hw_state = intel_connector_get_hw_state; 2046 2047 /* attach connector to encoder */ 2048 intel_connector_attach_encoder(intel_connector, encoder); 2049 2050 mutex_lock(&dev->mode_config.mutex); 2051 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 2052 mutex_unlock(&dev->mode_config.mutex); 2053 2054 if (!fixed_mode) { 2055 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); 2056 goto err; 2057 } 2058 2059 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 2060 intel_backlight_setup(intel_connector, INVALID_PIPE); 2061 2062 if (dev_priv->vbt.dsi.config->dual_link) 2063 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 2064 else 2065 intel_dsi->ports = BIT(port); 2066 2067 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; 2068 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; 2069 2070 for_each_dsi_port(port, intel_dsi->ports) { 2071 struct intel_dsi_host *host; 2072 2073 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2074 if (!host) 2075 goto err; 2076 2077 intel_dsi->dsi_hosts[port] = host; 2078 } 2079 2080 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2081 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 2082 goto err; 2083 } 2084 2085 icl_dphy_param_init(intel_dsi); 2086 2087 icl_dsi_add_properties(intel_connector); 2088 return; 2089 2090 err: 2091 drm_connector_cleanup(connector); 2092 drm_encoder_cleanup(&encoder->base); 2093 kfree(intel_dsi); 2094 kfree(intel_connector); 2095 } 2096