1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/display/drm_dsc_helper.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_mipi_dsi.h> 31 32 #include "icl_dsi.h" 33 #include "icl_dsi_regs.h" 34 #include "intel_atomic.h" 35 #include "intel_backlight.h" 36 #include "intel_backlight_regs.h" 37 #include "intel_combo_phy.h" 38 #include "intel_combo_phy_regs.h" 39 #include "intel_connector.h" 40 #include "intel_crtc.h" 41 #include "intel_ddi.h" 42 #include "intel_de.h" 43 #include "intel_dsi.h" 44 #include "intel_dsi_vbt.h" 45 #include "intel_panel.h" 46 #include "intel_vdsc.h" 47 #include "skl_scaler.h" 48 #include "skl_universal_plane.h" 49 50 static int header_credits_available(struct drm_i915_private *dev_priv, 51 enum transcoder dsi_trans) 52 { 53 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 54 >> FREE_HEADER_CREDIT_SHIFT; 55 } 56 57 static int payload_credits_available(struct drm_i915_private *dev_priv, 58 enum transcoder dsi_trans) 59 { 60 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 61 >> FREE_PLOAD_CREDIT_SHIFT; 62 } 63 64 static bool wait_for_header_credits(struct drm_i915_private *dev_priv, 65 enum transcoder dsi_trans, int hdr_credit) 66 { 67 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= 68 hdr_credit, 100)) { 69 drm_err(&dev_priv->drm, "DSI header credits not released\n"); 70 return false; 71 } 72 73 return true; 74 } 75 76 static bool wait_for_payload_credits(struct drm_i915_private *dev_priv, 77 enum transcoder dsi_trans, int payld_credit) 78 { 79 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= 80 payld_credit, 100)) { 81 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); 82 return false; 83 } 84 85 return true; 86 } 87 88 static enum transcoder dsi_port_to_transcoder(enum port port) 89 { 90 if (port == PORT_A) 91 return TRANSCODER_DSI_0; 92 else 93 return TRANSCODER_DSI_1; 94 } 95 96 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 97 { 98 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 99 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 100 struct mipi_dsi_device *dsi; 101 enum port port; 102 enum transcoder dsi_trans; 103 int ret; 104 105 /* wait for header/payload credits to be released */ 106 for_each_dsi_port(port, intel_dsi->ports) { 107 dsi_trans = dsi_port_to_transcoder(port); 108 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 109 wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT); 110 } 111 112 /* send nop DCS command */ 113 for_each_dsi_port(port, intel_dsi->ports) { 114 dsi = intel_dsi->dsi_hosts[port]->device; 115 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 116 dsi->channel = 0; 117 ret = mipi_dsi_dcs_nop(dsi); 118 if (ret < 0) 119 drm_err(&dev_priv->drm, 120 "error sending DCS NOP command\n"); 121 } 122 123 /* wait for header credits to be released */ 124 for_each_dsi_port(port, intel_dsi->ports) { 125 dsi_trans = dsi_port_to_transcoder(port); 126 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 127 } 128 129 /* wait for LP TX in progress bit to be cleared */ 130 for_each_dsi_port(port, intel_dsi->ports) { 131 dsi_trans = dsi_port_to_transcoder(port); 132 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 133 LPTX_IN_PROGRESS), 20)) 134 drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); 135 } 136 } 137 138 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 139 const struct mipi_dsi_packet *packet) 140 { 141 struct intel_dsi *intel_dsi = host->intel_dsi; 142 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 143 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 144 const u8 *data = packet->payload; 145 u32 len = packet->payload_length; 146 int i, j; 147 148 /* payload queue can accept *256 bytes*, check limit */ 149 if (len > MAX_PLOAD_CREDIT * 4) { 150 drm_err(&i915->drm, "payload size exceeds max queue limit\n"); 151 return -EINVAL; 152 } 153 154 for (i = 0; i < len; i += 4) { 155 u32 tmp = 0; 156 157 if (!wait_for_payload_credits(i915, dsi_trans, 1)) 158 return -EBUSY; 159 160 for (j = 0; j < min_t(u32, len - i, 4); j++) 161 tmp |= *data++ << 8 * j; 162 163 intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp); 164 } 165 166 return 0; 167 } 168 169 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 170 const struct mipi_dsi_packet *packet, 171 bool enable_lpdt) 172 { 173 struct intel_dsi *intel_dsi = host->intel_dsi; 174 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 175 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 176 u32 tmp; 177 178 if (!wait_for_header_credits(dev_priv, dsi_trans, 1)) 179 return -EBUSY; 180 181 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); 182 183 if (packet->payload) 184 tmp |= PAYLOAD_PRESENT; 185 else 186 tmp &= ~PAYLOAD_PRESENT; 187 188 tmp &= ~VBLANK_FENCE; 189 190 if (enable_lpdt) 191 tmp |= LP_DATA_TRANSFER; 192 else 193 tmp &= ~LP_DATA_TRANSFER; 194 195 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 196 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); 197 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); 198 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); 199 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); 200 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); 201 202 return 0; 203 } 204 205 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 206 { 207 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 208 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 209 u32 tmp, mode_flags; 210 enum port port; 211 212 mode_flags = crtc_state->mode_flags; 213 214 /* 215 * case 1 also covers dual link 216 * In case of dual link, frame update should be set on 217 * DSI_0 218 */ 219 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 220 port = PORT_A; 221 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 222 port = PORT_B; 223 else 224 return; 225 226 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 227 tmp |= DSI_FRAME_UPDATE_REQUEST; 228 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 229 } 230 231 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 232 { 233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 234 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 235 enum phy phy; 236 u32 tmp; 237 int lane; 238 239 for_each_dsi_phy(phy, intel_dsi->phys) { 240 /* 241 * Program voltage swing and pre-emphasis level values as per 242 * table in BSPEC under DDI buffer programing 243 */ 244 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 245 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 246 tmp |= SCALING_MODE_SEL(0x2); 247 tmp |= TAP2_DISABLE | TAP3_DISABLE; 248 tmp |= RTERM_SELECT(0x6); 249 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 250 251 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 252 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 253 tmp |= SCALING_MODE_SEL(0x2); 254 tmp |= TAP2_DISABLE | TAP3_DISABLE; 255 tmp |= RTERM_SELECT(0x6); 256 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 257 258 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 259 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 260 RCOMP_SCALAR_MASK); 261 tmp |= SWING_SEL_UPPER(0x2); 262 tmp |= SWING_SEL_LOWER(0x2); 263 tmp |= RCOMP_SCALAR(0x98); 264 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 265 266 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 267 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 268 RCOMP_SCALAR_MASK); 269 tmp |= SWING_SEL_UPPER(0x2); 270 tmp |= SWING_SEL_LOWER(0x2); 271 tmp |= RCOMP_SCALAR(0x98); 272 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 273 274 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 275 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 276 CURSOR_COEFF_MASK); 277 tmp |= POST_CURSOR_1(0x0); 278 tmp |= POST_CURSOR_2(0x0); 279 tmp |= CURSOR_COEFF(0x3f); 280 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 281 282 for (lane = 0; lane <= 3; lane++) { 283 /* Bspec: must not use GRP register for write */ 284 tmp = intel_de_read(dev_priv, 285 ICL_PORT_TX_DW4_LN(lane, phy)); 286 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 287 CURSOR_COEFF_MASK); 288 tmp |= POST_CURSOR_1(0x0); 289 tmp |= POST_CURSOR_2(0x0); 290 tmp |= CURSOR_COEFF(0x3f); 291 intel_de_write(dev_priv, 292 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 293 } 294 } 295 } 296 297 static void configure_dual_link_mode(struct intel_encoder *encoder, 298 const struct intel_crtc_state *pipe_config) 299 { 300 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 301 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 302 u32 dss_ctl1; 303 304 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); 305 dss_ctl1 |= SPLITTER_ENABLE; 306 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 307 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 308 309 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 310 const struct drm_display_mode *adjusted_mode = 311 &pipe_config->hw.adjusted_mode; 312 u32 dss_ctl2; 313 u16 hactive = adjusted_mode->crtc_hdisplay; 314 u16 dl_buffer_depth; 315 316 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 317 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 318 319 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 320 drm_err(&dev_priv->drm, 321 "DL buffer depth exceed max value\n"); 322 323 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 324 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 325 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); 326 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; 327 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 328 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); 329 } else { 330 /* Interleave */ 331 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 332 } 333 334 intel_de_write(dev_priv, DSS_CTL1, dss_ctl1); 335 } 336 337 /* aka DSI 8X clock */ 338 static int afe_clk(struct intel_encoder *encoder, 339 const struct intel_crtc_state *crtc_state) 340 { 341 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 342 int bpp; 343 344 if (crtc_state->dsc.compression_enable) 345 bpp = crtc_state->dsc.compressed_bpp; 346 else 347 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 348 349 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 350 } 351 352 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 353 const struct intel_crtc_state *crtc_state) 354 { 355 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 356 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 357 enum port port; 358 int afe_clk_khz; 359 int theo_word_clk, act_word_clk; 360 u32 esc_clk_div_m, esc_clk_div_m_phy; 361 362 afe_clk_khz = afe_clk(encoder, crtc_state); 363 364 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 365 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 366 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 367 esc_clk_div_m = act_word_clk * 8; 368 esc_clk_div_m_phy = (act_word_clk - 1) / 2; 369 } else { 370 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 371 } 372 373 for_each_dsi_port(port, intel_dsi->ports) { 374 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), 375 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 376 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); 377 } 378 379 for_each_dsi_port(port, intel_dsi->ports) { 380 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port), 381 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 382 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); 383 } 384 385 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 386 for_each_dsi_port(port, intel_dsi->ports) { 387 intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8), 388 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); 389 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8)); 390 } 391 } 392 } 393 394 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, 395 struct intel_dsi *intel_dsi) 396 { 397 enum port port; 398 399 for_each_dsi_port(port, intel_dsi->ports) { 400 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); 401 intel_dsi->io_wakeref[port] = 402 intel_display_power_get(dev_priv, 403 port == PORT_A ? 404 POWER_DOMAIN_PORT_DDI_IO_A : 405 POWER_DOMAIN_PORT_DDI_IO_B); 406 } 407 } 408 409 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 410 { 411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 412 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 413 enum port port; 414 u32 tmp; 415 416 for_each_dsi_port(port, intel_dsi->ports) { 417 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 418 tmp |= COMBO_PHY_MODE_DSI; 419 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 420 } 421 422 get_dsi_io_power_domains(dev_priv, intel_dsi); 423 } 424 425 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 426 { 427 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 428 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 429 enum phy phy; 430 431 for_each_dsi_phy(phy, intel_dsi->phys) 432 intel_combo_phy_power_up_lanes(dev_priv, phy, true, 433 intel_dsi->lane_count, false); 434 } 435 436 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 437 { 438 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 439 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 440 enum phy phy; 441 u32 tmp; 442 int lane; 443 444 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 445 for_each_dsi_phy(phy, intel_dsi->phys) { 446 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 447 tmp &= ~LOADGEN_SELECT; 448 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 449 for (lane = 0; lane <= 3; lane++) { 450 tmp = intel_de_read(dev_priv, 451 ICL_PORT_TX_DW4_LN(lane, phy)); 452 tmp &= ~LOADGEN_SELECT; 453 if (lane != 2) 454 tmp |= LOADGEN_SELECT; 455 intel_de_write(dev_priv, 456 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 457 } 458 } 459 460 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 461 for_each_dsi_phy(phy, intel_dsi->phys) { 462 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 463 tmp &= ~FRC_LATENCY_OPTIM_MASK; 464 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 465 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 466 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 467 tmp &= ~FRC_LATENCY_OPTIM_MASK; 468 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 469 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 470 471 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 472 if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) { 473 tmp = intel_de_read(dev_priv, 474 ICL_PORT_PCS_DW1_AUX(phy)); 475 tmp &= ~LATENCY_OPTIM_MASK; 476 tmp |= LATENCY_OPTIM_VAL(0); 477 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), 478 tmp); 479 480 tmp = intel_de_read(dev_priv, 481 ICL_PORT_PCS_DW1_LN(0, phy)); 482 tmp &= ~LATENCY_OPTIM_MASK; 483 tmp |= LATENCY_OPTIM_VAL(0x1); 484 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), 485 tmp); 486 } 487 } 488 489 } 490 491 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 492 { 493 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 494 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 495 u32 tmp; 496 enum phy phy; 497 498 /* clear common keeper enable bit */ 499 for_each_dsi_phy(phy, intel_dsi->phys) { 500 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 501 tmp &= ~COMMON_KEEPER_EN; 502 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp); 503 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy)); 504 tmp &= ~COMMON_KEEPER_EN; 505 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp); 506 } 507 508 /* 509 * Set SUS Clock Config bitfield to 11b 510 * Note: loadgen select program is done 511 * as part of lane phy sequence configuration 512 */ 513 for_each_dsi_phy(phy, intel_dsi->phys) { 514 tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 515 tmp |= SUS_CLOCK_CONFIG; 516 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp); 517 } 518 519 /* Clear training enable to change swing values */ 520 for_each_dsi_phy(phy, intel_dsi->phys) { 521 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 522 tmp &= ~TX_TRAINING_EN; 523 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 524 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 525 tmp &= ~TX_TRAINING_EN; 526 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 527 } 528 529 /* Program swing and de-emphasis */ 530 dsi_program_swing_and_deemphasis(encoder); 531 532 /* Set training enable to trigger update */ 533 for_each_dsi_phy(phy, intel_dsi->phys) { 534 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 535 tmp |= TX_TRAINING_EN; 536 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 537 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 538 tmp |= TX_TRAINING_EN; 539 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 540 } 541 } 542 543 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 544 { 545 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 546 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 547 u32 tmp; 548 enum port port; 549 550 for_each_dsi_port(port, intel_dsi->ports) { 551 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 552 tmp |= DDI_BUF_CTL_ENABLE; 553 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 554 555 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 556 DDI_BUF_IS_IDLE), 557 500)) 558 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", 559 port_name(port)); 560 } 561 } 562 563 static void 564 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 565 const struct intel_crtc_state *crtc_state) 566 { 567 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 568 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 569 u32 tmp; 570 enum port port; 571 enum phy phy; 572 573 /* Program T-INIT master registers */ 574 for_each_dsi_port(port, intel_dsi->ports) { 575 tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port)); 576 tmp &= ~DSI_T_INIT_MASTER_MASK; 577 tmp |= intel_dsi->init_count; 578 intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp); 579 } 580 581 /* Program DPHY clock lanes timings */ 582 for_each_dsi_port(port, intel_dsi->ports) { 583 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port), 584 intel_dsi->dphy_reg); 585 586 /* shadow register inside display core */ 587 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port), 588 intel_dsi->dphy_reg); 589 } 590 591 /* Program DPHY data lanes timings */ 592 for_each_dsi_port(port, intel_dsi->ports) { 593 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port), 594 intel_dsi->dphy_data_lane_reg); 595 596 /* shadow register inside display core */ 597 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port), 598 intel_dsi->dphy_data_lane_reg); 599 } 600 601 /* 602 * If DSI link operating at or below an 800 MHz, 603 * TA_SURE should be override and programmed to 604 * a value '0' inside TA_PARAM_REGISTERS otherwise 605 * leave all fields at HW default values. 606 */ 607 if (DISPLAY_VER(dev_priv) == 11) { 608 if (afe_clk(encoder, crtc_state) <= 800000) { 609 for_each_dsi_port(port, intel_dsi->ports) { 610 tmp = intel_de_read(dev_priv, 611 DPHY_TA_TIMING_PARAM(port)); 612 tmp &= ~TA_SURE_MASK; 613 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 614 intel_de_write(dev_priv, 615 DPHY_TA_TIMING_PARAM(port), 616 tmp); 617 618 /* shadow register inside display core */ 619 tmp = intel_de_read(dev_priv, 620 DSI_TA_TIMING_PARAM(port)); 621 tmp &= ~TA_SURE_MASK; 622 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 623 intel_de_write(dev_priv, 624 DSI_TA_TIMING_PARAM(port), tmp); 625 } 626 } 627 } 628 629 if (IS_JSL_EHL(dev_priv)) { 630 for_each_dsi_phy(phy, intel_dsi->phys) { 631 tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy)); 632 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; 633 intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp); 634 } 635 } 636 } 637 638 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 639 { 640 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 641 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 642 u32 tmp; 643 enum phy phy; 644 645 mutex_lock(&dev_priv->display.dpll.lock); 646 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 647 for_each_dsi_phy(phy, intel_dsi->phys) 648 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 649 650 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 651 mutex_unlock(&dev_priv->display.dpll.lock); 652 } 653 654 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 655 { 656 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 657 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 658 u32 tmp; 659 enum phy phy; 660 661 mutex_lock(&dev_priv->display.dpll.lock); 662 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 663 for_each_dsi_phy(phy, intel_dsi->phys) 664 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 665 666 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 667 mutex_unlock(&dev_priv->display.dpll.lock); 668 } 669 670 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 671 { 672 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 673 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 674 bool clock_enabled = false; 675 enum phy phy; 676 u32 tmp; 677 678 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 679 680 for_each_dsi_phy(phy, intel_dsi->phys) { 681 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 682 clock_enabled = true; 683 } 684 685 return clock_enabled; 686 } 687 688 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 689 const struct intel_crtc_state *crtc_state) 690 { 691 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 692 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 693 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 694 enum phy phy; 695 u32 val; 696 697 mutex_lock(&dev_priv->display.dpll.lock); 698 699 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 700 for_each_dsi_phy(phy, intel_dsi->phys) { 701 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 702 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 703 } 704 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 705 706 for_each_dsi_phy(phy, intel_dsi->phys) { 707 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 708 } 709 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 710 711 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 712 713 mutex_unlock(&dev_priv->display.dpll.lock); 714 } 715 716 static void 717 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 718 const struct intel_crtc_state *pipe_config) 719 { 720 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 721 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 722 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 723 enum pipe pipe = crtc->pipe; 724 u32 tmp; 725 enum port port; 726 enum transcoder dsi_trans; 727 728 for_each_dsi_port(port, intel_dsi->ports) { 729 dsi_trans = dsi_port_to_transcoder(port); 730 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 731 732 if (intel_dsi->eotp_pkt) 733 tmp &= ~EOTP_DISABLED; 734 else 735 tmp |= EOTP_DISABLED; 736 737 /* enable link calibration if freq > 1.5Gbps */ 738 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 739 tmp &= ~LINK_CALIBRATION_MASK; 740 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 741 } 742 743 /* configure continuous clock */ 744 tmp &= ~CONTINUOUS_CLK_MASK; 745 if (intel_dsi->clock_stop) 746 tmp |= CLK_ENTER_LP_AFTER_DATA; 747 else 748 tmp |= CLK_HS_CONTINUOUS; 749 750 /* configure buffer threshold limit to minimum */ 751 tmp &= ~PIX_BUF_THRESHOLD_MASK; 752 tmp |= PIX_BUF_THRESHOLD_1_4; 753 754 /* set virtual channel to '0' */ 755 tmp &= ~PIX_VIRT_CHAN_MASK; 756 tmp |= PIX_VIRT_CHAN(0); 757 758 /* program BGR transmission */ 759 if (intel_dsi->bgr_enabled) 760 tmp |= BGR_TRANSMISSION; 761 762 /* select pixel format */ 763 tmp &= ~PIX_FMT_MASK; 764 if (pipe_config->dsc.compression_enable) { 765 tmp |= PIX_FMT_COMPRESSED; 766 } else { 767 switch (intel_dsi->pixel_format) { 768 default: 769 MISSING_CASE(intel_dsi->pixel_format); 770 fallthrough; 771 case MIPI_DSI_FMT_RGB565: 772 tmp |= PIX_FMT_RGB565; 773 break; 774 case MIPI_DSI_FMT_RGB666_PACKED: 775 tmp |= PIX_FMT_RGB666_PACKED; 776 break; 777 case MIPI_DSI_FMT_RGB666: 778 tmp |= PIX_FMT_RGB666_LOOSE; 779 break; 780 case MIPI_DSI_FMT_RGB888: 781 tmp |= PIX_FMT_RGB888; 782 break; 783 } 784 } 785 786 if (DISPLAY_VER(dev_priv) >= 12) { 787 if (is_vid_mode(intel_dsi)) 788 tmp |= BLANKING_PACKET_ENABLE; 789 } 790 791 /* program DSI operation mode */ 792 if (is_vid_mode(intel_dsi)) { 793 tmp &= ~OP_MODE_MASK; 794 switch (intel_dsi->video_mode) { 795 default: 796 MISSING_CASE(intel_dsi->video_mode); 797 fallthrough; 798 case NON_BURST_SYNC_EVENTS: 799 tmp |= VIDEO_MODE_SYNC_EVENT; 800 break; 801 case NON_BURST_SYNC_PULSE: 802 tmp |= VIDEO_MODE_SYNC_PULSE; 803 break; 804 } 805 } else { 806 /* 807 * FIXME: Retrieve this info from VBT. 808 * As per the spec when dsi transcoder is operating 809 * in TE GATE mode, TE comes from GPIO 810 * which is UTIL PIN for DSI 0. 811 * Also this GPIO would not be used for other 812 * purposes is an assumption. 813 */ 814 tmp &= ~OP_MODE_MASK; 815 tmp |= CMD_MODE_TE_GATE; 816 tmp |= TE_SOURCE_GPIO; 817 } 818 819 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 820 } 821 822 /* enable port sync mode if dual link */ 823 if (intel_dsi->dual_link) { 824 for_each_dsi_port(port, intel_dsi->ports) { 825 dsi_trans = dsi_port_to_transcoder(port); 826 tmp = intel_de_read(dev_priv, 827 TRANS_DDI_FUNC_CTL2(dsi_trans)); 828 tmp |= PORT_SYNC_MODE_ENABLE; 829 intel_de_write(dev_priv, 830 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 831 } 832 833 /* configure stream splitting */ 834 configure_dual_link_mode(encoder, pipe_config); 835 } 836 837 for_each_dsi_port(port, intel_dsi->ports) { 838 dsi_trans = dsi_port_to_transcoder(port); 839 840 /* select data lane width */ 841 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 842 tmp &= ~DDI_PORT_WIDTH_MASK; 843 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); 844 845 /* select input pipe */ 846 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 847 switch (pipe) { 848 default: 849 MISSING_CASE(pipe); 850 fallthrough; 851 case PIPE_A: 852 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 853 break; 854 case PIPE_B: 855 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 856 break; 857 case PIPE_C: 858 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 859 break; 860 case PIPE_D: 861 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 862 break; 863 } 864 865 /* enable DDI buffer */ 866 tmp |= TRANS_DDI_FUNC_ENABLE; 867 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 868 } 869 870 /* wait for link ready */ 871 for_each_dsi_port(port, intel_dsi->ports) { 872 dsi_trans = dsi_port_to_transcoder(port); 873 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) & 874 LINK_READY), 2500)) 875 drm_err(&dev_priv->drm, "DSI link not ready\n"); 876 } 877 } 878 879 static void 880 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 881 const struct intel_crtc_state *crtc_state) 882 { 883 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 884 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 885 const struct drm_display_mode *adjusted_mode = 886 &crtc_state->hw.adjusted_mode; 887 enum port port; 888 enum transcoder dsi_trans; 889 /* horizontal timings */ 890 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 891 u16 hback_porch; 892 /* vertical timings */ 893 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 894 int mul = 1, div = 1; 895 896 /* 897 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 898 * for slower link speed if DSC is enabled. 899 * 900 * The compression frequency ratio is the ratio between compressed and 901 * non-compressed link speeds, and simplifies down to the ratio between 902 * compressed and non-compressed bpp. 903 */ 904 if (crtc_state->dsc.compression_enable) { 905 mul = crtc_state->dsc.compressed_bpp; 906 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 907 } 908 909 hactive = adjusted_mode->crtc_hdisplay; 910 911 if (is_vid_mode(intel_dsi)) 912 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 913 else 914 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 915 916 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 917 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 918 hsync_size = hsync_end - hsync_start; 919 hback_porch = (adjusted_mode->crtc_htotal - 920 adjusted_mode->crtc_hsync_end); 921 vactive = adjusted_mode->crtc_vdisplay; 922 923 if (is_vid_mode(intel_dsi)) { 924 vtotal = adjusted_mode->crtc_vtotal; 925 } else { 926 int bpp, line_time_us, byte_clk_period_ns; 927 928 if (crtc_state->dsc.compression_enable) 929 bpp = crtc_state->dsc.compressed_bpp; 930 else 931 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 932 933 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 934 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 935 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 936 } 937 vsync_start = adjusted_mode->crtc_vsync_start; 938 vsync_end = adjusted_mode->crtc_vsync_end; 939 vsync_shift = hsync_start - htotal / 2; 940 941 if (intel_dsi->dual_link) { 942 hactive /= 2; 943 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 944 hactive += intel_dsi->pixel_overlap; 945 htotal /= 2; 946 } 947 948 /* minimum hactive as per bspec: 256 pixels */ 949 if (adjusted_mode->crtc_hdisplay < 256) 950 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); 951 952 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 953 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 954 drm_err(&dev_priv->drm, 955 "hactive pixels are not multiple of 4\n"); 956 957 /* program TRANS_HTOTAL register */ 958 for_each_dsi_port(port, intel_dsi->ports) { 959 dsi_trans = dsi_port_to_transcoder(port); 960 intel_de_write(dev_priv, HTOTAL(dsi_trans), 961 (hactive - 1) | ((htotal - 1) << 16)); 962 } 963 964 /* TRANS_HSYNC register to be programmed only for video mode */ 965 if (is_vid_mode(intel_dsi)) { 966 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { 967 /* BSPEC: hsync size should be atleast 16 pixels */ 968 if (hsync_size < 16) 969 drm_err(&dev_priv->drm, 970 "hsync size < 16 pixels\n"); 971 } 972 973 if (hback_porch < 16) 974 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); 975 976 if (intel_dsi->dual_link) { 977 hsync_start /= 2; 978 hsync_end /= 2; 979 } 980 981 for_each_dsi_port(port, intel_dsi->ports) { 982 dsi_trans = dsi_port_to_transcoder(port); 983 intel_de_write(dev_priv, HSYNC(dsi_trans), 984 (hsync_start - 1) | ((hsync_end - 1) << 16)); 985 } 986 } 987 988 /* program TRANS_VTOTAL register */ 989 for_each_dsi_port(port, intel_dsi->ports) { 990 dsi_trans = dsi_port_to_transcoder(port); 991 /* 992 * FIXME: Programing this by assuming progressive mode, since 993 * non-interlaced info from VBT is not saved inside 994 * struct drm_display_mode. 995 * For interlace mode: program required pixel minus 2 996 */ 997 intel_de_write(dev_priv, VTOTAL(dsi_trans), 998 (vactive - 1) | ((vtotal - 1) << 16)); 999 } 1000 1001 if (vsync_end < vsync_start || vsync_end > vtotal) 1002 drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); 1003 1004 if (vsync_start < vactive) 1005 drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); 1006 1007 /* program TRANS_VSYNC register for video mode only */ 1008 if (is_vid_mode(intel_dsi)) { 1009 for_each_dsi_port(port, intel_dsi->ports) { 1010 dsi_trans = dsi_port_to_transcoder(port); 1011 intel_de_write(dev_priv, VSYNC(dsi_trans), 1012 (vsync_start - 1) | ((vsync_end - 1) << 16)); 1013 } 1014 } 1015 1016 /* 1017 * FIXME: It has to be programmed only for video modes and interlaced 1018 * modes. Put the check condition here once interlaced 1019 * info available as described above. 1020 * program TRANS_VSYNCSHIFT register 1021 */ 1022 if (is_vid_mode(intel_dsi)) { 1023 for_each_dsi_port(port, intel_dsi->ports) { 1024 dsi_trans = dsi_port_to_transcoder(port); 1025 intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans), 1026 vsync_shift); 1027 } 1028 } 1029 1030 /* program TRANS_VBLANK register, should be same as vtotal programmed */ 1031 if (DISPLAY_VER(dev_priv) >= 12) { 1032 for_each_dsi_port(port, intel_dsi->ports) { 1033 dsi_trans = dsi_port_to_transcoder(port); 1034 intel_de_write(dev_priv, VBLANK(dsi_trans), 1035 (vactive - 1) | ((vtotal - 1) << 16)); 1036 } 1037 } 1038 } 1039 1040 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1041 { 1042 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1043 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1044 enum port port; 1045 enum transcoder dsi_trans; 1046 u32 tmp; 1047 1048 for_each_dsi_port(port, intel_dsi->ports) { 1049 dsi_trans = dsi_port_to_transcoder(port); 1050 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1051 tmp |= PIPECONF_ENABLE; 1052 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1053 1054 /* wait for transcoder to be enabled */ 1055 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), 1056 PIPECONF_STATE_ENABLE, 10)) 1057 drm_err(&dev_priv->drm, 1058 "DSI transcoder not enabled\n"); 1059 } 1060 } 1061 1062 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1063 const struct intel_crtc_state *crtc_state) 1064 { 1065 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1066 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1067 enum port port; 1068 enum transcoder dsi_trans; 1069 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1070 1071 /* 1072 * escape clock count calculation: 1073 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1074 * UI (nsec) = (10^6)/Bitrate 1075 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1076 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1077 */ 1078 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1079 mul = 8 * 1000000; 1080 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1081 divisor); 1082 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1083 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1084 1085 for_each_dsi_port(port, intel_dsi->ports) { 1086 dsi_trans = dsi_port_to_transcoder(port); 1087 1088 /* program hst_tx_timeout */ 1089 tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans)); 1090 tmp &= ~HSTX_TIMEOUT_VALUE_MASK; 1091 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout); 1092 intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp); 1093 1094 /* FIXME: DSI_CALIB_TO */ 1095 1096 /* program lp_rx_host timeout */ 1097 tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans)); 1098 tmp &= ~LPRX_TIMEOUT_VALUE_MASK; 1099 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout); 1100 intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp); 1101 1102 /* FIXME: DSI_PWAIT_TO */ 1103 1104 /* program turn around timeout */ 1105 tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans)); 1106 tmp &= ~TA_TIMEOUT_VALUE_MASK; 1107 tmp |= TA_TIMEOUT_VALUE(ta_timeout); 1108 intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp); 1109 } 1110 } 1111 1112 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1113 bool enable) 1114 { 1115 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1116 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1117 u32 tmp; 1118 1119 /* 1120 * used as TE i/p for DSI0, 1121 * for dual link/DSI1 TE is from slave DSI1 1122 * through GPIO. 1123 */ 1124 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1125 return; 1126 1127 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL); 1128 1129 if (enable) { 1130 tmp |= UTIL_PIN_DIRECTION_INPUT; 1131 tmp |= UTIL_PIN_ENABLE; 1132 } else { 1133 tmp &= ~UTIL_PIN_ENABLE; 1134 } 1135 intel_de_write(dev_priv, UTIL_PIN_CTL, tmp); 1136 } 1137 1138 static void 1139 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1140 const struct intel_crtc_state *crtc_state) 1141 { 1142 /* step 4a: power up all lanes of the DDI used by DSI */ 1143 gen11_dsi_power_up_lanes(encoder); 1144 1145 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1146 gen11_dsi_config_phy_lanes_sequence(encoder); 1147 1148 /* step 4c: configure voltage swing and skew */ 1149 gen11_dsi_voltage_swing_program_seq(encoder); 1150 1151 /* enable DDI buffer */ 1152 gen11_dsi_enable_ddi_buffer(encoder); 1153 1154 /* setup D-PHY timings */ 1155 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1156 1157 /* Since transcoder is configured to take events from GPIO */ 1158 gen11_dsi_config_util_pin(encoder, true); 1159 1160 /* step 4h: setup DSI protocol timeouts */ 1161 gen11_dsi_setup_timeouts(encoder, crtc_state); 1162 1163 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1164 gen11_dsi_configure_transcoder(encoder, crtc_state); 1165 1166 /* Step 4l: Gate DDI clocks */ 1167 gen11_dsi_gate_clocks(encoder); 1168 } 1169 1170 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1171 { 1172 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1173 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1174 struct mipi_dsi_device *dsi; 1175 enum port port; 1176 enum transcoder dsi_trans; 1177 u32 tmp; 1178 int ret; 1179 1180 /* set maximum return packet size */ 1181 for_each_dsi_port(port, intel_dsi->ports) { 1182 dsi_trans = dsi_port_to_transcoder(port); 1183 1184 /* 1185 * FIXME: This uses the number of DW's currently in the payload 1186 * receive queue. This is probably not what we want here. 1187 */ 1188 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans)); 1189 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1190 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1191 tmp = tmp * 4; 1192 dsi = intel_dsi->dsi_hosts[port]->device; 1193 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1194 if (ret < 0) 1195 drm_err(&dev_priv->drm, 1196 "error setting max return pkt size%d\n", tmp); 1197 } 1198 1199 /* panel power on related mipi dsi vbt sequences */ 1200 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1201 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 1202 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1203 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1204 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1205 1206 /* ensure all panel commands dispatched before enabling transcoder */ 1207 wait_for_cmds_dispatched_to_panel(encoder); 1208 } 1209 1210 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1211 struct intel_encoder *encoder, 1212 const struct intel_crtc_state *crtc_state, 1213 const struct drm_connector_state *conn_state) 1214 { 1215 /* step2: enable IO power */ 1216 gen11_dsi_enable_io_power(encoder); 1217 1218 /* step3: enable DSI PLL */ 1219 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1220 } 1221 1222 static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1223 struct intel_encoder *encoder, 1224 const struct intel_crtc_state *pipe_config, 1225 const struct drm_connector_state *conn_state) 1226 { 1227 /* step3b */ 1228 gen11_dsi_map_pll(encoder, pipe_config); 1229 1230 /* step4: enable DSI port and DPHY */ 1231 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1232 1233 /* step5: program and powerup panel */ 1234 gen11_dsi_powerup_panel(encoder); 1235 1236 intel_dsc_dsi_pps_write(encoder, pipe_config); 1237 1238 /* step6c: configure transcoder timings */ 1239 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1240 } 1241 1242 /* 1243 * Wa_1409054076:icl,jsl,ehl 1244 * When pipe A is disabled and MIPI DSI is enabled on pipe B, 1245 * the AMT KVMR feature will incorrectly see pipe A as enabled. 1246 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave 1247 * it set while DSI is enabled on pipe B 1248 */ 1249 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, 1250 enum pipe pipe, bool enable) 1251 { 1252 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1253 1254 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) 1255 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1256 IGNORE_KVMR_PIPE_A, 1257 enable ? IGNORE_KVMR_PIPE_A : 0); 1258 } 1259 1260 /* 1261 * Wa_16012360555:adl-p 1262 * SW will have to program the "LP to HS Wakeup Guardband" 1263 * to account for the repeaters on the HS Request/Ready 1264 * PPI signaling between the Display engine and the DPHY. 1265 */ 1266 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) 1267 { 1268 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1269 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1270 enum port port; 1271 1272 if (DISPLAY_VER(i915) == 13) { 1273 for_each_dsi_port(port, intel_dsi->ports) 1274 intel_de_rmw(i915, TGL_DSI_CHKN_REG(port), 1275 TGL_DSI_CHKN_LSHS_GB_MASK, 1276 TGL_DSI_CHKN_LSHS_GB(4)); 1277 } 1278 } 1279 1280 static void gen11_dsi_enable(struct intel_atomic_state *state, 1281 struct intel_encoder *encoder, 1282 const struct intel_crtc_state *crtc_state, 1283 const struct drm_connector_state *conn_state) 1284 { 1285 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1286 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 1287 1288 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 1289 1290 /* Wa_1409054076:icl,jsl,ehl */ 1291 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); 1292 1293 /* Wa_16012360555:adl-p */ 1294 adlp_set_lp_hs_wakeup_gb(encoder); 1295 1296 /* step6d: enable dsi transcoder */ 1297 gen11_dsi_enable_transcoder(encoder); 1298 1299 /* step7: enable backlight */ 1300 intel_backlight_enable(crtc_state, conn_state); 1301 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1302 1303 intel_crtc_vblank_on(crtc_state); 1304 } 1305 1306 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1307 { 1308 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1309 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1310 enum port port; 1311 enum transcoder dsi_trans; 1312 u32 tmp; 1313 1314 for_each_dsi_port(port, intel_dsi->ports) { 1315 dsi_trans = dsi_port_to_transcoder(port); 1316 1317 /* disable transcoder */ 1318 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1319 tmp &= ~PIPECONF_ENABLE; 1320 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1321 1322 /* wait for transcoder to be disabled */ 1323 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), 1324 PIPECONF_STATE_ENABLE, 50)) 1325 drm_err(&dev_priv->drm, 1326 "DSI trancoder not disabled\n"); 1327 } 1328 } 1329 1330 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1331 { 1332 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1333 1334 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1335 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1336 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1337 1338 /* ensure cmds dispatched to panel */ 1339 wait_for_cmds_dispatched_to_panel(encoder); 1340 } 1341 1342 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1343 { 1344 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1345 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1346 enum port port; 1347 enum transcoder dsi_trans; 1348 u32 tmp; 1349 1350 /* disable periodic update mode */ 1351 if (is_cmd_mode(intel_dsi)) { 1352 for_each_dsi_port(port, intel_dsi->ports) { 1353 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 1354 tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE; 1355 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 1356 } 1357 } 1358 1359 /* put dsi link in ULPS */ 1360 for_each_dsi_port(port, intel_dsi->ports) { 1361 dsi_trans = dsi_port_to_transcoder(port); 1362 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)); 1363 tmp |= LINK_ENTER_ULPS; 1364 tmp &= ~LINK_ULPS_TYPE_LP11; 1365 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp); 1366 1367 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 1368 LINK_IN_ULPS), 1369 10)) 1370 drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); 1371 } 1372 1373 /* disable ddi function */ 1374 for_each_dsi_port(port, intel_dsi->ports) { 1375 dsi_trans = dsi_port_to_transcoder(port); 1376 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1377 tmp &= ~TRANS_DDI_FUNC_ENABLE; 1378 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 1379 } 1380 1381 /* disable port sync mode if dual link */ 1382 if (intel_dsi->dual_link) { 1383 for_each_dsi_port(port, intel_dsi->ports) { 1384 dsi_trans = dsi_port_to_transcoder(port); 1385 tmp = intel_de_read(dev_priv, 1386 TRANS_DDI_FUNC_CTL2(dsi_trans)); 1387 tmp &= ~PORT_SYNC_MODE_ENABLE; 1388 intel_de_write(dev_priv, 1389 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 1390 } 1391 } 1392 } 1393 1394 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1395 { 1396 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1397 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1398 u32 tmp; 1399 enum port port; 1400 1401 gen11_dsi_ungate_clocks(encoder); 1402 for_each_dsi_port(port, intel_dsi->ports) { 1403 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1404 tmp &= ~DDI_BUF_CTL_ENABLE; 1405 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 1406 1407 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1408 DDI_BUF_IS_IDLE), 1409 8)) 1410 drm_err(&dev_priv->drm, 1411 "DDI port:%c buffer not idle\n", 1412 port_name(port)); 1413 } 1414 gen11_dsi_gate_clocks(encoder); 1415 } 1416 1417 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1418 { 1419 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1420 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1421 enum port port; 1422 u32 tmp; 1423 1424 for_each_dsi_port(port, intel_dsi->ports) { 1425 intel_wakeref_t wakeref; 1426 1427 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1428 intel_display_power_put(dev_priv, 1429 port == PORT_A ? 1430 POWER_DOMAIN_PORT_DDI_IO_A : 1431 POWER_DOMAIN_PORT_DDI_IO_B, 1432 wakeref); 1433 } 1434 1435 /* set mode to DDI */ 1436 for_each_dsi_port(port, intel_dsi->ports) { 1437 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 1438 tmp &= ~COMBO_PHY_MODE_DSI; 1439 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 1440 } 1441 } 1442 1443 static void gen11_dsi_disable(struct intel_atomic_state *state, 1444 struct intel_encoder *encoder, 1445 const struct intel_crtc_state *old_crtc_state, 1446 const struct drm_connector_state *old_conn_state) 1447 { 1448 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1449 struct intel_crtc *crtc = to_intel_crtc(old_conn_state->crtc); 1450 1451 /* step1: turn off backlight */ 1452 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1453 intel_backlight_disable(old_conn_state); 1454 1455 /* step2d,e: disable transcoder and wait */ 1456 gen11_dsi_disable_transcoder(encoder); 1457 1458 /* Wa_1409054076:icl,jsl,ehl */ 1459 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); 1460 1461 /* step2f,g: powerdown panel */ 1462 gen11_dsi_powerdown_panel(encoder); 1463 1464 /* step2h,i,j: deconfig trancoder */ 1465 gen11_dsi_deconfigure_trancoder(encoder); 1466 1467 /* step3: disable port */ 1468 gen11_dsi_disable_port(encoder); 1469 1470 gen11_dsi_config_util_pin(encoder, false); 1471 1472 /* step4: disable IO power */ 1473 gen11_dsi_disable_io_power(encoder); 1474 } 1475 1476 static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1477 struct intel_encoder *encoder, 1478 const struct intel_crtc_state *old_crtc_state, 1479 const struct drm_connector_state *old_conn_state) 1480 { 1481 intel_crtc_vblank_off(old_crtc_state); 1482 1483 intel_dsc_disable(old_crtc_state); 1484 1485 skl_scaler_disable(old_crtc_state); 1486 } 1487 1488 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1489 struct drm_display_mode *mode) 1490 { 1491 /* FIXME: DSC? */ 1492 return intel_dsi_mode_valid(connector, mode); 1493 } 1494 1495 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1496 struct intel_crtc_state *pipe_config) 1497 { 1498 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1499 struct drm_display_mode *adjusted_mode = 1500 &pipe_config->hw.adjusted_mode; 1501 1502 if (pipe_config->dsc.compressed_bpp) { 1503 int div = pipe_config->dsc.compressed_bpp; 1504 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1505 1506 adjusted_mode->crtc_htotal = 1507 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1508 adjusted_mode->crtc_hsync_start = 1509 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1510 adjusted_mode->crtc_hsync_end = 1511 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1512 } 1513 1514 if (intel_dsi->dual_link) { 1515 adjusted_mode->crtc_hdisplay *= 2; 1516 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1517 adjusted_mode->crtc_hdisplay -= 1518 intel_dsi->pixel_overlap; 1519 adjusted_mode->crtc_htotal *= 2; 1520 } 1521 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1522 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1523 1524 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1525 if (intel_dsi->dual_link) { 1526 adjusted_mode->crtc_hsync_start *= 2; 1527 adjusted_mode->crtc_hsync_end *= 2; 1528 } 1529 } 1530 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1531 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1532 } 1533 1534 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1535 { 1536 struct drm_device *dev = intel_dsi->base.base.dev; 1537 struct drm_i915_private *dev_priv = to_i915(dev); 1538 enum transcoder dsi_trans; 1539 u32 val; 1540 1541 if (intel_dsi->ports == BIT(PORT_B)) 1542 dsi_trans = TRANSCODER_DSI_1; 1543 else 1544 dsi_trans = TRANSCODER_DSI_0; 1545 1546 val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 1547 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1548 } 1549 1550 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1551 struct intel_crtc_state *pipe_config) 1552 { 1553 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1554 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1555 I915_MODE_FLAG_DSI_USE_TE0; 1556 else if (intel_dsi->ports == BIT(PORT_B)) 1557 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1558 else 1559 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1560 } 1561 1562 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1563 struct intel_crtc_state *pipe_config) 1564 { 1565 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1566 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1567 1568 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1569 1570 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1571 if (intel_dsi->dual_link) 1572 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1573 1574 gen11_dsi_get_timings(encoder, pipe_config); 1575 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1576 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1577 1578 /* Get the details on which TE should be enabled */ 1579 if (is_cmd_mode(intel_dsi)) 1580 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1581 1582 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1583 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1584 } 1585 1586 static void gen11_dsi_sync_state(struct intel_encoder *encoder, 1587 const struct intel_crtc_state *crtc_state) 1588 { 1589 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1590 struct intel_crtc *intel_crtc; 1591 enum pipe pipe; 1592 1593 if (!crtc_state) 1594 return; 1595 1596 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1597 pipe = intel_crtc->pipe; 1598 1599 /* wa verify 1409054076:icl,jsl,ehl */ 1600 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && 1601 !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A)) 1602 drm_dbg_kms(&dev_priv->drm, 1603 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n", 1604 encoder->base.base.id, 1605 encoder->base.name); 1606 } 1607 1608 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1609 struct intel_crtc_state *crtc_state) 1610 { 1611 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1612 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1613 int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10; 1614 bool use_dsc; 1615 int ret; 1616 1617 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1618 if (!use_dsc) 1619 return 0; 1620 1621 if (crtc_state->pipe_bpp < 8 * 3) 1622 return -EINVAL; 1623 1624 /* FIXME: split only when necessary */ 1625 if (crtc_state->dsc.slice_count > 1) 1626 crtc_state->dsc.dsc_split = true; 1627 1628 vdsc_cfg->convert_rgb = true; 1629 1630 /* FIXME: initialize from VBT */ 1631 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1632 1633 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1634 1635 ret = intel_dsc_compute_params(crtc_state); 1636 if (ret) 1637 return ret; 1638 1639 /* DSI specific sanity checks on the common code */ 1640 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); 1641 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); 1642 drm_WARN_ON(&dev_priv->drm, 1643 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1644 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); 1645 drm_WARN_ON(&dev_priv->drm, 1646 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1647 1648 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1649 if (ret) 1650 return ret; 1651 1652 crtc_state->dsc.compression_enable = true; 1653 1654 return 0; 1655 } 1656 1657 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1658 struct intel_crtc_state *pipe_config, 1659 struct drm_connector_state *conn_state) 1660 { 1661 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1662 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 1663 base); 1664 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1665 struct drm_display_mode *adjusted_mode = 1666 &pipe_config->hw.adjusted_mode; 1667 int ret; 1668 1669 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1670 1671 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 1672 if (ret) 1673 return ret; 1674 1675 ret = intel_panel_fitting(pipe_config, conn_state); 1676 if (ret) 1677 return ret; 1678 1679 adjusted_mode->flags = 0; 1680 1681 /* Dual link goes to trancoder DSI'0' */ 1682 if (intel_dsi->ports == BIT(PORT_B)) 1683 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1684 else 1685 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1686 1687 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1688 pipe_config->pipe_bpp = 24; 1689 else 1690 pipe_config->pipe_bpp = 18; 1691 1692 pipe_config->clock_set = true; 1693 1694 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1695 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n"); 1696 1697 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1698 1699 /* 1700 * In case of TE GATE cmd mode, we 1701 * receive TE from the slave if 1702 * dual link is enabled 1703 */ 1704 if (is_cmd_mode(intel_dsi)) 1705 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1706 1707 return 0; 1708 } 1709 1710 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1711 struct intel_crtc_state *crtc_state) 1712 { 1713 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1714 1715 get_dsi_io_power_domains(i915, 1716 enc_to_intel_dsi(encoder)); 1717 } 1718 1719 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1720 enum pipe *pipe) 1721 { 1722 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1723 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1724 enum transcoder dsi_trans; 1725 intel_wakeref_t wakeref; 1726 enum port port; 1727 bool ret = false; 1728 u32 tmp; 1729 1730 wakeref = intel_display_power_get_if_enabled(dev_priv, 1731 encoder->power_domain); 1732 if (!wakeref) 1733 return false; 1734 1735 for_each_dsi_port(port, intel_dsi->ports) { 1736 dsi_trans = dsi_port_to_transcoder(port); 1737 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1738 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1739 case TRANS_DDI_EDP_INPUT_A_ON: 1740 *pipe = PIPE_A; 1741 break; 1742 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1743 *pipe = PIPE_B; 1744 break; 1745 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1746 *pipe = PIPE_C; 1747 break; 1748 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1749 *pipe = PIPE_D; 1750 break; 1751 default: 1752 drm_err(&dev_priv->drm, "Invalid PIPE input\n"); 1753 goto out; 1754 } 1755 1756 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1757 ret = tmp & PIPECONF_ENABLE; 1758 } 1759 out: 1760 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1761 return ret; 1762 } 1763 1764 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1765 struct intel_crtc_state *crtc_state) 1766 { 1767 if (crtc_state->dsc.compression_enable) { 1768 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1769 crtc_state->uapi.mode_changed = true; 1770 1771 return false; 1772 } 1773 1774 return true; 1775 } 1776 1777 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1778 { 1779 intel_encoder_destroy(encoder); 1780 } 1781 1782 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1783 .destroy = gen11_dsi_encoder_destroy, 1784 }; 1785 1786 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1787 .detect = intel_panel_detect, 1788 .late_register = intel_connector_register, 1789 .early_unregister = intel_connector_unregister, 1790 .destroy = intel_connector_destroy, 1791 .fill_modes = drm_helper_probe_single_connector_modes, 1792 .atomic_get_property = intel_digital_connector_atomic_get_property, 1793 .atomic_set_property = intel_digital_connector_atomic_set_property, 1794 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1795 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1796 }; 1797 1798 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1799 .get_modes = intel_dsi_get_modes, 1800 .mode_valid = gen11_dsi_mode_valid, 1801 .atomic_check = intel_digital_connector_atomic_check, 1802 }; 1803 1804 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1805 struct mipi_dsi_device *dsi) 1806 { 1807 return 0; 1808 } 1809 1810 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1811 struct mipi_dsi_device *dsi) 1812 { 1813 return 0; 1814 } 1815 1816 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1817 const struct mipi_dsi_msg *msg) 1818 { 1819 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1820 struct mipi_dsi_packet dsi_pkt; 1821 ssize_t ret; 1822 bool enable_lpdt = false; 1823 1824 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1825 if (ret < 0) 1826 return ret; 1827 1828 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1829 enable_lpdt = true; 1830 1831 /* only long packet contains payload */ 1832 if (mipi_dsi_packet_format_is_long(msg->type)) { 1833 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt); 1834 if (ret < 0) 1835 return ret; 1836 } 1837 1838 /* send packet header */ 1839 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt); 1840 if (ret < 0) 1841 return ret; 1842 1843 //TODO: add payload receive code if needed 1844 1845 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1846 1847 return ret; 1848 } 1849 1850 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1851 .attach = gen11_dsi_host_attach, 1852 .detach = gen11_dsi_host_detach, 1853 .transfer = gen11_dsi_host_transfer, 1854 }; 1855 1856 #define ICL_PREPARE_CNT_MAX 0x7 1857 #define ICL_CLK_ZERO_CNT_MAX 0xf 1858 #define ICL_TRAIL_CNT_MAX 0x7 1859 #define ICL_TCLK_PRE_CNT_MAX 0x3 1860 #define ICL_TCLK_POST_CNT_MAX 0x7 1861 #define ICL_HS_ZERO_CNT_MAX 0xf 1862 #define ICL_EXIT_ZERO_CNT_MAX 0x7 1863 1864 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1865 { 1866 struct drm_device *dev = intel_dsi->base.base.dev; 1867 struct drm_i915_private *dev_priv = to_i915(dev); 1868 struct intel_connector *connector = intel_dsi->attached_connector; 1869 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1870 u32 tlpx_ns; 1871 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1872 u32 ths_prepare_ns, tclk_trail_ns; 1873 u32 hs_zero_cnt; 1874 u32 tclk_pre_cnt, tclk_post_cnt; 1875 1876 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1877 1878 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1879 ths_prepare_ns = max(mipi_config->ths_prepare, 1880 mipi_config->tclk_prepare); 1881 1882 /* 1883 * prepare cnt in escape clocks 1884 * this field represents a hexadecimal value with a precision 1885 * of 1.2 – i.e. the most significant bit is the integer 1886 * and the least significant 2 bits are fraction bits. 1887 * so, the field can represent a range of 0.25 to 1.75 1888 */ 1889 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1890 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1891 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", 1892 prepare_cnt); 1893 prepare_cnt = ICL_PREPARE_CNT_MAX; 1894 } 1895 1896 /* clk zero count in escape clocks */ 1897 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1898 ths_prepare_ns, tlpx_ns); 1899 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1900 drm_dbg_kms(&dev_priv->drm, 1901 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1902 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1903 } 1904 1905 /* trail cnt in escape clocks*/ 1906 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1907 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1908 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", 1909 trail_cnt); 1910 trail_cnt = ICL_TRAIL_CNT_MAX; 1911 } 1912 1913 /* tclk pre count in escape clocks */ 1914 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1915 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1916 drm_dbg_kms(&dev_priv->drm, 1917 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1918 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1919 } 1920 1921 /* tclk post count in escape clocks */ 1922 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); 1923 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { 1924 drm_dbg_kms(&dev_priv->drm, 1925 "tclk_post_cnt out of range (%d)\n", 1926 tclk_post_cnt); 1927 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; 1928 } 1929 1930 /* hs zero cnt in escape clocks */ 1931 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1932 ths_prepare_ns, tlpx_ns); 1933 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1934 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", 1935 hs_zero_cnt); 1936 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1937 } 1938 1939 /* hs exit zero cnt in escape clocks */ 1940 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1941 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1942 drm_dbg_kms(&dev_priv->drm, 1943 "exit_zero_cnt out of range (%d)\n", 1944 exit_zero_cnt); 1945 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1946 } 1947 1948 /* clock lane dphy timings */ 1949 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1950 CLK_PREPARE(prepare_cnt) | 1951 CLK_ZERO_OVERRIDE | 1952 CLK_ZERO(clk_zero_cnt) | 1953 CLK_PRE_OVERRIDE | 1954 CLK_PRE(tclk_pre_cnt) | 1955 CLK_POST_OVERRIDE | 1956 CLK_POST(tclk_post_cnt) | 1957 CLK_TRAIL_OVERRIDE | 1958 CLK_TRAIL(trail_cnt)); 1959 1960 /* data lanes dphy timings */ 1961 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1962 HS_PREPARE(prepare_cnt) | 1963 HS_ZERO_OVERRIDE | 1964 HS_ZERO(hs_zero_cnt) | 1965 HS_TRAIL_OVERRIDE | 1966 HS_TRAIL(trail_cnt) | 1967 HS_EXIT_OVERRIDE | 1968 HS_EXIT(exit_zero_cnt)); 1969 1970 intel_dsi_log_params(intel_dsi); 1971 } 1972 1973 static void icl_dsi_add_properties(struct intel_connector *connector) 1974 { 1975 const struct drm_display_mode *fixed_mode = 1976 intel_panel_preferred_fixed_mode(connector); 1977 u32 allowed_scalers; 1978 1979 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | 1980 BIT(DRM_MODE_SCALE_FULLSCREEN) | 1981 BIT(DRM_MODE_SCALE_CENTER); 1982 1983 drm_connector_attach_scaling_mode_property(&connector->base, 1984 allowed_scalers); 1985 1986 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1987 1988 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1989 intel_dsi_get_panel_orientation(connector), 1990 fixed_mode->hdisplay, 1991 fixed_mode->vdisplay); 1992 } 1993 1994 void icl_dsi_init(struct drm_i915_private *dev_priv) 1995 { 1996 struct drm_device *dev = &dev_priv->drm; 1997 struct intel_dsi *intel_dsi; 1998 struct intel_encoder *encoder; 1999 struct intel_connector *intel_connector; 2000 struct drm_connector *connector; 2001 enum port port; 2002 2003 if (!intel_bios_is_dsi_present(dev_priv, &port)) 2004 return; 2005 2006 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 2007 if (!intel_dsi) 2008 return; 2009 2010 intel_connector = intel_connector_alloc(); 2011 if (!intel_connector) { 2012 kfree(intel_dsi); 2013 return; 2014 } 2015 2016 encoder = &intel_dsi->base; 2017 intel_dsi->attached_connector = intel_connector; 2018 connector = &intel_connector->base; 2019 2020 /* register DSI encoder with DRM subsystem */ 2021 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs, 2022 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 2023 2024 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 2025 encoder->pre_enable = gen11_dsi_pre_enable; 2026 encoder->enable = gen11_dsi_enable; 2027 encoder->disable = gen11_dsi_disable; 2028 encoder->post_disable = gen11_dsi_post_disable; 2029 encoder->port = port; 2030 encoder->get_config = gen11_dsi_get_config; 2031 encoder->sync_state = gen11_dsi_sync_state; 2032 encoder->update_pipe = intel_backlight_update; 2033 encoder->compute_config = gen11_dsi_compute_config; 2034 encoder->get_hw_state = gen11_dsi_get_hw_state; 2035 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 2036 encoder->type = INTEL_OUTPUT_DSI; 2037 encoder->cloneable = 0; 2038 encoder->pipe_mask = ~0; 2039 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 2040 encoder->get_power_domains = gen11_dsi_get_power_domains; 2041 encoder->disable_clock = gen11_dsi_gate_clocks; 2042 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 2043 2044 /* register DSI connector with DRM subsystem */ 2045 drm_connector_init(dev, connector, &gen11_dsi_connector_funcs, 2046 DRM_MODE_CONNECTOR_DSI); 2047 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 2048 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 2049 connector->interlace_allowed = false; 2050 connector->doublescan_allowed = false; 2051 intel_connector->get_hw_state = intel_connector_get_hw_state; 2052 2053 /* attach connector to encoder */ 2054 intel_connector_attach_encoder(intel_connector, encoder); 2055 2056 intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL, NULL); 2057 2058 mutex_lock(&dev->mode_config.mutex); 2059 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 2060 mutex_unlock(&dev->mode_config.mutex); 2061 2062 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2063 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); 2064 goto err; 2065 } 2066 2067 intel_panel_init(intel_connector); 2068 2069 intel_backlight_setup(intel_connector, INVALID_PIPE); 2070 2071 if (intel_connector->panel.vbt.dsi.config->dual_link) 2072 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 2073 else 2074 intel_dsi->ports = BIT(port); 2075 2076 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) 2077 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; 2078 2079 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) 2080 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; 2081 2082 for_each_dsi_port(port, intel_dsi->ports) { 2083 struct intel_dsi_host *host; 2084 2085 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2086 if (!host) 2087 goto err; 2088 2089 intel_dsi->dsi_hosts[port] = host; 2090 } 2091 2092 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2093 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 2094 goto err; 2095 } 2096 2097 icl_dphy_param_init(intel_dsi); 2098 2099 icl_dsi_add_properties(intel_connector); 2100 return; 2101 2102 err: 2103 drm_connector_cleanup(connector); 2104 drm_encoder_cleanup(&encoder->base); 2105 kfree(intel_dsi); 2106 kfree(intel_connector); 2107 } 2108