1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/display/drm_dsc_helper.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_mipi_dsi.h> 31 32 #include "i915_reg.h" 33 #include "icl_dsi.h" 34 #include "icl_dsi_regs.h" 35 #include "intel_atomic.h" 36 #include "intel_backlight.h" 37 #include "intel_backlight_regs.h" 38 #include "intel_combo_phy.h" 39 #include "intel_combo_phy_regs.h" 40 #include "intel_connector.h" 41 #include "intel_crtc.h" 42 #include "intel_ddi.h" 43 #include "intel_de.h" 44 #include "intel_dsi.h" 45 #include "intel_dsi_vbt.h" 46 #include "intel_panel.h" 47 #include "intel_vdsc.h" 48 #include "skl_scaler.h" 49 #include "skl_universal_plane.h" 50 51 static int header_credits_available(struct drm_i915_private *dev_priv, 52 enum transcoder dsi_trans) 53 { 54 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 55 >> FREE_HEADER_CREDIT_SHIFT; 56 } 57 58 static int payload_credits_available(struct drm_i915_private *dev_priv, 59 enum transcoder dsi_trans) 60 { 61 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 62 >> FREE_PLOAD_CREDIT_SHIFT; 63 } 64 65 static bool wait_for_header_credits(struct drm_i915_private *dev_priv, 66 enum transcoder dsi_trans, int hdr_credit) 67 { 68 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= 69 hdr_credit, 100)) { 70 drm_err(&dev_priv->drm, "DSI header credits not released\n"); 71 return false; 72 } 73 74 return true; 75 } 76 77 static bool wait_for_payload_credits(struct drm_i915_private *dev_priv, 78 enum transcoder dsi_trans, int payld_credit) 79 { 80 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= 81 payld_credit, 100)) { 82 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); 83 return false; 84 } 85 86 return true; 87 } 88 89 static enum transcoder dsi_port_to_transcoder(enum port port) 90 { 91 if (port == PORT_A) 92 return TRANSCODER_DSI_0; 93 else 94 return TRANSCODER_DSI_1; 95 } 96 97 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 98 { 99 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 100 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 101 struct mipi_dsi_device *dsi; 102 enum port port; 103 enum transcoder dsi_trans; 104 int ret; 105 106 /* wait for header/payload credits to be released */ 107 for_each_dsi_port(port, intel_dsi->ports) { 108 dsi_trans = dsi_port_to_transcoder(port); 109 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 110 wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT); 111 } 112 113 /* send nop DCS command */ 114 for_each_dsi_port(port, intel_dsi->ports) { 115 dsi = intel_dsi->dsi_hosts[port]->device; 116 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 117 dsi->channel = 0; 118 ret = mipi_dsi_dcs_nop(dsi); 119 if (ret < 0) 120 drm_err(&dev_priv->drm, 121 "error sending DCS NOP command\n"); 122 } 123 124 /* wait for header credits to be released */ 125 for_each_dsi_port(port, intel_dsi->ports) { 126 dsi_trans = dsi_port_to_transcoder(port); 127 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 128 } 129 130 /* wait for LP TX in progress bit to be cleared */ 131 for_each_dsi_port(port, intel_dsi->ports) { 132 dsi_trans = dsi_port_to_transcoder(port); 133 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 134 LPTX_IN_PROGRESS), 20)) 135 drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); 136 } 137 } 138 139 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 140 const struct mipi_dsi_packet *packet) 141 { 142 struct intel_dsi *intel_dsi = host->intel_dsi; 143 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 144 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 145 const u8 *data = packet->payload; 146 u32 len = packet->payload_length; 147 int i, j; 148 149 /* payload queue can accept *256 bytes*, check limit */ 150 if (len > MAX_PLOAD_CREDIT * 4) { 151 drm_err(&i915->drm, "payload size exceeds max queue limit\n"); 152 return -EINVAL; 153 } 154 155 for (i = 0; i < len; i += 4) { 156 u32 tmp = 0; 157 158 if (!wait_for_payload_credits(i915, dsi_trans, 1)) 159 return -EBUSY; 160 161 for (j = 0; j < min_t(u32, len - i, 4); j++) 162 tmp |= *data++ << 8 * j; 163 164 intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp); 165 } 166 167 return 0; 168 } 169 170 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 171 const struct mipi_dsi_packet *packet, 172 bool enable_lpdt) 173 { 174 struct intel_dsi *intel_dsi = host->intel_dsi; 175 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 176 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 177 u32 tmp; 178 179 if (!wait_for_header_credits(dev_priv, dsi_trans, 1)) 180 return -EBUSY; 181 182 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); 183 184 if (packet->payload) 185 tmp |= PAYLOAD_PRESENT; 186 else 187 tmp &= ~PAYLOAD_PRESENT; 188 189 tmp &= ~VBLANK_FENCE; 190 191 if (enable_lpdt) 192 tmp |= LP_DATA_TRANSFER; 193 else 194 tmp &= ~LP_DATA_TRANSFER; 195 196 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 197 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); 198 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); 199 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); 200 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); 201 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); 202 203 return 0; 204 } 205 206 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 207 { 208 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 209 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 210 u32 tmp, mode_flags; 211 enum port port; 212 213 mode_flags = crtc_state->mode_flags; 214 215 /* 216 * case 1 also covers dual link 217 * In case of dual link, frame update should be set on 218 * DSI_0 219 */ 220 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 221 port = PORT_A; 222 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 223 port = PORT_B; 224 else 225 return; 226 227 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 228 tmp |= DSI_FRAME_UPDATE_REQUEST; 229 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 230 } 231 232 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 233 { 234 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 235 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 236 enum phy phy; 237 u32 tmp; 238 int lane; 239 240 for_each_dsi_phy(phy, intel_dsi->phys) { 241 /* 242 * Program voltage swing and pre-emphasis level values as per 243 * table in BSPEC under DDI buffer programing 244 */ 245 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 246 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 247 tmp |= SCALING_MODE_SEL(0x2); 248 tmp |= TAP2_DISABLE | TAP3_DISABLE; 249 tmp |= RTERM_SELECT(0x6); 250 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 251 252 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 253 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 254 tmp |= SCALING_MODE_SEL(0x2); 255 tmp |= TAP2_DISABLE | TAP3_DISABLE; 256 tmp |= RTERM_SELECT(0x6); 257 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 258 259 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 260 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 261 RCOMP_SCALAR_MASK); 262 tmp |= SWING_SEL_UPPER(0x2); 263 tmp |= SWING_SEL_LOWER(0x2); 264 tmp |= RCOMP_SCALAR(0x98); 265 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 266 267 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 268 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 269 RCOMP_SCALAR_MASK); 270 tmp |= SWING_SEL_UPPER(0x2); 271 tmp |= SWING_SEL_LOWER(0x2); 272 tmp |= RCOMP_SCALAR(0x98); 273 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 274 275 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 276 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 277 CURSOR_COEFF_MASK); 278 tmp |= POST_CURSOR_1(0x0); 279 tmp |= POST_CURSOR_2(0x0); 280 tmp |= CURSOR_COEFF(0x3f); 281 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 282 283 for (lane = 0; lane <= 3; lane++) { 284 /* Bspec: must not use GRP register for write */ 285 tmp = intel_de_read(dev_priv, 286 ICL_PORT_TX_DW4_LN(lane, phy)); 287 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 288 CURSOR_COEFF_MASK); 289 tmp |= POST_CURSOR_1(0x0); 290 tmp |= POST_CURSOR_2(0x0); 291 tmp |= CURSOR_COEFF(0x3f); 292 intel_de_write(dev_priv, 293 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 294 } 295 } 296 } 297 298 static void configure_dual_link_mode(struct intel_encoder *encoder, 299 const struct intel_crtc_state *pipe_config) 300 { 301 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 302 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 303 u32 dss_ctl1; 304 305 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); 306 dss_ctl1 |= SPLITTER_ENABLE; 307 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 308 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 309 310 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 311 const struct drm_display_mode *adjusted_mode = 312 &pipe_config->hw.adjusted_mode; 313 u32 dss_ctl2; 314 u16 hactive = adjusted_mode->crtc_hdisplay; 315 u16 dl_buffer_depth; 316 317 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 318 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 319 320 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 321 drm_err(&dev_priv->drm, 322 "DL buffer depth exceed max value\n"); 323 324 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 325 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 326 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); 327 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; 328 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 329 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); 330 } else { 331 /* Interleave */ 332 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 333 } 334 335 intel_de_write(dev_priv, DSS_CTL1, dss_ctl1); 336 } 337 338 /* aka DSI 8X clock */ 339 static int afe_clk(struct intel_encoder *encoder, 340 const struct intel_crtc_state *crtc_state) 341 { 342 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 343 int bpp; 344 345 if (crtc_state->dsc.compression_enable) 346 bpp = crtc_state->dsc.compressed_bpp; 347 else 348 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 349 350 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 351 } 352 353 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 354 const struct intel_crtc_state *crtc_state) 355 { 356 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 357 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 358 enum port port; 359 int afe_clk_khz; 360 int theo_word_clk, act_word_clk; 361 u32 esc_clk_div_m, esc_clk_div_m_phy; 362 363 afe_clk_khz = afe_clk(encoder, crtc_state); 364 365 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 366 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 367 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 368 esc_clk_div_m = act_word_clk * 8; 369 esc_clk_div_m_phy = (act_word_clk - 1) / 2; 370 } else { 371 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 372 } 373 374 for_each_dsi_port(port, intel_dsi->ports) { 375 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), 376 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 377 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); 378 } 379 380 for_each_dsi_port(port, intel_dsi->ports) { 381 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port), 382 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 383 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); 384 } 385 386 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 387 for_each_dsi_port(port, intel_dsi->ports) { 388 intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8), 389 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); 390 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8)); 391 } 392 } 393 } 394 395 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, 396 struct intel_dsi *intel_dsi) 397 { 398 enum port port; 399 400 for_each_dsi_port(port, intel_dsi->ports) { 401 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); 402 intel_dsi->io_wakeref[port] = 403 intel_display_power_get(dev_priv, 404 port == PORT_A ? 405 POWER_DOMAIN_PORT_DDI_IO_A : 406 POWER_DOMAIN_PORT_DDI_IO_B); 407 } 408 } 409 410 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 411 { 412 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 413 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 414 enum port port; 415 u32 tmp; 416 417 for_each_dsi_port(port, intel_dsi->ports) { 418 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 419 tmp |= COMBO_PHY_MODE_DSI; 420 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 421 } 422 423 get_dsi_io_power_domains(dev_priv, intel_dsi); 424 } 425 426 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 427 { 428 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 429 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 430 enum phy phy; 431 432 for_each_dsi_phy(phy, intel_dsi->phys) 433 intel_combo_phy_power_up_lanes(dev_priv, phy, true, 434 intel_dsi->lane_count, false); 435 } 436 437 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 438 { 439 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 440 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 441 enum phy phy; 442 u32 tmp; 443 int lane; 444 445 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 446 for_each_dsi_phy(phy, intel_dsi->phys) { 447 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 448 tmp &= ~LOADGEN_SELECT; 449 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 450 for (lane = 0; lane <= 3; lane++) { 451 tmp = intel_de_read(dev_priv, 452 ICL_PORT_TX_DW4_LN(lane, phy)); 453 tmp &= ~LOADGEN_SELECT; 454 if (lane != 2) 455 tmp |= LOADGEN_SELECT; 456 intel_de_write(dev_priv, 457 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 458 } 459 } 460 461 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 462 for_each_dsi_phy(phy, intel_dsi->phys) { 463 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 464 tmp &= ~FRC_LATENCY_OPTIM_MASK; 465 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 466 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 467 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 468 tmp &= ~FRC_LATENCY_OPTIM_MASK; 469 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 470 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 471 472 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 473 if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) { 474 tmp = intel_de_read(dev_priv, 475 ICL_PORT_PCS_DW1_AUX(phy)); 476 tmp &= ~LATENCY_OPTIM_MASK; 477 tmp |= LATENCY_OPTIM_VAL(0); 478 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), 479 tmp); 480 481 tmp = intel_de_read(dev_priv, 482 ICL_PORT_PCS_DW1_LN(0, phy)); 483 tmp &= ~LATENCY_OPTIM_MASK; 484 tmp |= LATENCY_OPTIM_VAL(0x1); 485 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), 486 tmp); 487 } 488 } 489 490 } 491 492 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 493 { 494 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 495 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 496 u32 tmp; 497 enum phy phy; 498 499 /* clear common keeper enable bit */ 500 for_each_dsi_phy(phy, intel_dsi->phys) { 501 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 502 tmp &= ~COMMON_KEEPER_EN; 503 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp); 504 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy)); 505 tmp &= ~COMMON_KEEPER_EN; 506 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp); 507 } 508 509 /* 510 * Set SUS Clock Config bitfield to 11b 511 * Note: loadgen select program is done 512 * as part of lane phy sequence configuration 513 */ 514 for_each_dsi_phy(phy, intel_dsi->phys) { 515 tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 516 tmp |= SUS_CLOCK_CONFIG; 517 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp); 518 } 519 520 /* Clear training enable to change swing values */ 521 for_each_dsi_phy(phy, intel_dsi->phys) { 522 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 523 tmp &= ~TX_TRAINING_EN; 524 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 525 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 526 tmp &= ~TX_TRAINING_EN; 527 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 528 } 529 530 /* Program swing and de-emphasis */ 531 dsi_program_swing_and_deemphasis(encoder); 532 533 /* Set training enable to trigger update */ 534 for_each_dsi_phy(phy, intel_dsi->phys) { 535 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 536 tmp |= TX_TRAINING_EN; 537 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 538 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 539 tmp |= TX_TRAINING_EN; 540 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 541 } 542 } 543 544 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 545 { 546 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 547 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 548 u32 tmp; 549 enum port port; 550 551 for_each_dsi_port(port, intel_dsi->ports) { 552 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 553 tmp |= DDI_BUF_CTL_ENABLE; 554 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 555 556 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 557 DDI_BUF_IS_IDLE), 558 500)) 559 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", 560 port_name(port)); 561 } 562 } 563 564 static void 565 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 566 const struct intel_crtc_state *crtc_state) 567 { 568 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 569 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 570 u32 tmp; 571 enum port port; 572 enum phy phy; 573 574 /* Program T-INIT master registers */ 575 for_each_dsi_port(port, intel_dsi->ports) { 576 tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port)); 577 tmp &= ~DSI_T_INIT_MASTER_MASK; 578 tmp |= intel_dsi->init_count; 579 intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp); 580 } 581 582 /* Program DPHY clock lanes timings */ 583 for_each_dsi_port(port, intel_dsi->ports) { 584 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port), 585 intel_dsi->dphy_reg); 586 587 /* shadow register inside display core */ 588 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port), 589 intel_dsi->dphy_reg); 590 } 591 592 /* Program DPHY data lanes timings */ 593 for_each_dsi_port(port, intel_dsi->ports) { 594 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port), 595 intel_dsi->dphy_data_lane_reg); 596 597 /* shadow register inside display core */ 598 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port), 599 intel_dsi->dphy_data_lane_reg); 600 } 601 602 /* 603 * If DSI link operating at or below an 800 MHz, 604 * TA_SURE should be override and programmed to 605 * a value '0' inside TA_PARAM_REGISTERS otherwise 606 * leave all fields at HW default values. 607 */ 608 if (DISPLAY_VER(dev_priv) == 11) { 609 if (afe_clk(encoder, crtc_state) <= 800000) { 610 for_each_dsi_port(port, intel_dsi->ports) { 611 tmp = intel_de_read(dev_priv, 612 DPHY_TA_TIMING_PARAM(port)); 613 tmp &= ~TA_SURE_MASK; 614 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 615 intel_de_write(dev_priv, 616 DPHY_TA_TIMING_PARAM(port), 617 tmp); 618 619 /* shadow register inside display core */ 620 tmp = intel_de_read(dev_priv, 621 DSI_TA_TIMING_PARAM(port)); 622 tmp &= ~TA_SURE_MASK; 623 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 624 intel_de_write(dev_priv, 625 DSI_TA_TIMING_PARAM(port), tmp); 626 } 627 } 628 } 629 630 if (IS_JSL_EHL(dev_priv)) { 631 for_each_dsi_phy(phy, intel_dsi->phys) { 632 tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy)); 633 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; 634 intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp); 635 } 636 } 637 } 638 639 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 640 { 641 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 642 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 643 u32 tmp; 644 enum phy phy; 645 646 mutex_lock(&dev_priv->display.dpll.lock); 647 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 648 for_each_dsi_phy(phy, intel_dsi->phys) 649 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 650 651 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 652 mutex_unlock(&dev_priv->display.dpll.lock); 653 } 654 655 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 656 { 657 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 658 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 659 u32 tmp; 660 enum phy phy; 661 662 mutex_lock(&dev_priv->display.dpll.lock); 663 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 664 for_each_dsi_phy(phy, intel_dsi->phys) 665 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 666 667 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 668 mutex_unlock(&dev_priv->display.dpll.lock); 669 } 670 671 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 672 { 673 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 674 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 675 bool clock_enabled = false; 676 enum phy phy; 677 u32 tmp; 678 679 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 680 681 for_each_dsi_phy(phy, intel_dsi->phys) { 682 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 683 clock_enabled = true; 684 } 685 686 return clock_enabled; 687 } 688 689 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 690 const struct intel_crtc_state *crtc_state) 691 { 692 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 693 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 694 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 695 enum phy phy; 696 u32 val; 697 698 mutex_lock(&dev_priv->display.dpll.lock); 699 700 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 701 for_each_dsi_phy(phy, intel_dsi->phys) { 702 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 703 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 704 } 705 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 706 707 for_each_dsi_phy(phy, intel_dsi->phys) { 708 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 709 } 710 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 711 712 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 713 714 mutex_unlock(&dev_priv->display.dpll.lock); 715 } 716 717 static void 718 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 719 const struct intel_crtc_state *pipe_config) 720 { 721 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 722 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 723 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 724 enum pipe pipe = crtc->pipe; 725 u32 tmp; 726 enum port port; 727 enum transcoder dsi_trans; 728 729 for_each_dsi_port(port, intel_dsi->ports) { 730 dsi_trans = dsi_port_to_transcoder(port); 731 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 732 733 if (intel_dsi->eotp_pkt) 734 tmp &= ~EOTP_DISABLED; 735 else 736 tmp |= EOTP_DISABLED; 737 738 /* enable link calibration if freq > 1.5Gbps */ 739 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 740 tmp &= ~LINK_CALIBRATION_MASK; 741 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 742 } 743 744 /* configure continuous clock */ 745 tmp &= ~CONTINUOUS_CLK_MASK; 746 if (intel_dsi->clock_stop) 747 tmp |= CLK_ENTER_LP_AFTER_DATA; 748 else 749 tmp |= CLK_HS_CONTINUOUS; 750 751 /* configure buffer threshold limit to minimum */ 752 tmp &= ~PIX_BUF_THRESHOLD_MASK; 753 tmp |= PIX_BUF_THRESHOLD_1_4; 754 755 /* set virtual channel to '0' */ 756 tmp &= ~PIX_VIRT_CHAN_MASK; 757 tmp |= PIX_VIRT_CHAN(0); 758 759 /* program BGR transmission */ 760 if (intel_dsi->bgr_enabled) 761 tmp |= BGR_TRANSMISSION; 762 763 /* select pixel format */ 764 tmp &= ~PIX_FMT_MASK; 765 if (pipe_config->dsc.compression_enable) { 766 tmp |= PIX_FMT_COMPRESSED; 767 } else { 768 switch (intel_dsi->pixel_format) { 769 default: 770 MISSING_CASE(intel_dsi->pixel_format); 771 fallthrough; 772 case MIPI_DSI_FMT_RGB565: 773 tmp |= PIX_FMT_RGB565; 774 break; 775 case MIPI_DSI_FMT_RGB666_PACKED: 776 tmp |= PIX_FMT_RGB666_PACKED; 777 break; 778 case MIPI_DSI_FMT_RGB666: 779 tmp |= PIX_FMT_RGB666_LOOSE; 780 break; 781 case MIPI_DSI_FMT_RGB888: 782 tmp |= PIX_FMT_RGB888; 783 break; 784 } 785 } 786 787 if (DISPLAY_VER(dev_priv) >= 12) { 788 if (is_vid_mode(intel_dsi)) 789 tmp |= BLANKING_PACKET_ENABLE; 790 } 791 792 /* program DSI operation mode */ 793 if (is_vid_mode(intel_dsi)) { 794 tmp &= ~OP_MODE_MASK; 795 switch (intel_dsi->video_mode) { 796 default: 797 MISSING_CASE(intel_dsi->video_mode); 798 fallthrough; 799 case NON_BURST_SYNC_EVENTS: 800 tmp |= VIDEO_MODE_SYNC_EVENT; 801 break; 802 case NON_BURST_SYNC_PULSE: 803 tmp |= VIDEO_MODE_SYNC_PULSE; 804 break; 805 } 806 } else { 807 /* 808 * FIXME: Retrieve this info from VBT. 809 * As per the spec when dsi transcoder is operating 810 * in TE GATE mode, TE comes from GPIO 811 * which is UTIL PIN for DSI 0. 812 * Also this GPIO would not be used for other 813 * purposes is an assumption. 814 */ 815 tmp &= ~OP_MODE_MASK; 816 tmp |= CMD_MODE_TE_GATE; 817 tmp |= TE_SOURCE_GPIO; 818 } 819 820 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 821 } 822 823 /* enable port sync mode if dual link */ 824 if (intel_dsi->dual_link) { 825 for_each_dsi_port(port, intel_dsi->ports) { 826 dsi_trans = dsi_port_to_transcoder(port); 827 tmp = intel_de_read(dev_priv, 828 TRANS_DDI_FUNC_CTL2(dsi_trans)); 829 tmp |= PORT_SYNC_MODE_ENABLE; 830 intel_de_write(dev_priv, 831 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 832 } 833 834 /* configure stream splitting */ 835 configure_dual_link_mode(encoder, pipe_config); 836 } 837 838 for_each_dsi_port(port, intel_dsi->ports) { 839 dsi_trans = dsi_port_to_transcoder(port); 840 841 /* select data lane width */ 842 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 843 tmp &= ~DDI_PORT_WIDTH_MASK; 844 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); 845 846 /* select input pipe */ 847 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 848 switch (pipe) { 849 default: 850 MISSING_CASE(pipe); 851 fallthrough; 852 case PIPE_A: 853 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 854 break; 855 case PIPE_B: 856 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 857 break; 858 case PIPE_C: 859 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 860 break; 861 case PIPE_D: 862 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 863 break; 864 } 865 866 /* enable DDI buffer */ 867 tmp |= TRANS_DDI_FUNC_ENABLE; 868 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 869 } 870 871 /* wait for link ready */ 872 for_each_dsi_port(port, intel_dsi->ports) { 873 dsi_trans = dsi_port_to_transcoder(port); 874 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) & 875 LINK_READY), 2500)) 876 drm_err(&dev_priv->drm, "DSI link not ready\n"); 877 } 878 } 879 880 static void 881 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 882 const struct intel_crtc_state *crtc_state) 883 { 884 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 885 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 886 const struct drm_display_mode *adjusted_mode = 887 &crtc_state->hw.adjusted_mode; 888 enum port port; 889 enum transcoder dsi_trans; 890 /* horizontal timings */ 891 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 892 u16 hback_porch; 893 /* vertical timings */ 894 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 895 int mul = 1, div = 1; 896 897 /* 898 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 899 * for slower link speed if DSC is enabled. 900 * 901 * The compression frequency ratio is the ratio between compressed and 902 * non-compressed link speeds, and simplifies down to the ratio between 903 * compressed and non-compressed bpp. 904 */ 905 if (crtc_state->dsc.compression_enable) { 906 mul = crtc_state->dsc.compressed_bpp; 907 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 908 } 909 910 hactive = adjusted_mode->crtc_hdisplay; 911 912 if (is_vid_mode(intel_dsi)) 913 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 914 else 915 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 916 917 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 918 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 919 hsync_size = hsync_end - hsync_start; 920 hback_porch = (adjusted_mode->crtc_htotal - 921 adjusted_mode->crtc_hsync_end); 922 vactive = adjusted_mode->crtc_vdisplay; 923 924 if (is_vid_mode(intel_dsi)) { 925 vtotal = adjusted_mode->crtc_vtotal; 926 } else { 927 int bpp, line_time_us, byte_clk_period_ns; 928 929 if (crtc_state->dsc.compression_enable) 930 bpp = crtc_state->dsc.compressed_bpp; 931 else 932 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 933 934 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 935 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 936 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 937 } 938 vsync_start = adjusted_mode->crtc_vsync_start; 939 vsync_end = adjusted_mode->crtc_vsync_end; 940 vsync_shift = hsync_start - htotal / 2; 941 942 if (intel_dsi->dual_link) { 943 hactive /= 2; 944 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 945 hactive += intel_dsi->pixel_overlap; 946 htotal /= 2; 947 } 948 949 /* minimum hactive as per bspec: 256 pixels */ 950 if (adjusted_mode->crtc_hdisplay < 256) 951 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); 952 953 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 954 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 955 drm_err(&dev_priv->drm, 956 "hactive pixels are not multiple of 4\n"); 957 958 /* program TRANS_HTOTAL register */ 959 for_each_dsi_port(port, intel_dsi->ports) { 960 dsi_trans = dsi_port_to_transcoder(port); 961 intel_de_write(dev_priv, HTOTAL(dsi_trans), 962 (hactive - 1) | ((htotal - 1) << 16)); 963 } 964 965 /* TRANS_HSYNC register to be programmed only for video mode */ 966 if (is_vid_mode(intel_dsi)) { 967 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { 968 /* BSPEC: hsync size should be atleast 16 pixels */ 969 if (hsync_size < 16) 970 drm_err(&dev_priv->drm, 971 "hsync size < 16 pixels\n"); 972 } 973 974 if (hback_porch < 16) 975 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); 976 977 if (intel_dsi->dual_link) { 978 hsync_start /= 2; 979 hsync_end /= 2; 980 } 981 982 for_each_dsi_port(port, intel_dsi->ports) { 983 dsi_trans = dsi_port_to_transcoder(port); 984 intel_de_write(dev_priv, HSYNC(dsi_trans), 985 (hsync_start - 1) | ((hsync_end - 1) << 16)); 986 } 987 } 988 989 /* program TRANS_VTOTAL register */ 990 for_each_dsi_port(port, intel_dsi->ports) { 991 dsi_trans = dsi_port_to_transcoder(port); 992 /* 993 * FIXME: Programing this by assuming progressive mode, since 994 * non-interlaced info from VBT is not saved inside 995 * struct drm_display_mode. 996 * For interlace mode: program required pixel minus 2 997 */ 998 intel_de_write(dev_priv, VTOTAL(dsi_trans), 999 (vactive - 1) | ((vtotal - 1) << 16)); 1000 } 1001 1002 if (vsync_end < vsync_start || vsync_end > vtotal) 1003 drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); 1004 1005 if (vsync_start < vactive) 1006 drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); 1007 1008 /* program TRANS_VSYNC register for video mode only */ 1009 if (is_vid_mode(intel_dsi)) { 1010 for_each_dsi_port(port, intel_dsi->ports) { 1011 dsi_trans = dsi_port_to_transcoder(port); 1012 intel_de_write(dev_priv, VSYNC(dsi_trans), 1013 (vsync_start - 1) | ((vsync_end - 1) << 16)); 1014 } 1015 } 1016 1017 /* 1018 * FIXME: It has to be programmed only for video modes and interlaced 1019 * modes. Put the check condition here once interlaced 1020 * info available as described above. 1021 * program TRANS_VSYNCSHIFT register 1022 */ 1023 if (is_vid_mode(intel_dsi)) { 1024 for_each_dsi_port(port, intel_dsi->ports) { 1025 dsi_trans = dsi_port_to_transcoder(port); 1026 intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans), 1027 vsync_shift); 1028 } 1029 } 1030 1031 /* program TRANS_VBLANK register, should be same as vtotal programmed */ 1032 if (DISPLAY_VER(dev_priv) >= 12) { 1033 for_each_dsi_port(port, intel_dsi->ports) { 1034 dsi_trans = dsi_port_to_transcoder(port); 1035 intel_de_write(dev_priv, VBLANK(dsi_trans), 1036 (vactive - 1) | ((vtotal - 1) << 16)); 1037 } 1038 } 1039 } 1040 1041 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1042 { 1043 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1044 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1045 enum port port; 1046 enum transcoder dsi_trans; 1047 u32 tmp; 1048 1049 for_each_dsi_port(port, intel_dsi->ports) { 1050 dsi_trans = dsi_port_to_transcoder(port); 1051 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1052 tmp |= PIPECONF_ENABLE; 1053 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1054 1055 /* wait for transcoder to be enabled */ 1056 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), 1057 PIPECONF_STATE_ENABLE, 10)) 1058 drm_err(&dev_priv->drm, 1059 "DSI transcoder not enabled\n"); 1060 } 1061 } 1062 1063 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1064 const struct intel_crtc_state *crtc_state) 1065 { 1066 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1067 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1068 enum port port; 1069 enum transcoder dsi_trans; 1070 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1071 1072 /* 1073 * escape clock count calculation: 1074 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1075 * UI (nsec) = (10^6)/Bitrate 1076 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1077 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1078 */ 1079 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1080 mul = 8 * 1000000; 1081 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1082 divisor); 1083 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1084 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1085 1086 for_each_dsi_port(port, intel_dsi->ports) { 1087 dsi_trans = dsi_port_to_transcoder(port); 1088 1089 /* program hst_tx_timeout */ 1090 tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans)); 1091 tmp &= ~HSTX_TIMEOUT_VALUE_MASK; 1092 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout); 1093 intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp); 1094 1095 /* FIXME: DSI_CALIB_TO */ 1096 1097 /* program lp_rx_host timeout */ 1098 tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans)); 1099 tmp &= ~LPRX_TIMEOUT_VALUE_MASK; 1100 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout); 1101 intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp); 1102 1103 /* FIXME: DSI_PWAIT_TO */ 1104 1105 /* program turn around timeout */ 1106 tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans)); 1107 tmp &= ~TA_TIMEOUT_VALUE_MASK; 1108 tmp |= TA_TIMEOUT_VALUE(ta_timeout); 1109 intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp); 1110 } 1111 } 1112 1113 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1114 bool enable) 1115 { 1116 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1117 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1118 u32 tmp; 1119 1120 /* 1121 * used as TE i/p for DSI0, 1122 * for dual link/DSI1 TE is from slave DSI1 1123 * through GPIO. 1124 */ 1125 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1126 return; 1127 1128 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL); 1129 1130 if (enable) { 1131 tmp |= UTIL_PIN_DIRECTION_INPUT; 1132 tmp |= UTIL_PIN_ENABLE; 1133 } else { 1134 tmp &= ~UTIL_PIN_ENABLE; 1135 } 1136 intel_de_write(dev_priv, UTIL_PIN_CTL, tmp); 1137 } 1138 1139 static void 1140 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1141 const struct intel_crtc_state *crtc_state) 1142 { 1143 /* step 4a: power up all lanes of the DDI used by DSI */ 1144 gen11_dsi_power_up_lanes(encoder); 1145 1146 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1147 gen11_dsi_config_phy_lanes_sequence(encoder); 1148 1149 /* step 4c: configure voltage swing and skew */ 1150 gen11_dsi_voltage_swing_program_seq(encoder); 1151 1152 /* enable DDI buffer */ 1153 gen11_dsi_enable_ddi_buffer(encoder); 1154 1155 /* setup D-PHY timings */ 1156 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1157 1158 /* Since transcoder is configured to take events from GPIO */ 1159 gen11_dsi_config_util_pin(encoder, true); 1160 1161 /* step 4h: setup DSI protocol timeouts */ 1162 gen11_dsi_setup_timeouts(encoder, crtc_state); 1163 1164 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1165 gen11_dsi_configure_transcoder(encoder, crtc_state); 1166 1167 /* Step 4l: Gate DDI clocks */ 1168 gen11_dsi_gate_clocks(encoder); 1169 } 1170 1171 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1172 { 1173 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1174 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1175 struct mipi_dsi_device *dsi; 1176 enum port port; 1177 enum transcoder dsi_trans; 1178 u32 tmp; 1179 int ret; 1180 1181 /* set maximum return packet size */ 1182 for_each_dsi_port(port, intel_dsi->ports) { 1183 dsi_trans = dsi_port_to_transcoder(port); 1184 1185 /* 1186 * FIXME: This uses the number of DW's currently in the payload 1187 * receive queue. This is probably not what we want here. 1188 */ 1189 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans)); 1190 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1191 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1192 tmp = tmp * 4; 1193 dsi = intel_dsi->dsi_hosts[port]->device; 1194 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1195 if (ret < 0) 1196 drm_err(&dev_priv->drm, 1197 "error setting max return pkt size%d\n", tmp); 1198 } 1199 1200 /* panel power on related mipi dsi vbt sequences */ 1201 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1202 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 1203 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1204 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1205 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1206 1207 /* ensure all panel commands dispatched before enabling transcoder */ 1208 wait_for_cmds_dispatched_to_panel(encoder); 1209 } 1210 1211 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1212 struct intel_encoder *encoder, 1213 const struct intel_crtc_state *crtc_state, 1214 const struct drm_connector_state *conn_state) 1215 { 1216 /* step2: enable IO power */ 1217 gen11_dsi_enable_io_power(encoder); 1218 1219 /* step3: enable DSI PLL */ 1220 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1221 } 1222 1223 static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1224 struct intel_encoder *encoder, 1225 const struct intel_crtc_state *pipe_config, 1226 const struct drm_connector_state *conn_state) 1227 { 1228 /* step3b */ 1229 gen11_dsi_map_pll(encoder, pipe_config); 1230 1231 /* step4: enable DSI port and DPHY */ 1232 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1233 1234 /* step5: program and powerup panel */ 1235 gen11_dsi_powerup_panel(encoder); 1236 1237 intel_dsc_dsi_pps_write(encoder, pipe_config); 1238 1239 /* step6c: configure transcoder timings */ 1240 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1241 } 1242 1243 /* 1244 * Wa_1409054076:icl,jsl,ehl 1245 * When pipe A is disabled and MIPI DSI is enabled on pipe B, 1246 * the AMT KVMR feature will incorrectly see pipe A as enabled. 1247 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave 1248 * it set while DSI is enabled on pipe B 1249 */ 1250 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, 1251 enum pipe pipe, bool enable) 1252 { 1253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1254 1255 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) 1256 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1257 IGNORE_KVMR_PIPE_A, 1258 enable ? IGNORE_KVMR_PIPE_A : 0); 1259 } 1260 1261 /* 1262 * Wa_16012360555:adl-p 1263 * SW will have to program the "LP to HS Wakeup Guardband" 1264 * to account for the repeaters on the HS Request/Ready 1265 * PPI signaling between the Display engine and the DPHY. 1266 */ 1267 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) 1268 { 1269 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1270 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1271 enum port port; 1272 1273 if (DISPLAY_VER(i915) == 13) { 1274 for_each_dsi_port(port, intel_dsi->ports) 1275 intel_de_rmw(i915, TGL_DSI_CHKN_REG(port), 1276 TGL_DSI_CHKN_LSHS_GB_MASK, 1277 TGL_DSI_CHKN_LSHS_GB(4)); 1278 } 1279 } 1280 1281 static void gen11_dsi_enable(struct intel_atomic_state *state, 1282 struct intel_encoder *encoder, 1283 const struct intel_crtc_state *crtc_state, 1284 const struct drm_connector_state *conn_state) 1285 { 1286 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1287 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 1288 1289 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 1290 1291 /* Wa_1409054076:icl,jsl,ehl */ 1292 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); 1293 1294 /* Wa_16012360555:adl-p */ 1295 adlp_set_lp_hs_wakeup_gb(encoder); 1296 1297 /* step6d: enable dsi transcoder */ 1298 gen11_dsi_enable_transcoder(encoder); 1299 1300 /* step7: enable backlight */ 1301 intel_backlight_enable(crtc_state, conn_state); 1302 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1303 1304 intel_crtc_vblank_on(crtc_state); 1305 } 1306 1307 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1308 { 1309 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1310 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1311 enum port port; 1312 enum transcoder dsi_trans; 1313 u32 tmp; 1314 1315 for_each_dsi_port(port, intel_dsi->ports) { 1316 dsi_trans = dsi_port_to_transcoder(port); 1317 1318 /* disable transcoder */ 1319 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1320 tmp &= ~PIPECONF_ENABLE; 1321 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1322 1323 /* wait for transcoder to be disabled */ 1324 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), 1325 PIPECONF_STATE_ENABLE, 50)) 1326 drm_err(&dev_priv->drm, 1327 "DSI trancoder not disabled\n"); 1328 } 1329 } 1330 1331 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1332 { 1333 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1334 1335 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1336 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1337 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1338 1339 /* ensure cmds dispatched to panel */ 1340 wait_for_cmds_dispatched_to_panel(encoder); 1341 } 1342 1343 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1344 { 1345 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1346 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1347 enum port port; 1348 enum transcoder dsi_trans; 1349 u32 tmp; 1350 1351 /* disable periodic update mode */ 1352 if (is_cmd_mode(intel_dsi)) { 1353 for_each_dsi_port(port, intel_dsi->ports) { 1354 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 1355 tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE; 1356 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 1357 } 1358 } 1359 1360 /* put dsi link in ULPS */ 1361 for_each_dsi_port(port, intel_dsi->ports) { 1362 dsi_trans = dsi_port_to_transcoder(port); 1363 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)); 1364 tmp |= LINK_ENTER_ULPS; 1365 tmp &= ~LINK_ULPS_TYPE_LP11; 1366 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp); 1367 1368 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 1369 LINK_IN_ULPS), 1370 10)) 1371 drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); 1372 } 1373 1374 /* disable ddi function */ 1375 for_each_dsi_port(port, intel_dsi->ports) { 1376 dsi_trans = dsi_port_to_transcoder(port); 1377 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1378 tmp &= ~TRANS_DDI_FUNC_ENABLE; 1379 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 1380 } 1381 1382 /* disable port sync mode if dual link */ 1383 if (intel_dsi->dual_link) { 1384 for_each_dsi_port(port, intel_dsi->ports) { 1385 dsi_trans = dsi_port_to_transcoder(port); 1386 tmp = intel_de_read(dev_priv, 1387 TRANS_DDI_FUNC_CTL2(dsi_trans)); 1388 tmp &= ~PORT_SYNC_MODE_ENABLE; 1389 intel_de_write(dev_priv, 1390 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 1391 } 1392 } 1393 } 1394 1395 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1396 { 1397 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1398 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1399 u32 tmp; 1400 enum port port; 1401 1402 gen11_dsi_ungate_clocks(encoder); 1403 for_each_dsi_port(port, intel_dsi->ports) { 1404 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1405 tmp &= ~DDI_BUF_CTL_ENABLE; 1406 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 1407 1408 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1409 DDI_BUF_IS_IDLE), 1410 8)) 1411 drm_err(&dev_priv->drm, 1412 "DDI port:%c buffer not idle\n", 1413 port_name(port)); 1414 } 1415 gen11_dsi_gate_clocks(encoder); 1416 } 1417 1418 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1419 { 1420 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1421 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1422 enum port port; 1423 u32 tmp; 1424 1425 for_each_dsi_port(port, intel_dsi->ports) { 1426 intel_wakeref_t wakeref; 1427 1428 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1429 intel_display_power_put(dev_priv, 1430 port == PORT_A ? 1431 POWER_DOMAIN_PORT_DDI_IO_A : 1432 POWER_DOMAIN_PORT_DDI_IO_B, 1433 wakeref); 1434 } 1435 1436 /* set mode to DDI */ 1437 for_each_dsi_port(port, intel_dsi->ports) { 1438 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 1439 tmp &= ~COMBO_PHY_MODE_DSI; 1440 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 1441 } 1442 } 1443 1444 static void gen11_dsi_disable(struct intel_atomic_state *state, 1445 struct intel_encoder *encoder, 1446 const struct intel_crtc_state *old_crtc_state, 1447 const struct drm_connector_state *old_conn_state) 1448 { 1449 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1450 struct intel_crtc *crtc = to_intel_crtc(old_conn_state->crtc); 1451 1452 /* step1: turn off backlight */ 1453 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1454 intel_backlight_disable(old_conn_state); 1455 1456 /* step2d,e: disable transcoder and wait */ 1457 gen11_dsi_disable_transcoder(encoder); 1458 1459 /* Wa_1409054076:icl,jsl,ehl */ 1460 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); 1461 1462 /* step2f,g: powerdown panel */ 1463 gen11_dsi_powerdown_panel(encoder); 1464 1465 /* step2h,i,j: deconfig trancoder */ 1466 gen11_dsi_deconfigure_trancoder(encoder); 1467 1468 /* step3: disable port */ 1469 gen11_dsi_disable_port(encoder); 1470 1471 gen11_dsi_config_util_pin(encoder, false); 1472 1473 /* step4: disable IO power */ 1474 gen11_dsi_disable_io_power(encoder); 1475 } 1476 1477 static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1478 struct intel_encoder *encoder, 1479 const struct intel_crtc_state *old_crtc_state, 1480 const struct drm_connector_state *old_conn_state) 1481 { 1482 intel_crtc_vblank_off(old_crtc_state); 1483 1484 intel_dsc_disable(old_crtc_state); 1485 1486 skl_scaler_disable(old_crtc_state); 1487 } 1488 1489 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1490 struct drm_display_mode *mode) 1491 { 1492 /* FIXME: DSC? */ 1493 return intel_dsi_mode_valid(connector, mode); 1494 } 1495 1496 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1497 struct intel_crtc_state *pipe_config) 1498 { 1499 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1500 struct drm_display_mode *adjusted_mode = 1501 &pipe_config->hw.adjusted_mode; 1502 1503 if (pipe_config->dsc.compressed_bpp) { 1504 int div = pipe_config->dsc.compressed_bpp; 1505 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1506 1507 adjusted_mode->crtc_htotal = 1508 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1509 adjusted_mode->crtc_hsync_start = 1510 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1511 adjusted_mode->crtc_hsync_end = 1512 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1513 } 1514 1515 if (intel_dsi->dual_link) { 1516 adjusted_mode->crtc_hdisplay *= 2; 1517 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1518 adjusted_mode->crtc_hdisplay -= 1519 intel_dsi->pixel_overlap; 1520 adjusted_mode->crtc_htotal *= 2; 1521 } 1522 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1523 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1524 1525 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1526 if (intel_dsi->dual_link) { 1527 adjusted_mode->crtc_hsync_start *= 2; 1528 adjusted_mode->crtc_hsync_end *= 2; 1529 } 1530 } 1531 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1532 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1533 } 1534 1535 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1536 { 1537 struct drm_device *dev = intel_dsi->base.base.dev; 1538 struct drm_i915_private *dev_priv = to_i915(dev); 1539 enum transcoder dsi_trans; 1540 u32 val; 1541 1542 if (intel_dsi->ports == BIT(PORT_B)) 1543 dsi_trans = TRANSCODER_DSI_1; 1544 else 1545 dsi_trans = TRANSCODER_DSI_0; 1546 1547 val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 1548 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1549 } 1550 1551 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1552 struct intel_crtc_state *pipe_config) 1553 { 1554 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1555 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1556 I915_MODE_FLAG_DSI_USE_TE0; 1557 else if (intel_dsi->ports == BIT(PORT_B)) 1558 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1559 else 1560 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1561 } 1562 1563 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1564 struct intel_crtc_state *pipe_config) 1565 { 1566 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1567 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1568 1569 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1570 1571 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1572 if (intel_dsi->dual_link) 1573 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1574 1575 gen11_dsi_get_timings(encoder, pipe_config); 1576 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1577 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1578 1579 /* Get the details on which TE should be enabled */ 1580 if (is_cmd_mode(intel_dsi)) 1581 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1582 1583 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1584 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1585 } 1586 1587 static void gen11_dsi_sync_state(struct intel_encoder *encoder, 1588 const struct intel_crtc_state *crtc_state) 1589 { 1590 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1591 struct intel_crtc *intel_crtc; 1592 enum pipe pipe; 1593 1594 if (!crtc_state) 1595 return; 1596 1597 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1598 pipe = intel_crtc->pipe; 1599 1600 /* wa verify 1409054076:icl,jsl,ehl */ 1601 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && 1602 !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A)) 1603 drm_dbg_kms(&dev_priv->drm, 1604 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n", 1605 encoder->base.base.id, 1606 encoder->base.name); 1607 } 1608 1609 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1610 struct intel_crtc_state *crtc_state) 1611 { 1612 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1613 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1614 int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10; 1615 bool use_dsc; 1616 int ret; 1617 1618 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1619 if (!use_dsc) 1620 return 0; 1621 1622 if (crtc_state->pipe_bpp < 8 * 3) 1623 return -EINVAL; 1624 1625 /* FIXME: split only when necessary */ 1626 if (crtc_state->dsc.slice_count > 1) 1627 crtc_state->dsc.dsc_split = true; 1628 1629 vdsc_cfg->convert_rgb = true; 1630 1631 /* FIXME: initialize from VBT */ 1632 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1633 1634 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1635 1636 ret = intel_dsc_compute_params(crtc_state); 1637 if (ret) 1638 return ret; 1639 1640 /* DSI specific sanity checks on the common code */ 1641 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); 1642 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); 1643 drm_WARN_ON(&dev_priv->drm, 1644 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1645 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); 1646 drm_WARN_ON(&dev_priv->drm, 1647 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1648 1649 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1650 if (ret) 1651 return ret; 1652 1653 crtc_state->dsc.compression_enable = true; 1654 1655 return 0; 1656 } 1657 1658 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1659 struct intel_crtc_state *pipe_config, 1660 struct drm_connector_state *conn_state) 1661 { 1662 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1663 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 1664 base); 1665 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1666 struct drm_display_mode *adjusted_mode = 1667 &pipe_config->hw.adjusted_mode; 1668 int ret; 1669 1670 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1671 1672 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 1673 if (ret) 1674 return ret; 1675 1676 ret = intel_panel_fitting(pipe_config, conn_state); 1677 if (ret) 1678 return ret; 1679 1680 adjusted_mode->flags = 0; 1681 1682 /* Dual link goes to trancoder DSI'0' */ 1683 if (intel_dsi->ports == BIT(PORT_B)) 1684 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1685 else 1686 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1687 1688 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1689 pipe_config->pipe_bpp = 24; 1690 else 1691 pipe_config->pipe_bpp = 18; 1692 1693 pipe_config->clock_set = true; 1694 1695 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1696 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n"); 1697 1698 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1699 1700 /* 1701 * In case of TE GATE cmd mode, we 1702 * receive TE from the slave if 1703 * dual link is enabled 1704 */ 1705 if (is_cmd_mode(intel_dsi)) 1706 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1707 1708 return 0; 1709 } 1710 1711 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1712 struct intel_crtc_state *crtc_state) 1713 { 1714 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1715 1716 get_dsi_io_power_domains(i915, 1717 enc_to_intel_dsi(encoder)); 1718 } 1719 1720 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1721 enum pipe *pipe) 1722 { 1723 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1724 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1725 enum transcoder dsi_trans; 1726 intel_wakeref_t wakeref; 1727 enum port port; 1728 bool ret = false; 1729 u32 tmp; 1730 1731 wakeref = intel_display_power_get_if_enabled(dev_priv, 1732 encoder->power_domain); 1733 if (!wakeref) 1734 return false; 1735 1736 for_each_dsi_port(port, intel_dsi->ports) { 1737 dsi_trans = dsi_port_to_transcoder(port); 1738 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1739 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1740 case TRANS_DDI_EDP_INPUT_A_ON: 1741 *pipe = PIPE_A; 1742 break; 1743 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1744 *pipe = PIPE_B; 1745 break; 1746 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1747 *pipe = PIPE_C; 1748 break; 1749 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1750 *pipe = PIPE_D; 1751 break; 1752 default: 1753 drm_err(&dev_priv->drm, "Invalid PIPE input\n"); 1754 goto out; 1755 } 1756 1757 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1758 ret = tmp & PIPECONF_ENABLE; 1759 } 1760 out: 1761 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1762 return ret; 1763 } 1764 1765 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1766 struct intel_crtc_state *crtc_state) 1767 { 1768 if (crtc_state->dsc.compression_enable) { 1769 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1770 crtc_state->uapi.mode_changed = true; 1771 1772 return false; 1773 } 1774 1775 return true; 1776 } 1777 1778 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1779 { 1780 intel_encoder_destroy(encoder); 1781 } 1782 1783 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1784 .destroy = gen11_dsi_encoder_destroy, 1785 }; 1786 1787 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1788 .detect = intel_panel_detect, 1789 .late_register = intel_connector_register, 1790 .early_unregister = intel_connector_unregister, 1791 .destroy = intel_connector_destroy, 1792 .fill_modes = drm_helper_probe_single_connector_modes, 1793 .atomic_get_property = intel_digital_connector_atomic_get_property, 1794 .atomic_set_property = intel_digital_connector_atomic_set_property, 1795 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1796 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1797 }; 1798 1799 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1800 .get_modes = intel_dsi_get_modes, 1801 .mode_valid = gen11_dsi_mode_valid, 1802 .atomic_check = intel_digital_connector_atomic_check, 1803 }; 1804 1805 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1806 struct mipi_dsi_device *dsi) 1807 { 1808 return 0; 1809 } 1810 1811 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1812 struct mipi_dsi_device *dsi) 1813 { 1814 return 0; 1815 } 1816 1817 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1818 const struct mipi_dsi_msg *msg) 1819 { 1820 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1821 struct mipi_dsi_packet dsi_pkt; 1822 ssize_t ret; 1823 bool enable_lpdt = false; 1824 1825 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1826 if (ret < 0) 1827 return ret; 1828 1829 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1830 enable_lpdt = true; 1831 1832 /* only long packet contains payload */ 1833 if (mipi_dsi_packet_format_is_long(msg->type)) { 1834 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt); 1835 if (ret < 0) 1836 return ret; 1837 } 1838 1839 /* send packet header */ 1840 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt); 1841 if (ret < 0) 1842 return ret; 1843 1844 //TODO: add payload receive code if needed 1845 1846 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1847 1848 return ret; 1849 } 1850 1851 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1852 .attach = gen11_dsi_host_attach, 1853 .detach = gen11_dsi_host_detach, 1854 .transfer = gen11_dsi_host_transfer, 1855 }; 1856 1857 #define ICL_PREPARE_CNT_MAX 0x7 1858 #define ICL_CLK_ZERO_CNT_MAX 0xf 1859 #define ICL_TRAIL_CNT_MAX 0x7 1860 #define ICL_TCLK_PRE_CNT_MAX 0x3 1861 #define ICL_TCLK_POST_CNT_MAX 0x7 1862 #define ICL_HS_ZERO_CNT_MAX 0xf 1863 #define ICL_EXIT_ZERO_CNT_MAX 0x7 1864 1865 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1866 { 1867 struct drm_device *dev = intel_dsi->base.base.dev; 1868 struct drm_i915_private *dev_priv = to_i915(dev); 1869 struct intel_connector *connector = intel_dsi->attached_connector; 1870 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1871 u32 tlpx_ns; 1872 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1873 u32 ths_prepare_ns, tclk_trail_ns; 1874 u32 hs_zero_cnt; 1875 u32 tclk_pre_cnt, tclk_post_cnt; 1876 1877 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1878 1879 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1880 ths_prepare_ns = max(mipi_config->ths_prepare, 1881 mipi_config->tclk_prepare); 1882 1883 /* 1884 * prepare cnt in escape clocks 1885 * this field represents a hexadecimal value with a precision 1886 * of 1.2 – i.e. the most significant bit is the integer 1887 * and the least significant 2 bits are fraction bits. 1888 * so, the field can represent a range of 0.25 to 1.75 1889 */ 1890 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1891 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1892 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", 1893 prepare_cnt); 1894 prepare_cnt = ICL_PREPARE_CNT_MAX; 1895 } 1896 1897 /* clk zero count in escape clocks */ 1898 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1899 ths_prepare_ns, tlpx_ns); 1900 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1901 drm_dbg_kms(&dev_priv->drm, 1902 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1903 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1904 } 1905 1906 /* trail cnt in escape clocks*/ 1907 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1908 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1909 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", 1910 trail_cnt); 1911 trail_cnt = ICL_TRAIL_CNT_MAX; 1912 } 1913 1914 /* tclk pre count in escape clocks */ 1915 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1916 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1917 drm_dbg_kms(&dev_priv->drm, 1918 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1919 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1920 } 1921 1922 /* tclk post count in escape clocks */ 1923 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); 1924 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { 1925 drm_dbg_kms(&dev_priv->drm, 1926 "tclk_post_cnt out of range (%d)\n", 1927 tclk_post_cnt); 1928 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; 1929 } 1930 1931 /* hs zero cnt in escape clocks */ 1932 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1933 ths_prepare_ns, tlpx_ns); 1934 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1935 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", 1936 hs_zero_cnt); 1937 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1938 } 1939 1940 /* hs exit zero cnt in escape clocks */ 1941 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1942 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1943 drm_dbg_kms(&dev_priv->drm, 1944 "exit_zero_cnt out of range (%d)\n", 1945 exit_zero_cnt); 1946 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1947 } 1948 1949 /* clock lane dphy timings */ 1950 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1951 CLK_PREPARE(prepare_cnt) | 1952 CLK_ZERO_OVERRIDE | 1953 CLK_ZERO(clk_zero_cnt) | 1954 CLK_PRE_OVERRIDE | 1955 CLK_PRE(tclk_pre_cnt) | 1956 CLK_POST_OVERRIDE | 1957 CLK_POST(tclk_post_cnt) | 1958 CLK_TRAIL_OVERRIDE | 1959 CLK_TRAIL(trail_cnt)); 1960 1961 /* data lanes dphy timings */ 1962 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1963 HS_PREPARE(prepare_cnt) | 1964 HS_ZERO_OVERRIDE | 1965 HS_ZERO(hs_zero_cnt) | 1966 HS_TRAIL_OVERRIDE | 1967 HS_TRAIL(trail_cnt) | 1968 HS_EXIT_OVERRIDE | 1969 HS_EXIT(exit_zero_cnt)); 1970 1971 intel_dsi_log_params(intel_dsi); 1972 } 1973 1974 static void icl_dsi_add_properties(struct intel_connector *connector) 1975 { 1976 const struct drm_display_mode *fixed_mode = 1977 intel_panel_preferred_fixed_mode(connector); 1978 1979 intel_attach_scaling_mode_property(&connector->base); 1980 1981 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1982 intel_dsi_get_panel_orientation(connector), 1983 fixed_mode->hdisplay, 1984 fixed_mode->vdisplay); 1985 } 1986 1987 void icl_dsi_init(struct drm_i915_private *dev_priv) 1988 { 1989 struct intel_dsi *intel_dsi; 1990 struct intel_encoder *encoder; 1991 struct intel_connector *intel_connector; 1992 struct drm_connector *connector; 1993 enum port port; 1994 1995 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1996 return; 1997 1998 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1999 if (!intel_dsi) 2000 return; 2001 2002 intel_connector = intel_connector_alloc(); 2003 if (!intel_connector) { 2004 kfree(intel_dsi); 2005 return; 2006 } 2007 2008 encoder = &intel_dsi->base; 2009 intel_dsi->attached_connector = intel_connector; 2010 connector = &intel_connector->base; 2011 2012 /* register DSI encoder with DRM subsystem */ 2013 drm_encoder_init(&dev_priv->drm, &encoder->base, &gen11_dsi_encoder_funcs, 2014 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 2015 2016 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 2017 encoder->pre_enable = gen11_dsi_pre_enable; 2018 encoder->enable = gen11_dsi_enable; 2019 encoder->disable = gen11_dsi_disable; 2020 encoder->post_disable = gen11_dsi_post_disable; 2021 encoder->port = port; 2022 encoder->get_config = gen11_dsi_get_config; 2023 encoder->sync_state = gen11_dsi_sync_state; 2024 encoder->update_pipe = intel_backlight_update; 2025 encoder->compute_config = gen11_dsi_compute_config; 2026 encoder->get_hw_state = gen11_dsi_get_hw_state; 2027 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 2028 encoder->type = INTEL_OUTPUT_DSI; 2029 encoder->cloneable = 0; 2030 encoder->pipe_mask = ~0; 2031 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 2032 encoder->get_power_domains = gen11_dsi_get_power_domains; 2033 encoder->disable_clock = gen11_dsi_gate_clocks; 2034 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 2035 2036 /* register DSI connector with DRM subsystem */ 2037 drm_connector_init(&dev_priv->drm, connector, &gen11_dsi_connector_funcs, 2038 DRM_MODE_CONNECTOR_DSI); 2039 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 2040 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 2041 intel_connector->get_hw_state = intel_connector_get_hw_state; 2042 2043 /* attach connector to encoder */ 2044 intel_connector_attach_encoder(intel_connector, encoder); 2045 2046 intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL, NULL); 2047 2048 mutex_lock(&dev_priv->drm.mode_config.mutex); 2049 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 2050 mutex_unlock(&dev_priv->drm.mode_config.mutex); 2051 2052 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2053 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); 2054 goto err; 2055 } 2056 2057 intel_panel_init(intel_connector); 2058 2059 intel_backlight_setup(intel_connector, INVALID_PIPE); 2060 2061 if (intel_connector->panel.vbt.dsi.config->dual_link) 2062 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 2063 else 2064 intel_dsi->ports = BIT(port); 2065 2066 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) 2067 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; 2068 2069 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) 2070 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; 2071 2072 for_each_dsi_port(port, intel_dsi->ports) { 2073 struct intel_dsi_host *host; 2074 2075 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2076 if (!host) 2077 goto err; 2078 2079 intel_dsi->dsi_hosts[port] = host; 2080 } 2081 2082 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2083 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 2084 goto err; 2085 } 2086 2087 icl_dphy_param_init(intel_dsi); 2088 2089 icl_dsi_add_properties(intel_connector); 2090 return; 2091 2092 err: 2093 drm_connector_cleanup(connector); 2094 drm_encoder_cleanup(&encoder->base); 2095 kfree(intel_dsi); 2096 kfree(intel_connector); 2097 } 2098