1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/display/drm_dsc_helper.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_mipi_dsi.h> 31 32 #include "i915_reg.h" 33 #include "icl_dsi.h" 34 #include "icl_dsi_regs.h" 35 #include "intel_atomic.h" 36 #include "intel_backlight.h" 37 #include "intel_backlight_regs.h" 38 #include "intel_combo_phy.h" 39 #include "intel_combo_phy_regs.h" 40 #include "intel_connector.h" 41 #include "intel_crtc.h" 42 #include "intel_ddi.h" 43 #include "intel_de.h" 44 #include "intel_dsi.h" 45 #include "intel_dsi_vbt.h" 46 #include "intel_panel.h" 47 #include "intel_vdsc.h" 48 #include "intel_vdsc_regs.h" 49 #include "skl_scaler.h" 50 #include "skl_universal_plane.h" 51 52 static int header_credits_available(struct drm_i915_private *dev_priv, 53 enum transcoder dsi_trans) 54 { 55 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 56 >> FREE_HEADER_CREDIT_SHIFT; 57 } 58 59 static int payload_credits_available(struct drm_i915_private *dev_priv, 60 enum transcoder dsi_trans) 61 { 62 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 63 >> FREE_PLOAD_CREDIT_SHIFT; 64 } 65 66 static bool wait_for_header_credits(struct drm_i915_private *dev_priv, 67 enum transcoder dsi_trans, int hdr_credit) 68 { 69 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= 70 hdr_credit, 100)) { 71 drm_err(&dev_priv->drm, "DSI header credits not released\n"); 72 return false; 73 } 74 75 return true; 76 } 77 78 static bool wait_for_payload_credits(struct drm_i915_private *dev_priv, 79 enum transcoder dsi_trans, int payld_credit) 80 { 81 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= 82 payld_credit, 100)) { 83 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); 84 return false; 85 } 86 87 return true; 88 } 89 90 static enum transcoder dsi_port_to_transcoder(enum port port) 91 { 92 if (port == PORT_A) 93 return TRANSCODER_DSI_0; 94 else 95 return TRANSCODER_DSI_1; 96 } 97 98 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 99 { 100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 101 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 102 struct mipi_dsi_device *dsi; 103 enum port port; 104 enum transcoder dsi_trans; 105 int ret; 106 107 /* wait for header/payload credits to be released */ 108 for_each_dsi_port(port, intel_dsi->ports) { 109 dsi_trans = dsi_port_to_transcoder(port); 110 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 111 wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT); 112 } 113 114 /* send nop DCS command */ 115 for_each_dsi_port(port, intel_dsi->ports) { 116 dsi = intel_dsi->dsi_hosts[port]->device; 117 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 118 dsi->channel = 0; 119 ret = mipi_dsi_dcs_nop(dsi); 120 if (ret < 0) 121 drm_err(&dev_priv->drm, 122 "error sending DCS NOP command\n"); 123 } 124 125 /* wait for header credits to be released */ 126 for_each_dsi_port(port, intel_dsi->ports) { 127 dsi_trans = dsi_port_to_transcoder(port); 128 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 129 } 130 131 /* wait for LP TX in progress bit to be cleared */ 132 for_each_dsi_port(port, intel_dsi->ports) { 133 dsi_trans = dsi_port_to_transcoder(port); 134 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 135 LPTX_IN_PROGRESS), 20)) 136 drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); 137 } 138 } 139 140 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 141 const struct mipi_dsi_packet *packet) 142 { 143 struct intel_dsi *intel_dsi = host->intel_dsi; 144 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 145 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 146 const u8 *data = packet->payload; 147 u32 len = packet->payload_length; 148 int i, j; 149 150 /* payload queue can accept *256 bytes*, check limit */ 151 if (len > MAX_PLOAD_CREDIT * 4) { 152 drm_err(&i915->drm, "payload size exceeds max queue limit\n"); 153 return -EINVAL; 154 } 155 156 for (i = 0; i < len; i += 4) { 157 u32 tmp = 0; 158 159 if (!wait_for_payload_credits(i915, dsi_trans, 1)) 160 return -EBUSY; 161 162 for (j = 0; j < min_t(u32, len - i, 4); j++) 163 tmp |= *data++ << 8 * j; 164 165 intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp); 166 } 167 168 return 0; 169 } 170 171 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 172 const struct mipi_dsi_packet *packet, 173 bool enable_lpdt) 174 { 175 struct intel_dsi *intel_dsi = host->intel_dsi; 176 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 177 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 178 u32 tmp; 179 180 if (!wait_for_header_credits(dev_priv, dsi_trans, 1)) 181 return -EBUSY; 182 183 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); 184 185 if (packet->payload) 186 tmp |= PAYLOAD_PRESENT; 187 else 188 tmp &= ~PAYLOAD_PRESENT; 189 190 tmp &= ~VBLANK_FENCE; 191 192 if (enable_lpdt) 193 tmp |= LP_DATA_TRANSFER; 194 else 195 tmp &= ~LP_DATA_TRANSFER; 196 197 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 198 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); 199 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); 200 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); 201 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); 202 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); 203 204 return 0; 205 } 206 207 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 208 { 209 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 210 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 211 u32 mode_flags; 212 enum port port; 213 214 mode_flags = crtc_state->mode_flags; 215 216 /* 217 * case 1 also covers dual link 218 * In case of dual link, frame update should be set on 219 * DSI_0 220 */ 221 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 222 port = PORT_A; 223 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 224 port = PORT_B; 225 else 226 return; 227 228 intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port), 0, DSI_FRAME_UPDATE_REQUEST); 229 } 230 231 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 232 { 233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 234 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 235 enum phy phy; 236 u32 tmp, mask, val; 237 int lane; 238 239 for_each_dsi_phy(phy, intel_dsi->phys) { 240 /* 241 * Program voltage swing and pre-emphasis level values as per 242 * table in BSPEC under DDI buffer programing 243 */ 244 mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK; 245 val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE | 246 RTERM_SELECT(0x6); 247 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 248 tmp &= ~mask; 249 tmp |= val; 250 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 251 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), mask, val); 252 253 mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 254 RCOMP_SCALAR_MASK; 255 val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) | 256 RCOMP_SCALAR(0x98); 257 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 258 tmp &= ~mask; 259 tmp |= val; 260 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 261 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), mask, val); 262 263 mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 264 CURSOR_COEFF_MASK; 265 val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) | 266 CURSOR_COEFF(0x3f); 267 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), mask, val); 268 269 /* Bspec: must not use GRP register for write */ 270 for (lane = 0; lane <= 3; lane++) 271 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy), 272 mask, val); 273 } 274 } 275 276 static void configure_dual_link_mode(struct intel_encoder *encoder, 277 const struct intel_crtc_state *pipe_config) 278 { 279 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 280 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 281 i915_reg_t dss_ctl1_reg, dss_ctl2_reg; 282 u32 dss_ctl1; 283 284 /* FIXME: Move all DSS handling to intel_vdsc.c */ 285 if (DISPLAY_VER(dev_priv) >= 12) { 286 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 287 288 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); 289 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); 290 } else { 291 dss_ctl1_reg = DSS_CTL1; 292 dss_ctl2_reg = DSS_CTL2; 293 } 294 295 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg); 296 dss_ctl1 |= SPLITTER_ENABLE; 297 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 298 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 299 300 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 301 const struct drm_display_mode *adjusted_mode = 302 &pipe_config->hw.adjusted_mode; 303 u16 hactive = adjusted_mode->crtc_hdisplay; 304 u16 dl_buffer_depth; 305 306 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 307 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 308 309 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 310 drm_err(&dev_priv->drm, 311 "DL buffer depth exceed max value\n"); 312 313 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 314 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 315 intel_de_rmw(dev_priv, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK, 316 RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth)); 317 } else { 318 /* Interleave */ 319 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 320 } 321 322 intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1); 323 } 324 325 /* aka DSI 8X clock */ 326 static int afe_clk(struct intel_encoder *encoder, 327 const struct intel_crtc_state *crtc_state) 328 { 329 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 330 int bpp; 331 332 if (crtc_state->dsc.compression_enable) 333 bpp = crtc_state->dsc.compressed_bpp; 334 else 335 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 336 337 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 338 } 339 340 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 341 const struct intel_crtc_state *crtc_state) 342 { 343 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 344 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 345 enum port port; 346 int afe_clk_khz; 347 int theo_word_clk, act_word_clk; 348 u32 esc_clk_div_m, esc_clk_div_m_phy; 349 350 afe_clk_khz = afe_clk(encoder, crtc_state); 351 352 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 353 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 354 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 355 esc_clk_div_m = act_word_clk * 8; 356 esc_clk_div_m_phy = (act_word_clk - 1) / 2; 357 } else { 358 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 359 } 360 361 for_each_dsi_port(port, intel_dsi->ports) { 362 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), 363 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 364 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); 365 } 366 367 for_each_dsi_port(port, intel_dsi->ports) { 368 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port), 369 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 370 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); 371 } 372 373 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 374 for_each_dsi_port(port, intel_dsi->ports) { 375 intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8), 376 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); 377 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8)); 378 } 379 } 380 } 381 382 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, 383 struct intel_dsi *intel_dsi) 384 { 385 enum port port; 386 387 for_each_dsi_port(port, intel_dsi->ports) { 388 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); 389 intel_dsi->io_wakeref[port] = 390 intel_display_power_get(dev_priv, 391 port == PORT_A ? 392 POWER_DOMAIN_PORT_DDI_IO_A : 393 POWER_DOMAIN_PORT_DDI_IO_B); 394 } 395 } 396 397 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 398 { 399 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 400 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 401 enum port port; 402 403 for_each_dsi_port(port, intel_dsi->ports) 404 intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port), 405 0, COMBO_PHY_MODE_DSI); 406 407 get_dsi_io_power_domains(dev_priv, intel_dsi); 408 } 409 410 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 411 { 412 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 413 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 414 enum phy phy; 415 416 for_each_dsi_phy(phy, intel_dsi->phys) 417 intel_combo_phy_power_up_lanes(dev_priv, phy, true, 418 intel_dsi->lane_count, false); 419 } 420 421 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 422 { 423 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 424 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 425 enum phy phy; 426 u32 tmp; 427 int lane; 428 429 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 430 for_each_dsi_phy(phy, intel_dsi->phys) { 431 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), LOADGEN_SELECT, 0); 432 for (lane = 0; lane <= 3; lane++) 433 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy), 434 LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0); 435 } 436 437 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 438 for_each_dsi_phy(phy, intel_dsi->phys) { 439 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), 440 FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5)); 441 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 442 tmp &= ~FRC_LATENCY_OPTIM_MASK; 443 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 444 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 445 446 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 447 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) || 448 (DISPLAY_VER(dev_priv) >= 12)) { 449 intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), 450 LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0)); 451 452 tmp = intel_de_read(dev_priv, 453 ICL_PORT_PCS_DW1_LN(0, phy)); 454 tmp &= ~LATENCY_OPTIM_MASK; 455 tmp |= LATENCY_OPTIM_VAL(0x1); 456 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), 457 tmp); 458 } 459 } 460 461 } 462 463 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 464 { 465 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 466 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 467 u32 tmp; 468 enum phy phy; 469 470 /* clear common keeper enable bit */ 471 for_each_dsi_phy(phy, intel_dsi->phys) { 472 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 473 tmp &= ~COMMON_KEEPER_EN; 474 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp); 475 intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0); 476 } 477 478 /* 479 * Set SUS Clock Config bitfield to 11b 480 * Note: loadgen select program is done 481 * as part of lane phy sequence configuration 482 */ 483 for_each_dsi_phy(phy, intel_dsi->phys) 484 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 0, SUS_CLOCK_CONFIG); 485 486 /* Clear training enable to change swing values */ 487 for_each_dsi_phy(phy, intel_dsi->phys) { 488 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 489 tmp &= ~TX_TRAINING_EN; 490 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 491 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0); 492 } 493 494 /* Program swing and de-emphasis */ 495 dsi_program_swing_and_deemphasis(encoder); 496 497 /* Set training enable to trigger update */ 498 for_each_dsi_phy(phy, intel_dsi->phys) { 499 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 500 tmp |= TX_TRAINING_EN; 501 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 502 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN); 503 } 504 } 505 506 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 507 { 508 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 509 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 510 enum port port; 511 512 for_each_dsi_port(port, intel_dsi->ports) { 513 intel_de_rmw(dev_priv, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE); 514 515 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 516 DDI_BUF_IS_IDLE), 517 500)) 518 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", 519 port_name(port)); 520 } 521 } 522 523 static void 524 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 525 const struct intel_crtc_state *crtc_state) 526 { 527 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 528 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 529 enum port port; 530 enum phy phy; 531 532 /* Program DPHY clock lanes timings */ 533 for_each_dsi_port(port, intel_dsi->ports) 534 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port), 535 intel_dsi->dphy_reg); 536 537 /* Program DPHY data lanes timings */ 538 for_each_dsi_port(port, intel_dsi->ports) 539 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port), 540 intel_dsi->dphy_data_lane_reg); 541 542 /* 543 * If DSI link operating at or below an 800 MHz, 544 * TA_SURE should be override and programmed to 545 * a value '0' inside TA_PARAM_REGISTERS otherwise 546 * leave all fields at HW default values. 547 */ 548 if (DISPLAY_VER(dev_priv) == 11) { 549 if (afe_clk(encoder, crtc_state) <= 800000) { 550 for_each_dsi_port(port, intel_dsi->ports) 551 intel_de_rmw(dev_priv, DPHY_TA_TIMING_PARAM(port), 552 TA_SURE_MASK, 553 TA_SURE_OVERRIDE | TA_SURE(0)); 554 } 555 } 556 557 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 558 for_each_dsi_phy(phy, intel_dsi->phys) 559 intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy), 560 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP); 561 } 562 } 563 564 static void 565 gen11_dsi_setup_timings(struct intel_encoder *encoder, 566 const struct intel_crtc_state *crtc_state) 567 { 568 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 569 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 570 enum port port; 571 572 /* Program T-INIT master registers */ 573 for_each_dsi_port(port, intel_dsi->ports) 574 intel_de_rmw(dev_priv, ICL_DSI_T_INIT_MASTER(port), 575 DSI_T_INIT_MASTER_MASK, intel_dsi->init_count); 576 577 /* shadow register inside display core */ 578 for_each_dsi_port(port, intel_dsi->ports) 579 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port), 580 intel_dsi->dphy_reg); 581 582 /* shadow register inside display core */ 583 for_each_dsi_port(port, intel_dsi->ports) 584 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port), 585 intel_dsi->dphy_data_lane_reg); 586 587 /* shadow register inside display core */ 588 if (DISPLAY_VER(dev_priv) == 11) { 589 if (afe_clk(encoder, crtc_state) <= 800000) { 590 for_each_dsi_port(port, intel_dsi->ports) { 591 intel_de_rmw(dev_priv, DSI_TA_TIMING_PARAM(port), 592 TA_SURE_MASK, 593 TA_SURE_OVERRIDE | TA_SURE(0)); 594 } 595 } 596 } 597 } 598 599 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 600 { 601 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 602 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 603 u32 tmp; 604 enum phy phy; 605 606 mutex_lock(&dev_priv->display.dpll.lock); 607 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 608 for_each_dsi_phy(phy, intel_dsi->phys) 609 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 610 611 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 612 mutex_unlock(&dev_priv->display.dpll.lock); 613 } 614 615 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 616 { 617 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 618 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 619 u32 tmp; 620 enum phy phy; 621 622 mutex_lock(&dev_priv->display.dpll.lock); 623 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 624 for_each_dsi_phy(phy, intel_dsi->phys) 625 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 626 627 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 628 mutex_unlock(&dev_priv->display.dpll.lock); 629 } 630 631 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 632 { 633 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 634 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 635 bool clock_enabled = false; 636 enum phy phy; 637 u32 tmp; 638 639 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 640 641 for_each_dsi_phy(phy, intel_dsi->phys) { 642 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 643 clock_enabled = true; 644 } 645 646 return clock_enabled; 647 } 648 649 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 650 const struct intel_crtc_state *crtc_state) 651 { 652 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 653 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 654 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 655 enum phy phy; 656 u32 val; 657 658 mutex_lock(&dev_priv->display.dpll.lock); 659 660 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 661 for_each_dsi_phy(phy, intel_dsi->phys) { 662 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 663 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 664 } 665 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 666 667 for_each_dsi_phy(phy, intel_dsi->phys) { 668 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 669 } 670 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 671 672 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 673 674 mutex_unlock(&dev_priv->display.dpll.lock); 675 } 676 677 static void 678 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 679 const struct intel_crtc_state *pipe_config) 680 { 681 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 682 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 683 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 684 enum pipe pipe = crtc->pipe; 685 u32 tmp; 686 enum port port; 687 enum transcoder dsi_trans; 688 689 for_each_dsi_port(port, intel_dsi->ports) { 690 dsi_trans = dsi_port_to_transcoder(port); 691 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 692 693 if (intel_dsi->eotp_pkt) 694 tmp &= ~EOTP_DISABLED; 695 else 696 tmp |= EOTP_DISABLED; 697 698 /* enable link calibration if freq > 1.5Gbps */ 699 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 700 tmp &= ~LINK_CALIBRATION_MASK; 701 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 702 } 703 704 /* configure continuous clock */ 705 tmp &= ~CONTINUOUS_CLK_MASK; 706 if (intel_dsi->clock_stop) 707 tmp |= CLK_ENTER_LP_AFTER_DATA; 708 else 709 tmp |= CLK_HS_CONTINUOUS; 710 711 /* configure buffer threshold limit to minimum */ 712 tmp &= ~PIX_BUF_THRESHOLD_MASK; 713 tmp |= PIX_BUF_THRESHOLD_1_4; 714 715 /* set virtual channel to '0' */ 716 tmp &= ~PIX_VIRT_CHAN_MASK; 717 tmp |= PIX_VIRT_CHAN(0); 718 719 /* program BGR transmission */ 720 if (intel_dsi->bgr_enabled) 721 tmp |= BGR_TRANSMISSION; 722 723 /* select pixel format */ 724 tmp &= ~PIX_FMT_MASK; 725 if (pipe_config->dsc.compression_enable) { 726 tmp |= PIX_FMT_COMPRESSED; 727 } else { 728 switch (intel_dsi->pixel_format) { 729 default: 730 MISSING_CASE(intel_dsi->pixel_format); 731 fallthrough; 732 case MIPI_DSI_FMT_RGB565: 733 tmp |= PIX_FMT_RGB565; 734 break; 735 case MIPI_DSI_FMT_RGB666_PACKED: 736 tmp |= PIX_FMT_RGB666_PACKED; 737 break; 738 case MIPI_DSI_FMT_RGB666: 739 tmp |= PIX_FMT_RGB666_LOOSE; 740 break; 741 case MIPI_DSI_FMT_RGB888: 742 tmp |= PIX_FMT_RGB888; 743 break; 744 } 745 } 746 747 if (DISPLAY_VER(dev_priv) >= 12) { 748 if (is_vid_mode(intel_dsi)) 749 tmp |= BLANKING_PACKET_ENABLE; 750 } 751 752 /* program DSI operation mode */ 753 if (is_vid_mode(intel_dsi)) { 754 tmp &= ~OP_MODE_MASK; 755 switch (intel_dsi->video_mode) { 756 default: 757 MISSING_CASE(intel_dsi->video_mode); 758 fallthrough; 759 case NON_BURST_SYNC_EVENTS: 760 tmp |= VIDEO_MODE_SYNC_EVENT; 761 break; 762 case NON_BURST_SYNC_PULSE: 763 tmp |= VIDEO_MODE_SYNC_PULSE; 764 break; 765 } 766 } else { 767 /* 768 * FIXME: Retrieve this info from VBT. 769 * As per the spec when dsi transcoder is operating 770 * in TE GATE mode, TE comes from GPIO 771 * which is UTIL PIN for DSI 0. 772 * Also this GPIO would not be used for other 773 * purposes is an assumption. 774 */ 775 tmp &= ~OP_MODE_MASK; 776 tmp |= CMD_MODE_TE_GATE; 777 tmp |= TE_SOURCE_GPIO; 778 } 779 780 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 781 } 782 783 /* enable port sync mode if dual link */ 784 if (intel_dsi->dual_link) { 785 for_each_dsi_port(port, intel_dsi->ports) { 786 dsi_trans = dsi_port_to_transcoder(port); 787 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL2(dsi_trans), 788 0, PORT_SYNC_MODE_ENABLE); 789 } 790 791 /* configure stream splitting */ 792 configure_dual_link_mode(encoder, pipe_config); 793 } 794 795 for_each_dsi_port(port, intel_dsi->ports) { 796 dsi_trans = dsi_port_to_transcoder(port); 797 798 /* select data lane width */ 799 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 800 tmp &= ~DDI_PORT_WIDTH_MASK; 801 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); 802 803 /* select input pipe */ 804 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 805 switch (pipe) { 806 default: 807 MISSING_CASE(pipe); 808 fallthrough; 809 case PIPE_A: 810 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 811 break; 812 case PIPE_B: 813 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 814 break; 815 case PIPE_C: 816 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 817 break; 818 case PIPE_D: 819 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 820 break; 821 } 822 823 /* enable DDI buffer */ 824 tmp |= TRANS_DDI_FUNC_ENABLE; 825 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 826 } 827 828 /* wait for link ready */ 829 for_each_dsi_port(port, intel_dsi->ports) { 830 dsi_trans = dsi_port_to_transcoder(port); 831 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) & 832 LINK_READY), 2500)) 833 drm_err(&dev_priv->drm, "DSI link not ready\n"); 834 } 835 } 836 837 static void 838 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 839 const struct intel_crtc_state *crtc_state) 840 { 841 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 842 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 843 const struct drm_display_mode *adjusted_mode = 844 &crtc_state->hw.adjusted_mode; 845 enum port port; 846 enum transcoder dsi_trans; 847 /* horizontal timings */ 848 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 849 u16 hback_porch; 850 /* vertical timings */ 851 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 852 int mul = 1, div = 1; 853 854 /* 855 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 856 * for slower link speed if DSC is enabled. 857 * 858 * The compression frequency ratio is the ratio between compressed and 859 * non-compressed link speeds, and simplifies down to the ratio between 860 * compressed and non-compressed bpp. 861 */ 862 if (crtc_state->dsc.compression_enable) { 863 mul = crtc_state->dsc.compressed_bpp; 864 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 865 } 866 867 hactive = adjusted_mode->crtc_hdisplay; 868 869 if (is_vid_mode(intel_dsi)) 870 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 871 else 872 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 873 874 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 875 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 876 hsync_size = hsync_end - hsync_start; 877 hback_porch = (adjusted_mode->crtc_htotal - 878 adjusted_mode->crtc_hsync_end); 879 vactive = adjusted_mode->crtc_vdisplay; 880 881 if (is_vid_mode(intel_dsi)) { 882 vtotal = adjusted_mode->crtc_vtotal; 883 } else { 884 int bpp, line_time_us, byte_clk_period_ns; 885 886 if (crtc_state->dsc.compression_enable) 887 bpp = crtc_state->dsc.compressed_bpp; 888 else 889 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 890 891 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 892 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 893 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 894 } 895 vsync_start = adjusted_mode->crtc_vsync_start; 896 vsync_end = adjusted_mode->crtc_vsync_end; 897 vsync_shift = hsync_start - htotal / 2; 898 899 if (intel_dsi->dual_link) { 900 hactive /= 2; 901 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 902 hactive += intel_dsi->pixel_overlap; 903 htotal /= 2; 904 } 905 906 /* minimum hactive as per bspec: 256 pixels */ 907 if (adjusted_mode->crtc_hdisplay < 256) 908 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); 909 910 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 911 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 912 drm_err(&dev_priv->drm, 913 "hactive pixels are not multiple of 4\n"); 914 915 /* program TRANS_HTOTAL register */ 916 for_each_dsi_port(port, intel_dsi->ports) { 917 dsi_trans = dsi_port_to_transcoder(port); 918 intel_de_write(dev_priv, TRANS_HTOTAL(dsi_trans), 919 HACTIVE(hactive - 1) | HTOTAL(htotal - 1)); 920 } 921 922 /* TRANS_HSYNC register to be programmed only for video mode */ 923 if (is_vid_mode(intel_dsi)) { 924 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { 925 /* BSPEC: hsync size should be atleast 16 pixels */ 926 if (hsync_size < 16) 927 drm_err(&dev_priv->drm, 928 "hsync size < 16 pixels\n"); 929 } 930 931 if (hback_porch < 16) 932 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); 933 934 if (intel_dsi->dual_link) { 935 hsync_start /= 2; 936 hsync_end /= 2; 937 } 938 939 for_each_dsi_port(port, intel_dsi->ports) { 940 dsi_trans = dsi_port_to_transcoder(port); 941 intel_de_write(dev_priv, TRANS_HSYNC(dsi_trans), 942 HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1)); 943 } 944 } 945 946 /* program TRANS_VTOTAL register */ 947 for_each_dsi_port(port, intel_dsi->ports) { 948 dsi_trans = dsi_port_to_transcoder(port); 949 /* 950 * FIXME: Programing this by assuming progressive mode, since 951 * non-interlaced info from VBT is not saved inside 952 * struct drm_display_mode. 953 * For interlace mode: program required pixel minus 2 954 */ 955 intel_de_write(dev_priv, TRANS_VTOTAL(dsi_trans), 956 VACTIVE(vactive - 1) | VTOTAL(vtotal - 1)); 957 } 958 959 if (vsync_end < vsync_start || vsync_end > vtotal) 960 drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); 961 962 if (vsync_start < vactive) 963 drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); 964 965 /* program TRANS_VSYNC register for video mode only */ 966 if (is_vid_mode(intel_dsi)) { 967 for_each_dsi_port(port, intel_dsi->ports) { 968 dsi_trans = dsi_port_to_transcoder(port); 969 intel_de_write(dev_priv, TRANS_VSYNC(dsi_trans), 970 VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1)); 971 } 972 } 973 974 /* 975 * FIXME: It has to be programmed only for video modes and interlaced 976 * modes. Put the check condition here once interlaced 977 * info available as described above. 978 * program TRANS_VSYNCSHIFT register 979 */ 980 if (is_vid_mode(intel_dsi)) { 981 for_each_dsi_port(port, intel_dsi->ports) { 982 dsi_trans = dsi_port_to_transcoder(port); 983 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(dsi_trans), 984 vsync_shift); 985 } 986 } 987 988 /* 989 * program TRANS_VBLANK register, should be same as vtotal programmed 990 * 991 * FIXME get rid of these local hacks and do it right, 992 * this will not handle eg. delayed vblank correctly. 993 */ 994 if (DISPLAY_VER(dev_priv) >= 12) { 995 for_each_dsi_port(port, intel_dsi->ports) { 996 dsi_trans = dsi_port_to_transcoder(port); 997 intel_de_write(dev_priv, TRANS_VBLANK(dsi_trans), 998 VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1)); 999 } 1000 } 1001 } 1002 1003 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1004 { 1005 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1006 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1007 enum port port; 1008 enum transcoder dsi_trans; 1009 1010 for_each_dsi_port(port, intel_dsi->ports) { 1011 dsi_trans = dsi_port_to_transcoder(port); 1012 intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), 0, TRANSCONF_ENABLE); 1013 1014 /* wait for transcoder to be enabled */ 1015 if (intel_de_wait_for_set(dev_priv, TRANSCONF(dsi_trans), 1016 TRANSCONF_STATE_ENABLE, 10)) 1017 drm_err(&dev_priv->drm, 1018 "DSI transcoder not enabled\n"); 1019 } 1020 } 1021 1022 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1023 const struct intel_crtc_state *crtc_state) 1024 { 1025 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1026 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1027 enum port port; 1028 enum transcoder dsi_trans; 1029 u32 hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1030 1031 /* 1032 * escape clock count calculation: 1033 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1034 * UI (nsec) = (10^6)/Bitrate 1035 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1036 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1037 */ 1038 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1039 mul = 8 * 1000000; 1040 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1041 divisor); 1042 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1043 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1044 1045 for_each_dsi_port(port, intel_dsi->ports) { 1046 dsi_trans = dsi_port_to_transcoder(port); 1047 1048 /* program hst_tx_timeout */ 1049 intel_de_rmw(dev_priv, DSI_HSTX_TO(dsi_trans), 1050 HSTX_TIMEOUT_VALUE_MASK, 1051 HSTX_TIMEOUT_VALUE(hs_tx_timeout)); 1052 1053 /* FIXME: DSI_CALIB_TO */ 1054 1055 /* program lp_rx_host timeout */ 1056 intel_de_rmw(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), 1057 LPRX_TIMEOUT_VALUE_MASK, 1058 LPRX_TIMEOUT_VALUE(lp_rx_timeout)); 1059 1060 /* FIXME: DSI_PWAIT_TO */ 1061 1062 /* program turn around timeout */ 1063 intel_de_rmw(dev_priv, DSI_TA_TO(dsi_trans), 1064 TA_TIMEOUT_VALUE_MASK, 1065 TA_TIMEOUT_VALUE(ta_timeout)); 1066 } 1067 } 1068 1069 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1070 bool enable) 1071 { 1072 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1073 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1074 u32 tmp; 1075 1076 /* 1077 * used as TE i/p for DSI0, 1078 * for dual link/DSI1 TE is from slave DSI1 1079 * through GPIO. 1080 */ 1081 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1082 return; 1083 1084 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL); 1085 1086 if (enable) { 1087 tmp |= UTIL_PIN_DIRECTION_INPUT; 1088 tmp |= UTIL_PIN_ENABLE; 1089 } else { 1090 tmp &= ~UTIL_PIN_ENABLE; 1091 } 1092 intel_de_write(dev_priv, UTIL_PIN_CTL, tmp); 1093 } 1094 1095 static void 1096 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1097 const struct intel_crtc_state *crtc_state) 1098 { 1099 /* step 4a: power up all lanes of the DDI used by DSI */ 1100 gen11_dsi_power_up_lanes(encoder); 1101 1102 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1103 gen11_dsi_config_phy_lanes_sequence(encoder); 1104 1105 /* step 4c: configure voltage swing and skew */ 1106 gen11_dsi_voltage_swing_program_seq(encoder); 1107 1108 /* setup D-PHY timings */ 1109 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1110 1111 /* enable DDI buffer */ 1112 gen11_dsi_enable_ddi_buffer(encoder); 1113 1114 gen11_dsi_gate_clocks(encoder); 1115 1116 gen11_dsi_setup_timings(encoder, crtc_state); 1117 1118 /* Since transcoder is configured to take events from GPIO */ 1119 gen11_dsi_config_util_pin(encoder, true); 1120 1121 /* step 4h: setup DSI protocol timeouts */ 1122 gen11_dsi_setup_timeouts(encoder, crtc_state); 1123 1124 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1125 gen11_dsi_configure_transcoder(encoder, crtc_state); 1126 } 1127 1128 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1129 { 1130 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1131 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1132 struct mipi_dsi_device *dsi; 1133 enum port port; 1134 enum transcoder dsi_trans; 1135 u32 tmp; 1136 int ret; 1137 1138 /* set maximum return packet size */ 1139 for_each_dsi_port(port, intel_dsi->ports) { 1140 dsi_trans = dsi_port_to_transcoder(port); 1141 1142 /* 1143 * FIXME: This uses the number of DW's currently in the payload 1144 * receive queue. This is probably not what we want here. 1145 */ 1146 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans)); 1147 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1148 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1149 tmp = tmp * 4; 1150 dsi = intel_dsi->dsi_hosts[port]->device; 1151 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1152 if (ret < 0) 1153 drm_err(&dev_priv->drm, 1154 "error setting max return pkt size%d\n", tmp); 1155 } 1156 1157 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1158 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1159 1160 /* ensure all panel commands dispatched before enabling transcoder */ 1161 wait_for_cmds_dispatched_to_panel(encoder); 1162 } 1163 1164 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1165 struct intel_encoder *encoder, 1166 const struct intel_crtc_state *crtc_state, 1167 const struct drm_connector_state *conn_state) 1168 { 1169 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1170 1171 intel_dsi_wait_panel_power_cycle(intel_dsi); 1172 1173 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1174 msleep(intel_dsi->panel_on_delay); 1175 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1176 1177 /* step2: enable IO power */ 1178 gen11_dsi_enable_io_power(encoder); 1179 1180 /* step3: enable DSI PLL */ 1181 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1182 } 1183 1184 static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1185 struct intel_encoder *encoder, 1186 const struct intel_crtc_state *pipe_config, 1187 const struct drm_connector_state *conn_state) 1188 { 1189 /* step3b */ 1190 gen11_dsi_map_pll(encoder, pipe_config); 1191 1192 /* step4: enable DSI port and DPHY */ 1193 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1194 1195 /* step5: program and powerup panel */ 1196 gen11_dsi_powerup_panel(encoder); 1197 1198 intel_dsc_dsi_pps_write(encoder, pipe_config); 1199 1200 /* step6c: configure transcoder timings */ 1201 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1202 } 1203 1204 /* 1205 * Wa_1409054076:icl,jsl,ehl 1206 * When pipe A is disabled and MIPI DSI is enabled on pipe B, 1207 * the AMT KVMR feature will incorrectly see pipe A as enabled. 1208 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave 1209 * it set while DSI is enabled on pipe B 1210 */ 1211 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, 1212 enum pipe pipe, bool enable) 1213 { 1214 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1215 1216 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) 1217 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1218 IGNORE_KVMR_PIPE_A, 1219 enable ? IGNORE_KVMR_PIPE_A : 0); 1220 } 1221 1222 /* 1223 * Wa_16012360555:adl-p 1224 * SW will have to program the "LP to HS Wakeup Guardband" 1225 * to account for the repeaters on the HS Request/Ready 1226 * PPI signaling between the Display engine and the DPHY. 1227 */ 1228 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) 1229 { 1230 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1231 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1232 enum port port; 1233 1234 if (DISPLAY_VER(i915) == 13) { 1235 for_each_dsi_port(port, intel_dsi->ports) 1236 intel_de_rmw(i915, TGL_DSI_CHKN_REG(port), 1237 TGL_DSI_CHKN_LSHS_GB_MASK, 1238 TGL_DSI_CHKN_LSHS_GB(4)); 1239 } 1240 } 1241 1242 static void gen11_dsi_enable(struct intel_atomic_state *state, 1243 struct intel_encoder *encoder, 1244 const struct intel_crtc_state *crtc_state, 1245 const struct drm_connector_state *conn_state) 1246 { 1247 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1248 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1249 1250 /* Wa_1409054076:icl,jsl,ehl */ 1251 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); 1252 1253 /* Wa_16012360555:adl-p */ 1254 adlp_set_lp_hs_wakeup_gb(encoder); 1255 1256 /* step6d: enable dsi transcoder */ 1257 gen11_dsi_enable_transcoder(encoder); 1258 1259 /* step7: enable backlight */ 1260 intel_backlight_enable(crtc_state, conn_state); 1261 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1262 1263 intel_crtc_vblank_on(crtc_state); 1264 } 1265 1266 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1267 { 1268 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1269 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1270 enum port port; 1271 enum transcoder dsi_trans; 1272 1273 for_each_dsi_port(port, intel_dsi->ports) { 1274 dsi_trans = dsi_port_to_transcoder(port); 1275 1276 /* disable transcoder */ 1277 intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), TRANSCONF_ENABLE, 0); 1278 1279 /* wait for transcoder to be disabled */ 1280 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dsi_trans), 1281 TRANSCONF_STATE_ENABLE, 50)) 1282 drm_err(&dev_priv->drm, 1283 "DSI trancoder not disabled\n"); 1284 } 1285 } 1286 1287 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1288 { 1289 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1290 1291 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1292 1293 /* ensure cmds dispatched to panel */ 1294 wait_for_cmds_dispatched_to_panel(encoder); 1295 } 1296 1297 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1298 { 1299 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1300 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1301 enum port port; 1302 enum transcoder dsi_trans; 1303 u32 tmp; 1304 1305 /* disable periodic update mode */ 1306 if (is_cmd_mode(intel_dsi)) { 1307 for_each_dsi_port(port, intel_dsi->ports) 1308 intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port), 1309 DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0); 1310 } 1311 1312 /* put dsi link in ULPS */ 1313 for_each_dsi_port(port, intel_dsi->ports) { 1314 dsi_trans = dsi_port_to_transcoder(port); 1315 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)); 1316 tmp |= LINK_ENTER_ULPS; 1317 tmp &= ~LINK_ULPS_TYPE_LP11; 1318 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp); 1319 1320 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 1321 LINK_IN_ULPS), 1322 10)) 1323 drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); 1324 } 1325 1326 /* disable ddi function */ 1327 for_each_dsi_port(port, intel_dsi->ports) { 1328 dsi_trans = dsi_port_to_transcoder(port); 1329 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), 1330 TRANS_DDI_FUNC_ENABLE, 0); 1331 } 1332 1333 /* disable port sync mode if dual link */ 1334 if (intel_dsi->dual_link) { 1335 for_each_dsi_port(port, intel_dsi->ports) { 1336 dsi_trans = dsi_port_to_transcoder(port); 1337 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL2(dsi_trans), 1338 PORT_SYNC_MODE_ENABLE, 0); 1339 } 1340 } 1341 } 1342 1343 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1344 { 1345 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1346 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1347 enum port port; 1348 1349 gen11_dsi_ungate_clocks(encoder); 1350 for_each_dsi_port(port, intel_dsi->ports) { 1351 intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 1352 1353 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1354 DDI_BUF_IS_IDLE), 1355 8)) 1356 drm_err(&dev_priv->drm, 1357 "DDI port:%c buffer not idle\n", 1358 port_name(port)); 1359 } 1360 gen11_dsi_gate_clocks(encoder); 1361 } 1362 1363 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1364 { 1365 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1366 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1367 enum port port; 1368 1369 for_each_dsi_port(port, intel_dsi->ports) { 1370 intel_wakeref_t wakeref; 1371 1372 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1373 intel_display_power_put(dev_priv, 1374 port == PORT_A ? 1375 POWER_DOMAIN_PORT_DDI_IO_A : 1376 POWER_DOMAIN_PORT_DDI_IO_B, 1377 wakeref); 1378 } 1379 1380 /* set mode to DDI */ 1381 for_each_dsi_port(port, intel_dsi->ports) 1382 intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port), 1383 COMBO_PHY_MODE_DSI, 0); 1384 } 1385 1386 static void gen11_dsi_disable(struct intel_atomic_state *state, 1387 struct intel_encoder *encoder, 1388 const struct intel_crtc_state *old_crtc_state, 1389 const struct drm_connector_state *old_conn_state) 1390 { 1391 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1392 1393 /* step1: turn off backlight */ 1394 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1395 intel_backlight_disable(old_conn_state); 1396 } 1397 1398 static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1399 struct intel_encoder *encoder, 1400 const struct intel_crtc_state *old_crtc_state, 1401 const struct drm_connector_state *old_conn_state) 1402 { 1403 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1404 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1405 1406 intel_crtc_vblank_off(old_crtc_state); 1407 1408 /* step2d,e: disable transcoder and wait */ 1409 gen11_dsi_disable_transcoder(encoder); 1410 1411 /* Wa_1409054076:icl,jsl,ehl */ 1412 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); 1413 1414 /* step2f,g: powerdown panel */ 1415 gen11_dsi_powerdown_panel(encoder); 1416 1417 /* step2h,i,j: deconfig trancoder */ 1418 gen11_dsi_deconfigure_trancoder(encoder); 1419 1420 intel_dsc_disable(old_crtc_state); 1421 skl_scaler_disable(old_crtc_state); 1422 1423 /* step3: disable port */ 1424 gen11_dsi_disable_port(encoder); 1425 1426 gen11_dsi_config_util_pin(encoder, false); 1427 1428 /* step4: disable IO power */ 1429 gen11_dsi_disable_io_power(encoder); 1430 1431 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1432 1433 msleep(intel_dsi->panel_off_delay); 1434 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1435 1436 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1437 } 1438 1439 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1440 struct drm_display_mode *mode) 1441 { 1442 struct drm_i915_private *i915 = to_i915(connector->dev); 1443 enum drm_mode_status status; 1444 1445 status = intel_cpu_transcoder_mode_valid(i915, mode); 1446 if (status != MODE_OK) 1447 return status; 1448 1449 /* FIXME: DSC? */ 1450 return intel_dsi_mode_valid(connector, mode); 1451 } 1452 1453 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1454 struct intel_crtc_state *pipe_config) 1455 { 1456 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1457 struct drm_display_mode *adjusted_mode = 1458 &pipe_config->hw.adjusted_mode; 1459 1460 if (pipe_config->dsc.compressed_bpp) { 1461 int div = pipe_config->dsc.compressed_bpp; 1462 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1463 1464 adjusted_mode->crtc_htotal = 1465 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1466 adjusted_mode->crtc_hsync_start = 1467 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1468 adjusted_mode->crtc_hsync_end = 1469 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1470 } 1471 1472 if (intel_dsi->dual_link) { 1473 adjusted_mode->crtc_hdisplay *= 2; 1474 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1475 adjusted_mode->crtc_hdisplay -= 1476 intel_dsi->pixel_overlap; 1477 adjusted_mode->crtc_htotal *= 2; 1478 } 1479 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1480 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1481 1482 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1483 if (intel_dsi->dual_link) { 1484 adjusted_mode->crtc_hsync_start *= 2; 1485 adjusted_mode->crtc_hsync_end *= 2; 1486 } 1487 } 1488 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1489 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1490 } 1491 1492 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1493 { 1494 struct drm_device *dev = intel_dsi->base.base.dev; 1495 struct drm_i915_private *dev_priv = to_i915(dev); 1496 enum transcoder dsi_trans; 1497 u32 val; 1498 1499 if (intel_dsi->ports == BIT(PORT_B)) 1500 dsi_trans = TRANSCODER_DSI_1; 1501 else 1502 dsi_trans = TRANSCODER_DSI_0; 1503 1504 val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 1505 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1506 } 1507 1508 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1509 struct intel_crtc_state *pipe_config) 1510 { 1511 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1512 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1513 I915_MODE_FLAG_DSI_USE_TE0; 1514 else if (intel_dsi->ports == BIT(PORT_B)) 1515 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1516 else 1517 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1518 } 1519 1520 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1521 struct intel_crtc_state *pipe_config) 1522 { 1523 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1524 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1525 1526 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1527 1528 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1529 if (intel_dsi->dual_link) 1530 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1531 1532 gen11_dsi_get_timings(encoder, pipe_config); 1533 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1534 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); 1535 1536 /* Get the details on which TE should be enabled */ 1537 if (is_cmd_mode(intel_dsi)) 1538 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1539 1540 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1541 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1542 } 1543 1544 static void gen11_dsi_sync_state(struct intel_encoder *encoder, 1545 const struct intel_crtc_state *crtc_state) 1546 { 1547 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1548 struct intel_crtc *intel_crtc; 1549 enum pipe pipe; 1550 1551 if (!crtc_state) 1552 return; 1553 1554 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1555 pipe = intel_crtc->pipe; 1556 1557 /* wa verify 1409054076:icl,jsl,ehl */ 1558 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && 1559 !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A)) 1560 drm_dbg_kms(&dev_priv->drm, 1561 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n", 1562 encoder->base.base.id, 1563 encoder->base.name); 1564 } 1565 1566 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1567 struct intel_crtc_state *crtc_state) 1568 { 1569 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1570 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1571 int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10; 1572 bool use_dsc; 1573 int ret; 1574 1575 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1576 if (!use_dsc) 1577 return 0; 1578 1579 if (crtc_state->pipe_bpp < 8 * 3) 1580 return -EINVAL; 1581 1582 /* FIXME: split only when necessary */ 1583 if (crtc_state->dsc.slice_count > 1) 1584 crtc_state->dsc.dsc_split = true; 1585 1586 /* FIXME: initialize from VBT */ 1587 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1588 1589 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1590 1591 ret = intel_dsc_compute_params(crtc_state); 1592 if (ret) 1593 return ret; 1594 1595 /* DSI specific sanity checks on the common code */ 1596 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); 1597 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); 1598 drm_WARN_ON(&dev_priv->drm, 1599 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1600 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); 1601 drm_WARN_ON(&dev_priv->drm, 1602 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1603 1604 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1605 if (ret) 1606 return ret; 1607 1608 crtc_state->dsc.compression_enable = true; 1609 1610 return 0; 1611 } 1612 1613 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1614 struct intel_crtc_state *pipe_config, 1615 struct drm_connector_state *conn_state) 1616 { 1617 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1618 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 1619 base); 1620 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1621 struct drm_display_mode *adjusted_mode = 1622 &pipe_config->hw.adjusted_mode; 1623 int ret; 1624 1625 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 1626 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1627 1628 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 1629 if (ret) 1630 return ret; 1631 1632 ret = intel_panel_fitting(pipe_config, conn_state); 1633 if (ret) 1634 return ret; 1635 1636 adjusted_mode->flags = 0; 1637 1638 /* Dual link goes to trancoder DSI'0' */ 1639 if (intel_dsi->ports == BIT(PORT_B)) 1640 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1641 else 1642 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1643 1644 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1645 pipe_config->pipe_bpp = 24; 1646 else 1647 pipe_config->pipe_bpp = 18; 1648 1649 pipe_config->clock_set = true; 1650 1651 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1652 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n"); 1653 1654 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1655 1656 /* 1657 * In case of TE GATE cmd mode, we 1658 * receive TE from the slave if 1659 * dual link is enabled 1660 */ 1661 if (is_cmd_mode(intel_dsi)) 1662 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1663 1664 return 0; 1665 } 1666 1667 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1668 struct intel_crtc_state *crtc_state) 1669 { 1670 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1671 1672 get_dsi_io_power_domains(i915, 1673 enc_to_intel_dsi(encoder)); 1674 } 1675 1676 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1677 enum pipe *pipe) 1678 { 1679 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1680 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1681 enum transcoder dsi_trans; 1682 intel_wakeref_t wakeref; 1683 enum port port; 1684 bool ret = false; 1685 u32 tmp; 1686 1687 wakeref = intel_display_power_get_if_enabled(dev_priv, 1688 encoder->power_domain); 1689 if (!wakeref) 1690 return false; 1691 1692 for_each_dsi_port(port, intel_dsi->ports) { 1693 dsi_trans = dsi_port_to_transcoder(port); 1694 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1695 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1696 case TRANS_DDI_EDP_INPUT_A_ON: 1697 *pipe = PIPE_A; 1698 break; 1699 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1700 *pipe = PIPE_B; 1701 break; 1702 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1703 *pipe = PIPE_C; 1704 break; 1705 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1706 *pipe = PIPE_D; 1707 break; 1708 default: 1709 drm_err(&dev_priv->drm, "Invalid PIPE input\n"); 1710 goto out; 1711 } 1712 1713 tmp = intel_de_read(dev_priv, TRANSCONF(dsi_trans)); 1714 ret = tmp & TRANSCONF_ENABLE; 1715 } 1716 out: 1717 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1718 return ret; 1719 } 1720 1721 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1722 struct intel_crtc_state *crtc_state) 1723 { 1724 if (crtc_state->dsc.compression_enable) { 1725 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1726 crtc_state->uapi.mode_changed = true; 1727 1728 return false; 1729 } 1730 1731 return true; 1732 } 1733 1734 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1735 { 1736 intel_encoder_destroy(encoder); 1737 } 1738 1739 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1740 .destroy = gen11_dsi_encoder_destroy, 1741 }; 1742 1743 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1744 .detect = intel_panel_detect, 1745 .late_register = intel_connector_register, 1746 .early_unregister = intel_connector_unregister, 1747 .destroy = intel_connector_destroy, 1748 .fill_modes = drm_helper_probe_single_connector_modes, 1749 .atomic_get_property = intel_digital_connector_atomic_get_property, 1750 .atomic_set_property = intel_digital_connector_atomic_set_property, 1751 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1752 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1753 }; 1754 1755 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1756 .get_modes = intel_dsi_get_modes, 1757 .mode_valid = gen11_dsi_mode_valid, 1758 .atomic_check = intel_digital_connector_atomic_check, 1759 }; 1760 1761 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1762 struct mipi_dsi_device *dsi) 1763 { 1764 return 0; 1765 } 1766 1767 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1768 struct mipi_dsi_device *dsi) 1769 { 1770 return 0; 1771 } 1772 1773 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1774 const struct mipi_dsi_msg *msg) 1775 { 1776 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1777 struct mipi_dsi_packet dsi_pkt; 1778 ssize_t ret; 1779 bool enable_lpdt = false; 1780 1781 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1782 if (ret < 0) 1783 return ret; 1784 1785 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1786 enable_lpdt = true; 1787 1788 /* only long packet contains payload */ 1789 if (mipi_dsi_packet_format_is_long(msg->type)) { 1790 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt); 1791 if (ret < 0) 1792 return ret; 1793 } 1794 1795 /* send packet header */ 1796 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt); 1797 if (ret < 0) 1798 return ret; 1799 1800 //TODO: add payload receive code if needed 1801 1802 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1803 1804 return ret; 1805 } 1806 1807 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1808 .attach = gen11_dsi_host_attach, 1809 .detach = gen11_dsi_host_detach, 1810 .transfer = gen11_dsi_host_transfer, 1811 }; 1812 1813 #define ICL_PREPARE_CNT_MAX 0x7 1814 #define ICL_CLK_ZERO_CNT_MAX 0xf 1815 #define ICL_TRAIL_CNT_MAX 0x7 1816 #define ICL_TCLK_PRE_CNT_MAX 0x3 1817 #define ICL_TCLK_POST_CNT_MAX 0x7 1818 #define ICL_HS_ZERO_CNT_MAX 0xf 1819 #define ICL_EXIT_ZERO_CNT_MAX 0x7 1820 1821 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1822 { 1823 struct drm_device *dev = intel_dsi->base.base.dev; 1824 struct drm_i915_private *dev_priv = to_i915(dev); 1825 struct intel_connector *connector = intel_dsi->attached_connector; 1826 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1827 u32 tlpx_ns; 1828 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1829 u32 ths_prepare_ns, tclk_trail_ns; 1830 u32 hs_zero_cnt; 1831 u32 tclk_pre_cnt, tclk_post_cnt; 1832 1833 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1834 1835 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1836 ths_prepare_ns = max(mipi_config->ths_prepare, 1837 mipi_config->tclk_prepare); 1838 1839 /* 1840 * prepare cnt in escape clocks 1841 * this field represents a hexadecimal value with a precision 1842 * of 1.2 – i.e. the most significant bit is the integer 1843 * and the least significant 2 bits are fraction bits. 1844 * so, the field can represent a range of 0.25 to 1.75 1845 */ 1846 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1847 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1848 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", 1849 prepare_cnt); 1850 prepare_cnt = ICL_PREPARE_CNT_MAX; 1851 } 1852 1853 /* clk zero count in escape clocks */ 1854 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1855 ths_prepare_ns, tlpx_ns); 1856 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1857 drm_dbg_kms(&dev_priv->drm, 1858 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1859 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1860 } 1861 1862 /* trail cnt in escape clocks*/ 1863 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1864 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1865 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", 1866 trail_cnt); 1867 trail_cnt = ICL_TRAIL_CNT_MAX; 1868 } 1869 1870 /* tclk pre count in escape clocks */ 1871 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1872 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1873 drm_dbg_kms(&dev_priv->drm, 1874 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1875 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1876 } 1877 1878 /* tclk post count in escape clocks */ 1879 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); 1880 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { 1881 drm_dbg_kms(&dev_priv->drm, 1882 "tclk_post_cnt out of range (%d)\n", 1883 tclk_post_cnt); 1884 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; 1885 } 1886 1887 /* hs zero cnt in escape clocks */ 1888 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1889 ths_prepare_ns, tlpx_ns); 1890 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1891 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", 1892 hs_zero_cnt); 1893 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1894 } 1895 1896 /* hs exit zero cnt in escape clocks */ 1897 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1898 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1899 drm_dbg_kms(&dev_priv->drm, 1900 "exit_zero_cnt out of range (%d)\n", 1901 exit_zero_cnt); 1902 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1903 } 1904 1905 /* clock lane dphy timings */ 1906 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1907 CLK_PREPARE(prepare_cnt) | 1908 CLK_ZERO_OVERRIDE | 1909 CLK_ZERO(clk_zero_cnt) | 1910 CLK_PRE_OVERRIDE | 1911 CLK_PRE(tclk_pre_cnt) | 1912 CLK_POST_OVERRIDE | 1913 CLK_POST(tclk_post_cnt) | 1914 CLK_TRAIL_OVERRIDE | 1915 CLK_TRAIL(trail_cnt)); 1916 1917 /* data lanes dphy timings */ 1918 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1919 HS_PREPARE(prepare_cnt) | 1920 HS_ZERO_OVERRIDE | 1921 HS_ZERO(hs_zero_cnt) | 1922 HS_TRAIL_OVERRIDE | 1923 HS_TRAIL(trail_cnt) | 1924 HS_EXIT_OVERRIDE | 1925 HS_EXIT(exit_zero_cnt)); 1926 1927 intel_dsi_log_params(intel_dsi); 1928 } 1929 1930 static void icl_dsi_add_properties(struct intel_connector *connector) 1931 { 1932 const struct drm_display_mode *fixed_mode = 1933 intel_panel_preferred_fixed_mode(connector); 1934 1935 intel_attach_scaling_mode_property(&connector->base); 1936 1937 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1938 intel_dsi_get_panel_orientation(connector), 1939 fixed_mode->hdisplay, 1940 fixed_mode->vdisplay); 1941 } 1942 1943 void icl_dsi_init(struct drm_i915_private *dev_priv, 1944 const struct intel_bios_encoder_data *devdata) 1945 { 1946 struct intel_dsi *intel_dsi; 1947 struct intel_encoder *encoder; 1948 struct intel_connector *intel_connector; 1949 struct drm_connector *connector; 1950 enum port port; 1951 1952 port = intel_bios_encoder_port(devdata); 1953 if (port == PORT_NONE) 1954 return; 1955 1956 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1957 if (!intel_dsi) 1958 return; 1959 1960 intel_connector = intel_connector_alloc(); 1961 if (!intel_connector) { 1962 kfree(intel_dsi); 1963 return; 1964 } 1965 1966 encoder = &intel_dsi->base; 1967 intel_dsi->attached_connector = intel_connector; 1968 connector = &intel_connector->base; 1969 1970 encoder->devdata = devdata; 1971 1972 /* register DSI encoder with DRM subsystem */ 1973 drm_encoder_init(&dev_priv->drm, &encoder->base, &gen11_dsi_encoder_funcs, 1974 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 1975 1976 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 1977 encoder->pre_enable = gen11_dsi_pre_enable; 1978 encoder->enable = gen11_dsi_enable; 1979 encoder->disable = gen11_dsi_disable; 1980 encoder->post_disable = gen11_dsi_post_disable; 1981 encoder->port = port; 1982 encoder->get_config = gen11_dsi_get_config; 1983 encoder->sync_state = gen11_dsi_sync_state; 1984 encoder->update_pipe = intel_backlight_update; 1985 encoder->compute_config = gen11_dsi_compute_config; 1986 encoder->get_hw_state = gen11_dsi_get_hw_state; 1987 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 1988 encoder->type = INTEL_OUTPUT_DSI; 1989 encoder->cloneable = 0; 1990 encoder->pipe_mask = ~0; 1991 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1992 encoder->get_power_domains = gen11_dsi_get_power_domains; 1993 encoder->disable_clock = gen11_dsi_gate_clocks; 1994 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 1995 encoder->shutdown = intel_dsi_shutdown; 1996 1997 /* register DSI connector with DRM subsystem */ 1998 drm_connector_init(&dev_priv->drm, connector, &gen11_dsi_connector_funcs, 1999 DRM_MODE_CONNECTOR_DSI); 2000 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 2001 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 2002 intel_connector->get_hw_state = intel_connector_get_hw_state; 2003 2004 /* attach connector to encoder */ 2005 intel_connector_attach_encoder(intel_connector, encoder); 2006 2007 intel_dsi->panel_power_off_time = ktime_get_boottime(); 2008 2009 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata, NULL); 2010 2011 mutex_lock(&dev_priv->drm.mode_config.mutex); 2012 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 2013 mutex_unlock(&dev_priv->drm.mode_config.mutex); 2014 2015 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2016 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); 2017 goto err; 2018 } 2019 2020 intel_panel_init(intel_connector, NULL); 2021 2022 intel_backlight_setup(intel_connector, INVALID_PIPE); 2023 2024 if (intel_connector->panel.vbt.dsi.config->dual_link) 2025 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 2026 else 2027 intel_dsi->ports = BIT(port); 2028 2029 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) 2030 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; 2031 2032 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) 2033 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; 2034 2035 for_each_dsi_port(port, intel_dsi->ports) { 2036 struct intel_dsi_host *host; 2037 2038 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2039 if (!host) 2040 goto err; 2041 2042 intel_dsi->dsi_hosts[port] = host; 2043 } 2044 2045 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2046 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 2047 goto err; 2048 } 2049 2050 icl_dphy_param_init(intel_dsi); 2051 2052 icl_dsi_add_properties(intel_connector); 2053 return; 2054 2055 err: 2056 drm_connector_cleanup(connector); 2057 drm_encoder_cleanup(&encoder->base); 2058 kfree(intel_dsi); 2059 kfree(intel_connector); 2060 } 2061