1*94b49d53SJani Nikula /* SPDX-License-Identifier: MIT */ 2*94b49d53SJani Nikula /* 3*94b49d53SJani Nikula * Copyright © 2023 Intel Corporation 4*94b49d53SJani Nikula */ 5*94b49d53SJani Nikula 6*94b49d53SJani Nikula #ifndef __I9XX_WM_H__ 7*94b49d53SJani Nikula #define __I9XX_WM_H__ 8*94b49d53SJani Nikula 9*94b49d53SJani Nikula #include <linux/types.h> 10*94b49d53SJani Nikula 11*94b49d53SJani Nikula struct drm_i915_private; 12*94b49d53SJani Nikula struct intel_crtc_state; 13*94b49d53SJani Nikula struct intel_plane_state; 14*94b49d53SJani Nikula 15*94b49d53SJani Nikula int ilk_wm_max_level(const struct drm_i915_private *i915); 16*94b49d53SJani Nikula void g4x_wm_get_hw_state(struct drm_i915_private *i915); 17*94b49d53SJani Nikula void vlv_wm_get_hw_state(struct drm_i915_private *i915); 18*94b49d53SJani Nikula void ilk_wm_get_hw_state(struct drm_i915_private *i915); 19*94b49d53SJani Nikula void g4x_wm_sanitize(struct drm_i915_private *i915); 20*94b49d53SJani Nikula void vlv_wm_sanitize(struct drm_i915_private *i915); 21*94b49d53SJani Nikula bool ilk_disable_lp_wm(struct drm_i915_private *i915); 22*94b49d53SJani Nikula bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable); 23*94b49d53SJani Nikula void i9xx_wm_init(struct drm_i915_private *i915); 24*94b49d53SJani Nikula 25*94b49d53SJani Nikula #endif /* __I9XX_WM_H__ */ 26