194b49d53SJani Nikula /* SPDX-License-Identifier: MIT */ 294b49d53SJani Nikula /* 394b49d53SJani Nikula * Copyright © 2023 Intel Corporation 494b49d53SJani Nikula */ 594b49d53SJani Nikula 694b49d53SJani Nikula #ifndef __I9XX_WM_H__ 794b49d53SJani Nikula #define __I9XX_WM_H__ 894b49d53SJani Nikula 994b49d53SJani Nikula #include <linux/types.h> 1094b49d53SJani Nikula 1194b49d53SJani Nikula struct drm_i915_private; 1294b49d53SJani Nikula struct intel_crtc_state; 1394b49d53SJani Nikula struct intel_plane_state; 1494b49d53SJani Nikula 1594b49d53SJani Nikula int ilk_wm_max_level(const struct drm_i915_private *i915); 1694b49d53SJani Nikula bool ilk_disable_lp_wm(struct drm_i915_private *i915); 17*3dadb4a1SJani Nikula void ilk_wm_sanitize(struct drm_i915_private *i915); 1894b49d53SJani Nikula bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable); 1994b49d53SJani Nikula void i9xx_wm_init(struct drm_i915_private *i915); 2094b49d53SJani Nikula 2194b49d53SJani Nikula #endif /* __I9XX_WM_H__ */ 22