1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 #include <linux/kernel.h> 6 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_fourcc.h> 9 #include <drm/drm_plane_helper.h> 10 11 #include "intel_atomic.h" 12 #include "intel_atomic_plane.h" 13 #include "intel_display_types.h" 14 #include "intel_sprite.h" 15 #include "i9xx_plane.h" 16 17 /* Primary plane formats for gen <= 3 */ 18 static const u32 i8xx_primary_formats[] = { 19 DRM_FORMAT_C8, 20 DRM_FORMAT_XRGB1555, 21 DRM_FORMAT_RGB565, 22 DRM_FORMAT_XRGB8888, 23 }; 24 25 /* Primary plane formats for ivb (no fp16 due to hw issue) */ 26 static const u32 ivb_primary_formats[] = { 27 DRM_FORMAT_C8, 28 DRM_FORMAT_RGB565, 29 DRM_FORMAT_XRGB8888, 30 DRM_FORMAT_XBGR8888, 31 DRM_FORMAT_XRGB2101010, 32 DRM_FORMAT_XBGR2101010, 33 }; 34 35 /* Primary plane formats for gen >= 4, except ivb */ 36 static const u32 i965_primary_formats[] = { 37 DRM_FORMAT_C8, 38 DRM_FORMAT_RGB565, 39 DRM_FORMAT_XRGB8888, 40 DRM_FORMAT_XBGR8888, 41 DRM_FORMAT_XRGB2101010, 42 DRM_FORMAT_XBGR2101010, 43 DRM_FORMAT_XBGR16161616F, 44 }; 45 46 /* Primary plane formats for vlv/chv */ 47 static const u32 vlv_primary_formats[] = { 48 DRM_FORMAT_C8, 49 DRM_FORMAT_RGB565, 50 DRM_FORMAT_XRGB8888, 51 DRM_FORMAT_XBGR8888, 52 DRM_FORMAT_ARGB8888, 53 DRM_FORMAT_ABGR8888, 54 DRM_FORMAT_XRGB2101010, 55 DRM_FORMAT_XBGR2101010, 56 DRM_FORMAT_ARGB2101010, 57 DRM_FORMAT_ABGR2101010, 58 DRM_FORMAT_XBGR16161616F, 59 }; 60 61 static const u64 i9xx_format_modifiers[] = { 62 I915_FORMAT_MOD_X_TILED, 63 DRM_FORMAT_MOD_LINEAR, 64 DRM_FORMAT_MOD_INVALID 65 }; 66 67 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, 68 u32 format, u64 modifier) 69 { 70 switch (modifier) { 71 case DRM_FORMAT_MOD_LINEAR: 72 case I915_FORMAT_MOD_X_TILED: 73 break; 74 default: 75 return false; 76 } 77 78 switch (format) { 79 case DRM_FORMAT_C8: 80 case DRM_FORMAT_RGB565: 81 case DRM_FORMAT_XRGB1555: 82 case DRM_FORMAT_XRGB8888: 83 return modifier == DRM_FORMAT_MOD_LINEAR || 84 modifier == I915_FORMAT_MOD_X_TILED; 85 default: 86 return false; 87 } 88 } 89 90 static bool i965_plane_format_mod_supported(struct drm_plane *_plane, 91 u32 format, u64 modifier) 92 { 93 switch (modifier) { 94 case DRM_FORMAT_MOD_LINEAR: 95 case I915_FORMAT_MOD_X_TILED: 96 break; 97 default: 98 return false; 99 } 100 101 switch (format) { 102 case DRM_FORMAT_C8: 103 case DRM_FORMAT_RGB565: 104 case DRM_FORMAT_XRGB8888: 105 case DRM_FORMAT_XBGR8888: 106 case DRM_FORMAT_ARGB8888: 107 case DRM_FORMAT_ABGR8888: 108 case DRM_FORMAT_XRGB2101010: 109 case DRM_FORMAT_XBGR2101010: 110 case DRM_FORMAT_ARGB2101010: 111 case DRM_FORMAT_ABGR2101010: 112 case DRM_FORMAT_XBGR16161616F: 113 return modifier == DRM_FORMAT_MOD_LINEAR || 114 modifier == I915_FORMAT_MOD_X_TILED; 115 default: 116 return false; 117 } 118 } 119 120 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, 121 enum i9xx_plane_id i9xx_plane) 122 { 123 if (!HAS_FBC(dev_priv)) 124 return false; 125 126 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 127 return i9xx_plane == PLANE_A; /* tied to pipe A */ 128 else if (IS_IVYBRIDGE(dev_priv)) 129 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B || 130 i9xx_plane == PLANE_C; 131 else if (INTEL_GEN(dev_priv) >= 4) 132 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B; 133 else 134 return i9xx_plane == PLANE_A; 135 } 136 137 static bool i9xx_plane_has_windowing(struct intel_plane *plane) 138 { 139 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 140 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 141 142 if (IS_CHERRYVIEW(dev_priv)) 143 return i9xx_plane == PLANE_B; 144 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) 145 return false; 146 else if (IS_GEN(dev_priv, 4)) 147 return i9xx_plane == PLANE_C; 148 else 149 return i9xx_plane == PLANE_B || 150 i9xx_plane == PLANE_C; 151 } 152 153 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, 154 const struct intel_plane_state *plane_state) 155 { 156 struct drm_i915_private *dev_priv = 157 to_i915(plane_state->uapi.plane->dev); 158 const struct drm_framebuffer *fb = plane_state->hw.fb; 159 unsigned int rotation = plane_state->hw.rotation; 160 u32 dspcntr; 161 162 dspcntr = DISPLAY_PLANE_ENABLE; 163 164 if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) || 165 IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) 166 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 167 168 switch (fb->format->format) { 169 case DRM_FORMAT_C8: 170 dspcntr |= DISPPLANE_8BPP; 171 break; 172 case DRM_FORMAT_XRGB1555: 173 dspcntr |= DISPPLANE_BGRX555; 174 break; 175 case DRM_FORMAT_ARGB1555: 176 dspcntr |= DISPPLANE_BGRA555; 177 break; 178 case DRM_FORMAT_RGB565: 179 dspcntr |= DISPPLANE_BGRX565; 180 break; 181 case DRM_FORMAT_XRGB8888: 182 dspcntr |= DISPPLANE_BGRX888; 183 break; 184 case DRM_FORMAT_XBGR8888: 185 dspcntr |= DISPPLANE_RGBX888; 186 break; 187 case DRM_FORMAT_ARGB8888: 188 dspcntr |= DISPPLANE_BGRA888; 189 break; 190 case DRM_FORMAT_ABGR8888: 191 dspcntr |= DISPPLANE_RGBA888; 192 break; 193 case DRM_FORMAT_XRGB2101010: 194 dspcntr |= DISPPLANE_BGRX101010; 195 break; 196 case DRM_FORMAT_XBGR2101010: 197 dspcntr |= DISPPLANE_RGBX101010; 198 break; 199 case DRM_FORMAT_ARGB2101010: 200 dspcntr |= DISPPLANE_BGRA101010; 201 break; 202 case DRM_FORMAT_ABGR2101010: 203 dspcntr |= DISPPLANE_RGBA101010; 204 break; 205 case DRM_FORMAT_XBGR16161616F: 206 dspcntr |= DISPPLANE_RGBX161616; 207 break; 208 default: 209 MISSING_CASE(fb->format->format); 210 return 0; 211 } 212 213 if (INTEL_GEN(dev_priv) >= 4 && 214 fb->modifier == I915_FORMAT_MOD_X_TILED) 215 dspcntr |= DISPPLANE_TILED; 216 217 if (rotation & DRM_MODE_ROTATE_180) 218 dspcntr |= DISPPLANE_ROTATE_180; 219 220 if (rotation & DRM_MODE_REFLECT_X) 221 dspcntr |= DISPPLANE_MIRROR; 222 223 return dspcntr; 224 } 225 226 int i9xx_check_plane_surface(struct intel_plane_state *plane_state) 227 { 228 struct drm_i915_private *dev_priv = 229 to_i915(plane_state->uapi.plane->dev); 230 const struct drm_framebuffer *fb = plane_state->hw.fb; 231 int src_x, src_y, src_w; 232 u32 offset; 233 int ret; 234 235 ret = intel_plane_compute_gtt(plane_state); 236 if (ret) 237 return ret; 238 239 if (!plane_state->uapi.visible) 240 return 0; 241 242 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 243 src_x = plane_state->uapi.src.x1 >> 16; 244 src_y = plane_state->uapi.src.y1 >> 16; 245 246 /* Undocumented hardware limit on i965/g4x/vlv/chv */ 247 if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048) 248 return -EINVAL; 249 250 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); 251 252 if (INTEL_GEN(dev_priv) >= 4) 253 offset = intel_plane_compute_aligned_offset(&src_x, &src_y, 254 plane_state, 0); 255 else 256 offset = 0; 257 258 /* 259 * Put the final coordinates back so that the src 260 * coordinate checks will see the right values. 261 */ 262 drm_rect_translate_to(&plane_state->uapi.src, 263 src_x << 16, src_y << 16); 264 265 /* HSW/BDW do this automagically in hardware */ 266 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { 267 unsigned int rotation = plane_state->hw.rotation; 268 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 269 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 270 271 if (rotation & DRM_MODE_ROTATE_180) { 272 src_x += src_w - 1; 273 src_y += src_h - 1; 274 } else if (rotation & DRM_MODE_REFLECT_X) { 275 src_x += src_w - 1; 276 } 277 } 278 279 plane_state->color_plane[0].offset = offset; 280 plane_state->color_plane[0].x = src_x; 281 plane_state->color_plane[0].y = src_y; 282 283 return 0; 284 } 285 286 static int 287 i9xx_plane_check(struct intel_crtc_state *crtc_state, 288 struct intel_plane_state *plane_state) 289 { 290 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 291 int ret; 292 293 ret = chv_plane_check_rotation(plane_state); 294 if (ret) 295 return ret; 296 297 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 298 DRM_PLANE_HELPER_NO_SCALING, 299 DRM_PLANE_HELPER_NO_SCALING, 300 i9xx_plane_has_windowing(plane)); 301 if (ret) 302 return ret; 303 304 ret = i9xx_check_plane_surface(plane_state); 305 if (ret) 306 return ret; 307 308 if (!plane_state->uapi.visible) 309 return 0; 310 311 ret = intel_plane_check_src_coordinates(plane_state); 312 if (ret) 313 return ret; 314 315 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state); 316 317 return 0; 318 } 319 320 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) 321 { 322 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 323 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 324 u32 dspcntr = 0; 325 326 if (crtc_state->gamma_enable) 327 dspcntr |= DISPPLANE_GAMMA_ENABLE; 328 329 if (crtc_state->csc_enable) 330 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; 331 332 if (INTEL_GEN(dev_priv) < 5) 333 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); 334 335 return dspcntr; 336 } 337 338 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state, 339 const struct intel_plane_state *plane_state, 340 unsigned int *num, unsigned int *den) 341 { 342 const struct drm_framebuffer *fb = plane_state->hw.fb; 343 unsigned int cpp = fb->format->cpp[0]; 344 345 /* 346 * g4x bspec says 64bpp pixel rate can't exceed 80% 347 * of cdclk when the sprite plane is enabled on the 348 * same pipe. ilk/snb bspec says 64bpp pixel rate is 349 * never allowed to exceed 80% of cdclk. Let's just go 350 * with the ilk/snb limit always. 351 */ 352 if (cpp == 8) { 353 *num = 10; 354 *den = 8; 355 } else { 356 *num = 1; 357 *den = 1; 358 } 359 } 360 361 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 362 const struct intel_plane_state *plane_state) 363 { 364 unsigned int pixel_rate; 365 unsigned int num, den; 366 367 /* 368 * Note that crtc_state->pixel_rate accounts for both 369 * horizontal and vertical panel fitter downscaling factors. 370 * Pre-HSW bspec tells us to only consider the horizontal 371 * downscaling factor here. We ignore that and just consider 372 * both for simplicity. 373 */ 374 pixel_rate = crtc_state->pixel_rate; 375 376 i9xx_plane_ratio(crtc_state, plane_state, &num, &den); 377 378 /* two pixels per clock with double wide pipe */ 379 if (crtc_state->double_wide) 380 den *= 2; 381 382 return DIV_ROUND_UP(pixel_rate * num, den); 383 } 384 385 static void i9xx_update_plane(struct intel_plane *plane, 386 const struct intel_crtc_state *crtc_state, 387 const struct intel_plane_state *plane_state) 388 { 389 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 390 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 391 u32 linear_offset; 392 int x = plane_state->color_plane[0].x; 393 int y = plane_state->color_plane[0].y; 394 int crtc_x = plane_state->uapi.dst.x1; 395 int crtc_y = plane_state->uapi.dst.y1; 396 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 397 int crtc_h = drm_rect_height(&plane_state->uapi.dst); 398 unsigned long irqflags; 399 u32 dspaddr_offset; 400 u32 dspcntr; 401 402 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); 403 404 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 405 406 if (INTEL_GEN(dev_priv) >= 4) 407 dspaddr_offset = plane_state->color_plane[0].offset; 408 else 409 dspaddr_offset = linear_offset; 410 411 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 412 413 intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), 414 plane_state->color_plane[0].stride); 415 416 if (INTEL_GEN(dev_priv) < 4) { 417 /* 418 * PLANE_A doesn't actually have a full window 419 * generator but let's assume we still need to 420 * program whatever is there. 421 */ 422 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), 423 (crtc_y << 16) | crtc_x); 424 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), 425 ((crtc_h - 1) << 16) | (crtc_w - 1)); 426 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { 427 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), 428 (crtc_y << 16) | crtc_x); 429 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), 430 ((crtc_h - 1) << 16) | (crtc_w - 1)); 431 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); 432 } 433 434 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 435 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), 436 (y << 16) | x); 437 } else if (INTEL_GEN(dev_priv) >= 4) { 438 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), 439 linear_offset); 440 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), 441 (y << 16) | x); 442 } 443 444 /* 445 * The control register self-arms if the plane was previously 446 * disabled. Try to make the plane enable atomic by writing 447 * the control register just before the surface register. 448 */ 449 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); 450 if (INTEL_GEN(dev_priv) >= 4) 451 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 452 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 453 else 454 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 455 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 456 457 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 458 } 459 460 static void i9xx_disable_plane(struct intel_plane *plane, 461 const struct intel_crtc_state *crtc_state) 462 { 463 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 464 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 465 unsigned long irqflags; 466 u32 dspcntr; 467 468 /* 469 * DSPCNTR pipe gamma enable on g4x+ and pipe csc 470 * enable on ilk+ affect the pipe bottom color as 471 * well, so we must configure them even if the plane 472 * is disabled. 473 * 474 * On pre-g4x there is no way to gamma correct the 475 * pipe bottom color but we'll keep on doing this 476 * anyway so that the crtc state readout works correctly. 477 */ 478 dspcntr = i9xx_plane_ctl_crtc(crtc_state); 479 480 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 481 482 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); 483 if (INTEL_GEN(dev_priv) >= 4) 484 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); 485 else 486 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0); 487 488 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 489 } 490 491 static bool i9xx_plane_get_hw_state(struct intel_plane *plane, 492 enum pipe *pipe) 493 { 494 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 495 enum intel_display_power_domain power_domain; 496 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 497 intel_wakeref_t wakeref; 498 bool ret; 499 u32 val; 500 501 /* 502 * Not 100% correct for planes that can move between pipes, 503 * but that's only the case for gen2-4 which don't have any 504 * display power wells. 505 */ 506 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 507 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 508 if (!wakeref) 509 return false; 510 511 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 512 513 ret = val & DISPLAY_PLANE_ENABLE; 514 515 if (INTEL_GEN(dev_priv) >= 5) 516 *pipe = plane->pipe; 517 else 518 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> 519 DISPPLANE_SEL_PIPE_SHIFT; 520 521 intel_display_power_put(dev_priv, power_domain, wakeref); 522 523 return ret; 524 } 525 526 unsigned int 527 i9xx_plane_max_stride(struct intel_plane *plane, 528 u32 pixel_format, u64 modifier, 529 unsigned int rotation) 530 { 531 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 532 533 if (!HAS_GMCH(dev_priv)) { 534 return 32*1024; 535 } else if (INTEL_GEN(dev_priv) >= 4) { 536 if (modifier == I915_FORMAT_MOD_X_TILED) 537 return 16*1024; 538 else 539 return 32*1024; 540 } else if (INTEL_GEN(dev_priv) >= 3) { 541 if (modifier == I915_FORMAT_MOD_X_TILED) 542 return 8*1024; 543 else 544 return 16*1024; 545 } else { 546 if (plane->i9xx_plane == PLANE_C) 547 return 4*1024; 548 else 549 return 8*1024; 550 } 551 } 552 553 static const struct drm_plane_funcs i965_plane_funcs = { 554 .update_plane = drm_atomic_helper_update_plane, 555 .disable_plane = drm_atomic_helper_disable_plane, 556 .destroy = intel_plane_destroy, 557 .atomic_duplicate_state = intel_plane_duplicate_state, 558 .atomic_destroy_state = intel_plane_destroy_state, 559 .format_mod_supported = i965_plane_format_mod_supported, 560 }; 561 562 static const struct drm_plane_funcs i8xx_plane_funcs = { 563 .update_plane = drm_atomic_helper_update_plane, 564 .disable_plane = drm_atomic_helper_disable_plane, 565 .destroy = intel_plane_destroy, 566 .atomic_duplicate_state = intel_plane_duplicate_state, 567 .atomic_destroy_state = intel_plane_destroy_state, 568 .format_mod_supported = i8xx_plane_format_mod_supported, 569 }; 570 571 struct intel_plane * 572 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 573 { 574 struct intel_plane *plane; 575 const struct drm_plane_funcs *plane_funcs; 576 unsigned int supported_rotations; 577 const u32 *formats; 578 int num_formats; 579 int ret, zpos; 580 581 if (INTEL_GEN(dev_priv) >= 9) 582 return skl_universal_plane_create(dev_priv, pipe, 583 PLANE_PRIMARY); 584 585 plane = intel_plane_alloc(); 586 if (IS_ERR(plane)) 587 return plane; 588 589 plane->pipe = pipe; 590 /* 591 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS 592 * port is hooked to pipe B. Hence we want plane A feeding pipe B. 593 */ 594 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 && 595 INTEL_NUM_PIPES(dev_priv) == 2) 596 plane->i9xx_plane = (enum i9xx_plane_id) !pipe; 597 else 598 plane->i9xx_plane = (enum i9xx_plane_id) pipe; 599 plane->id = PLANE_PRIMARY; 600 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); 601 602 plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane); 603 if (plane->has_fbc) { 604 struct intel_fbc *fbc = &dev_priv->fbc; 605 606 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; 607 } 608 609 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 610 formats = vlv_primary_formats; 611 num_formats = ARRAY_SIZE(vlv_primary_formats); 612 } else if (INTEL_GEN(dev_priv) >= 4) { 613 /* 614 * WaFP16GammaEnabling:ivb 615 * "Workaround : When using the 64-bit format, the plane 616 * output on each color channel has one quarter amplitude. 617 * It can be brought up to full amplitude by using pipe 618 * gamma correction or pipe color space conversion to 619 * multiply the plane output by four." 620 * 621 * There is no dedicated plane gamma for the primary plane, 622 * and using the pipe gamma/csc could conflict with other 623 * planes, so we choose not to expose fp16 on IVB primary 624 * planes. HSW primary planes no longer have this problem. 625 */ 626 if (IS_IVYBRIDGE(dev_priv)) { 627 formats = ivb_primary_formats; 628 num_formats = ARRAY_SIZE(ivb_primary_formats); 629 } else { 630 formats = i965_primary_formats; 631 num_formats = ARRAY_SIZE(i965_primary_formats); 632 } 633 } else { 634 formats = i8xx_primary_formats; 635 num_formats = ARRAY_SIZE(i8xx_primary_formats); 636 } 637 638 if (INTEL_GEN(dev_priv) >= 4) 639 plane_funcs = &i965_plane_funcs; 640 else 641 plane_funcs = &i8xx_plane_funcs; 642 643 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 644 plane->min_cdclk = vlv_plane_min_cdclk; 645 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 646 plane->min_cdclk = hsw_plane_min_cdclk; 647 else if (IS_IVYBRIDGE(dev_priv)) 648 plane->min_cdclk = ivb_plane_min_cdclk; 649 else 650 plane->min_cdclk = i9xx_plane_min_cdclk; 651 652 plane->max_stride = i9xx_plane_max_stride; 653 plane->update_plane = i9xx_update_plane; 654 plane->disable_plane = i9xx_disable_plane; 655 plane->get_hw_state = i9xx_plane_get_hw_state; 656 plane->check_plane = i9xx_plane_check; 657 658 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) 659 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 660 0, plane_funcs, 661 formats, num_formats, 662 i9xx_format_modifiers, 663 DRM_PLANE_TYPE_PRIMARY, 664 "primary %c", pipe_name(pipe)); 665 else 666 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 667 0, plane_funcs, 668 formats, num_formats, 669 i9xx_format_modifiers, 670 DRM_PLANE_TYPE_PRIMARY, 671 "plane %c", 672 plane_name(plane->i9xx_plane)); 673 if (ret) 674 goto fail; 675 676 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 677 supported_rotations = 678 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | 679 DRM_MODE_REFLECT_X; 680 } else if (INTEL_GEN(dev_priv) >= 4) { 681 supported_rotations = 682 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 683 } else { 684 supported_rotations = DRM_MODE_ROTATE_0; 685 } 686 687 if (INTEL_GEN(dev_priv) >= 4) 688 drm_plane_create_rotation_property(&plane->base, 689 DRM_MODE_ROTATE_0, 690 supported_rotations); 691 692 zpos = 0; 693 drm_plane_create_zpos_immutable_property(&plane->base, zpos); 694 695 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); 696 697 return plane; 698 699 fail: 700 intel_plane_free(plane); 701 702 return ERR_PTR(ret); 703 } 704 705