1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 #include <linux/kernel.h> 6 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_blend.h> 9 #include <drm/drm_fourcc.h> 10 #include <drm/drm_plane_helper.h> 11 12 #include "intel_atomic.h" 13 #include "intel_atomic_plane.h" 14 #include "intel_de.h" 15 #include "intel_display_types.h" 16 #include "intel_fb.h" 17 #include "intel_fbc.h" 18 #include "intel_sprite.h" 19 #include "i9xx_plane.h" 20 21 /* Primary plane formats for gen <= 3 */ 22 static const u32 i8xx_primary_formats[] = { 23 DRM_FORMAT_C8, 24 DRM_FORMAT_XRGB1555, 25 DRM_FORMAT_RGB565, 26 DRM_FORMAT_XRGB8888, 27 }; 28 29 /* Primary plane formats for ivb (no fp16 due to hw issue) */ 30 static const u32 ivb_primary_formats[] = { 31 DRM_FORMAT_C8, 32 DRM_FORMAT_RGB565, 33 DRM_FORMAT_XRGB8888, 34 DRM_FORMAT_XBGR8888, 35 DRM_FORMAT_XRGB2101010, 36 DRM_FORMAT_XBGR2101010, 37 }; 38 39 /* Primary plane formats for gen >= 4, except ivb */ 40 static const u32 i965_primary_formats[] = { 41 DRM_FORMAT_C8, 42 DRM_FORMAT_RGB565, 43 DRM_FORMAT_XRGB8888, 44 DRM_FORMAT_XBGR8888, 45 DRM_FORMAT_XRGB2101010, 46 DRM_FORMAT_XBGR2101010, 47 DRM_FORMAT_XBGR16161616F, 48 }; 49 50 /* Primary plane formats for vlv/chv */ 51 static const u32 vlv_primary_formats[] = { 52 DRM_FORMAT_C8, 53 DRM_FORMAT_RGB565, 54 DRM_FORMAT_XRGB8888, 55 DRM_FORMAT_XBGR8888, 56 DRM_FORMAT_ARGB8888, 57 DRM_FORMAT_ABGR8888, 58 DRM_FORMAT_XRGB2101010, 59 DRM_FORMAT_XBGR2101010, 60 DRM_FORMAT_ARGB2101010, 61 DRM_FORMAT_ABGR2101010, 62 DRM_FORMAT_XBGR16161616F, 63 }; 64 65 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, 66 u32 format, u64 modifier) 67 { 68 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) 69 return false; 70 71 switch (format) { 72 case DRM_FORMAT_C8: 73 case DRM_FORMAT_RGB565: 74 case DRM_FORMAT_XRGB1555: 75 case DRM_FORMAT_XRGB8888: 76 return modifier == DRM_FORMAT_MOD_LINEAR || 77 modifier == I915_FORMAT_MOD_X_TILED; 78 default: 79 return false; 80 } 81 } 82 83 static bool i965_plane_format_mod_supported(struct drm_plane *_plane, 84 u32 format, u64 modifier) 85 { 86 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) 87 return false; 88 89 switch (format) { 90 case DRM_FORMAT_C8: 91 case DRM_FORMAT_RGB565: 92 case DRM_FORMAT_XRGB8888: 93 case DRM_FORMAT_XBGR8888: 94 case DRM_FORMAT_ARGB8888: 95 case DRM_FORMAT_ABGR8888: 96 case DRM_FORMAT_XRGB2101010: 97 case DRM_FORMAT_XBGR2101010: 98 case DRM_FORMAT_ARGB2101010: 99 case DRM_FORMAT_ABGR2101010: 100 case DRM_FORMAT_XBGR16161616F: 101 return modifier == DRM_FORMAT_MOD_LINEAR || 102 modifier == I915_FORMAT_MOD_X_TILED; 103 default: 104 return false; 105 } 106 } 107 108 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, 109 enum i9xx_plane_id i9xx_plane) 110 { 111 if (!HAS_FBC(dev_priv)) 112 return false; 113 114 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 115 return i9xx_plane == PLANE_A; /* tied to pipe A */ 116 else if (IS_IVYBRIDGE(dev_priv)) 117 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B || 118 i9xx_plane == PLANE_C; 119 else if (DISPLAY_VER(dev_priv) >= 4) 120 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B; 121 else 122 return i9xx_plane == PLANE_A; 123 } 124 125 static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv, 126 enum i9xx_plane_id i9xx_plane) 127 { 128 if (i9xx_plane_has_fbc(dev_priv, i9xx_plane)) 129 return dev_priv->fbc[INTEL_FBC_A]; 130 else 131 return NULL; 132 } 133 134 static bool i9xx_plane_has_windowing(struct intel_plane *plane) 135 { 136 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 137 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 138 139 if (IS_CHERRYVIEW(dev_priv)) 140 return i9xx_plane == PLANE_B; 141 else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 142 return false; 143 else if (DISPLAY_VER(dev_priv) == 4) 144 return i9xx_plane == PLANE_C; 145 else 146 return i9xx_plane == PLANE_B || 147 i9xx_plane == PLANE_C; 148 } 149 150 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, 151 const struct intel_plane_state *plane_state) 152 { 153 struct drm_i915_private *dev_priv = 154 to_i915(plane_state->uapi.plane->dev); 155 const struct drm_framebuffer *fb = plane_state->hw.fb; 156 unsigned int rotation = plane_state->hw.rotation; 157 u32 dspcntr; 158 159 dspcntr = DISP_ENABLE; 160 161 if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) || 162 IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) 163 dspcntr |= DISP_TRICKLE_FEED_DISABLE; 164 165 switch (fb->format->format) { 166 case DRM_FORMAT_C8: 167 dspcntr |= DISP_FORMAT_8BPP; 168 break; 169 case DRM_FORMAT_XRGB1555: 170 dspcntr |= DISP_FORMAT_BGRX555; 171 break; 172 case DRM_FORMAT_ARGB1555: 173 dspcntr |= DISP_FORMAT_BGRA555; 174 break; 175 case DRM_FORMAT_RGB565: 176 dspcntr |= DISP_FORMAT_BGRX565; 177 break; 178 case DRM_FORMAT_XRGB8888: 179 dspcntr |= DISP_FORMAT_BGRX888; 180 break; 181 case DRM_FORMAT_XBGR8888: 182 dspcntr |= DISP_FORMAT_RGBX888; 183 break; 184 case DRM_FORMAT_ARGB8888: 185 dspcntr |= DISP_FORMAT_BGRA888; 186 break; 187 case DRM_FORMAT_ABGR8888: 188 dspcntr |= DISP_FORMAT_RGBA888; 189 break; 190 case DRM_FORMAT_XRGB2101010: 191 dspcntr |= DISP_FORMAT_BGRX101010; 192 break; 193 case DRM_FORMAT_XBGR2101010: 194 dspcntr |= DISP_FORMAT_RGBX101010; 195 break; 196 case DRM_FORMAT_ARGB2101010: 197 dspcntr |= DISP_FORMAT_BGRA101010; 198 break; 199 case DRM_FORMAT_ABGR2101010: 200 dspcntr |= DISP_FORMAT_RGBA101010; 201 break; 202 case DRM_FORMAT_XBGR16161616F: 203 dspcntr |= DISP_FORMAT_RGBX161616; 204 break; 205 default: 206 MISSING_CASE(fb->format->format); 207 return 0; 208 } 209 210 if (DISPLAY_VER(dev_priv) >= 4 && 211 fb->modifier == I915_FORMAT_MOD_X_TILED) 212 dspcntr |= DISP_TILED; 213 214 if (rotation & DRM_MODE_ROTATE_180) 215 dspcntr |= DISP_ROTATE_180; 216 217 if (rotation & DRM_MODE_REFLECT_X) 218 dspcntr |= DISP_MIRROR; 219 220 return dspcntr; 221 } 222 223 int i9xx_check_plane_surface(struct intel_plane_state *plane_state) 224 { 225 struct drm_i915_private *dev_priv = 226 to_i915(plane_state->uapi.plane->dev); 227 const struct drm_framebuffer *fb = plane_state->hw.fb; 228 int src_x, src_y, src_w; 229 u32 offset; 230 int ret; 231 232 ret = intel_plane_compute_gtt(plane_state); 233 if (ret) 234 return ret; 235 236 if (!plane_state->uapi.visible) 237 return 0; 238 239 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 240 src_x = plane_state->uapi.src.x1 >> 16; 241 src_y = plane_state->uapi.src.y1 >> 16; 242 243 /* Undocumented hardware limit on i965/g4x/vlv/chv */ 244 if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048) 245 return -EINVAL; 246 247 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); 248 249 if (DISPLAY_VER(dev_priv) >= 4) 250 offset = intel_plane_compute_aligned_offset(&src_x, &src_y, 251 plane_state, 0); 252 else 253 offset = 0; 254 255 /* 256 * When using an X-tiled surface the plane starts to 257 * misbehave if the x offset + width exceeds the stride. 258 * hsw/bdw: underrun galore 259 * ilk/snb/ivb: wrap to the next tile row mid scanout 260 * i965/g4x: so far appear immune to this 261 * vlv/chv: TODO check 262 * 263 * Linear surfaces seem to work just fine, even on hsw/bdw 264 * despite them not using the linear offset anymore. 265 */ 266 if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { 267 u32 alignment = intel_surf_alignment(fb, 0); 268 int cpp = fb->format->cpp[0]; 269 270 while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) { 271 if (offset == 0) { 272 drm_dbg_kms(&dev_priv->drm, 273 "Unable to find suitable display surface offset due to X-tiling\n"); 274 return -EINVAL; 275 } 276 277 offset = intel_plane_adjust_aligned_offset(&src_x, &src_y, plane_state, 0, 278 offset, offset - alignment); 279 } 280 } 281 282 /* 283 * Put the final coordinates back so that the src 284 * coordinate checks will see the right values. 285 */ 286 drm_rect_translate_to(&plane_state->uapi.src, 287 src_x << 16, src_y << 16); 288 289 /* HSW/BDW do this automagically in hardware */ 290 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { 291 unsigned int rotation = plane_state->hw.rotation; 292 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 293 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 294 295 if (rotation & DRM_MODE_ROTATE_180) { 296 src_x += src_w - 1; 297 src_y += src_h - 1; 298 } else if (rotation & DRM_MODE_REFLECT_X) { 299 src_x += src_w - 1; 300 } 301 } 302 303 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 304 drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095); 305 } else if (DISPLAY_VER(dev_priv) >= 4 && 306 fb->modifier == I915_FORMAT_MOD_X_TILED) { 307 drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095); 308 } 309 310 plane_state->view.color_plane[0].offset = offset; 311 plane_state->view.color_plane[0].x = src_x; 312 plane_state->view.color_plane[0].y = src_y; 313 314 return 0; 315 } 316 317 static int 318 i9xx_plane_check(struct intel_crtc_state *crtc_state, 319 struct intel_plane_state *plane_state) 320 { 321 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 322 int ret; 323 324 ret = chv_plane_check_rotation(plane_state); 325 if (ret) 326 return ret; 327 328 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 329 DRM_PLANE_HELPER_NO_SCALING, 330 DRM_PLANE_HELPER_NO_SCALING, 331 i9xx_plane_has_windowing(plane)); 332 if (ret) 333 return ret; 334 335 ret = i9xx_check_plane_surface(plane_state); 336 if (ret) 337 return ret; 338 339 if (!plane_state->uapi.visible) 340 return 0; 341 342 ret = intel_plane_check_src_coordinates(plane_state); 343 if (ret) 344 return ret; 345 346 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state); 347 348 return 0; 349 } 350 351 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) 352 { 353 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 354 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 355 u32 dspcntr = 0; 356 357 if (crtc_state->gamma_enable) 358 dspcntr |= DISP_PIPE_GAMMA_ENABLE; 359 360 if (crtc_state->csc_enable) 361 dspcntr |= DISP_PIPE_CSC_ENABLE; 362 363 if (DISPLAY_VER(dev_priv) < 5) 364 dspcntr |= DISP_PIPE_SEL(crtc->pipe); 365 366 return dspcntr; 367 } 368 369 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state, 370 const struct intel_plane_state *plane_state, 371 unsigned int *num, unsigned int *den) 372 { 373 const struct drm_framebuffer *fb = plane_state->hw.fb; 374 unsigned int cpp = fb->format->cpp[0]; 375 376 /* 377 * g4x bspec says 64bpp pixel rate can't exceed 80% 378 * of cdclk when the sprite plane is enabled on the 379 * same pipe. ilk/snb bspec says 64bpp pixel rate is 380 * never allowed to exceed 80% of cdclk. Let's just go 381 * with the ilk/snb limit always. 382 */ 383 if (cpp == 8) { 384 *num = 10; 385 *den = 8; 386 } else { 387 *num = 1; 388 *den = 1; 389 } 390 } 391 392 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 393 const struct intel_plane_state *plane_state) 394 { 395 unsigned int pixel_rate; 396 unsigned int num, den; 397 398 /* 399 * Note that crtc_state->pixel_rate accounts for both 400 * horizontal and vertical panel fitter downscaling factors. 401 * Pre-HSW bspec tells us to only consider the horizontal 402 * downscaling factor here. We ignore that and just consider 403 * both for simplicity. 404 */ 405 pixel_rate = crtc_state->pixel_rate; 406 407 i9xx_plane_ratio(crtc_state, plane_state, &num, &den); 408 409 /* two pixels per clock with double wide pipe */ 410 if (crtc_state->double_wide) 411 den *= 2; 412 413 return DIV_ROUND_UP(pixel_rate * num, den); 414 } 415 416 static void i9xx_plane_update_noarm(struct intel_plane *plane, 417 const struct intel_crtc_state *crtc_state, 418 const struct intel_plane_state *plane_state) 419 { 420 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 421 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 422 423 intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), 424 plane_state->view.color_plane[0].mapping_stride); 425 426 if (DISPLAY_VER(dev_priv) < 4) { 427 int crtc_x = plane_state->uapi.dst.x1; 428 int crtc_y = plane_state->uapi.dst.y1; 429 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 430 int crtc_h = drm_rect_height(&plane_state->uapi.dst); 431 432 /* 433 * PLANE_A doesn't actually have a full window 434 * generator but let's assume we still need to 435 * program whatever is there. 436 */ 437 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), 438 DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x)); 439 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), 440 DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1)); 441 } 442 } 443 444 static void i9xx_plane_update_arm(struct intel_plane *plane, 445 const struct intel_crtc_state *crtc_state, 446 const struct intel_plane_state *plane_state) 447 { 448 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 449 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 450 int x = plane_state->view.color_plane[0].x; 451 int y = plane_state->view.color_plane[0].y; 452 u32 dspcntr, dspaddr_offset, linear_offset; 453 454 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); 455 456 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 457 458 if (DISPLAY_VER(dev_priv) >= 4) 459 dspaddr_offset = plane_state->view.color_plane[0].offset; 460 else 461 dspaddr_offset = linear_offset; 462 463 if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { 464 int crtc_x = plane_state->uapi.dst.x1; 465 int crtc_y = plane_state->uapi.dst.y1; 466 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 467 int crtc_h = drm_rect_height(&plane_state->uapi.dst); 468 469 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), 470 PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x)); 471 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), 472 PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); 473 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); 474 } 475 476 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 477 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), 478 DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); 479 } else if (DISPLAY_VER(dev_priv) >= 4) { 480 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), 481 linear_offset); 482 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), 483 DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); 484 } 485 486 /* 487 * The control register self-arms if the plane was previously 488 * disabled. Try to make the plane enable atomic by writing 489 * the control register just before the surface register. 490 */ 491 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); 492 493 if (DISPLAY_VER(dev_priv) >= 4) 494 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 495 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 496 else 497 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 498 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 499 } 500 501 static void i830_plane_update_arm(struct intel_plane *plane, 502 const struct intel_crtc_state *crtc_state, 503 const struct intel_plane_state *plane_state) 504 { 505 /* 506 * On i830/i845 all registers are self-arming [ALM040]. 507 * 508 * Additional breakage on i830 causes register reads to return 509 * the last latched value instead of the last written value [ALM026]. 510 */ 511 i9xx_plane_update_noarm(plane, crtc_state, plane_state); 512 i9xx_plane_update_arm(plane, crtc_state, plane_state); 513 } 514 515 static void i9xx_plane_disable_arm(struct intel_plane *plane, 516 const struct intel_crtc_state *crtc_state) 517 { 518 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 519 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 520 u32 dspcntr; 521 522 /* 523 * DSPCNTR pipe gamma enable on g4x+ and pipe csc 524 * enable on ilk+ affect the pipe bottom color as 525 * well, so we must configure them even if the plane 526 * is disabled. 527 * 528 * On pre-g4x there is no way to gamma correct the 529 * pipe bottom color but we'll keep on doing this 530 * anyway so that the crtc state readout works correctly. 531 */ 532 dspcntr = i9xx_plane_ctl_crtc(crtc_state); 533 534 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); 535 536 if (DISPLAY_VER(dev_priv) >= 4) 537 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); 538 else 539 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0); 540 } 541 542 static void 543 g4x_primary_async_flip(struct intel_plane *plane, 544 const struct intel_crtc_state *crtc_state, 545 const struct intel_plane_state *plane_state, 546 bool async_flip) 547 { 548 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 549 u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); 550 u32 dspaddr_offset = plane_state->view.color_plane[0].offset; 551 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 552 553 if (async_flip) 554 dspcntr |= DISP_ASYNC_FLIP; 555 556 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); 557 558 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 559 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 560 } 561 562 static void 563 vlv_primary_async_flip(struct intel_plane *plane, 564 const struct intel_crtc_state *crtc_state, 565 const struct intel_plane_state *plane_state, 566 bool async_flip) 567 { 568 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 569 u32 dspaddr_offset = plane_state->view.color_plane[0].offset; 570 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 571 572 intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane), 573 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 574 } 575 576 static void 577 bdw_primary_enable_flip_done(struct intel_plane *plane) 578 { 579 struct drm_i915_private *i915 = to_i915(plane->base.dev); 580 enum pipe pipe = plane->pipe; 581 582 spin_lock_irq(&i915->irq_lock); 583 bdw_enable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE); 584 spin_unlock_irq(&i915->irq_lock); 585 } 586 587 static void 588 bdw_primary_disable_flip_done(struct intel_plane *plane) 589 { 590 struct drm_i915_private *i915 = to_i915(plane->base.dev); 591 enum pipe pipe = plane->pipe; 592 593 spin_lock_irq(&i915->irq_lock); 594 bdw_disable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE); 595 spin_unlock_irq(&i915->irq_lock); 596 } 597 598 static void 599 ivb_primary_enable_flip_done(struct intel_plane *plane) 600 { 601 struct drm_i915_private *i915 = to_i915(plane->base.dev); 602 603 spin_lock_irq(&i915->irq_lock); 604 ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); 605 spin_unlock_irq(&i915->irq_lock); 606 } 607 608 static void 609 ivb_primary_disable_flip_done(struct intel_plane *plane) 610 { 611 struct drm_i915_private *i915 = to_i915(plane->base.dev); 612 613 spin_lock_irq(&i915->irq_lock); 614 ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); 615 spin_unlock_irq(&i915->irq_lock); 616 } 617 618 static void 619 ilk_primary_enable_flip_done(struct intel_plane *plane) 620 { 621 struct drm_i915_private *i915 = to_i915(plane->base.dev); 622 623 spin_lock_irq(&i915->irq_lock); 624 ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); 625 spin_unlock_irq(&i915->irq_lock); 626 } 627 628 static void 629 ilk_primary_disable_flip_done(struct intel_plane *plane) 630 { 631 struct drm_i915_private *i915 = to_i915(plane->base.dev); 632 633 spin_lock_irq(&i915->irq_lock); 634 ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); 635 spin_unlock_irq(&i915->irq_lock); 636 } 637 638 static void 639 vlv_primary_enable_flip_done(struct intel_plane *plane) 640 { 641 struct drm_i915_private *i915 = to_i915(plane->base.dev); 642 enum pipe pipe = plane->pipe; 643 644 spin_lock_irq(&i915->irq_lock); 645 i915_enable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV); 646 spin_unlock_irq(&i915->irq_lock); 647 } 648 649 static void 650 vlv_primary_disable_flip_done(struct intel_plane *plane) 651 { 652 struct drm_i915_private *i915 = to_i915(plane->base.dev); 653 enum pipe pipe = plane->pipe; 654 655 spin_lock_irq(&i915->irq_lock); 656 i915_disable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV); 657 spin_unlock_irq(&i915->irq_lock); 658 } 659 660 static bool i9xx_plane_get_hw_state(struct intel_plane *plane, 661 enum pipe *pipe) 662 { 663 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 664 enum intel_display_power_domain power_domain; 665 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 666 intel_wakeref_t wakeref; 667 bool ret; 668 u32 val; 669 670 /* 671 * Not 100% correct for planes that can move between pipes, 672 * but that's only the case for gen2-4 which don't have any 673 * display power wells. 674 */ 675 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 676 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 677 if (!wakeref) 678 return false; 679 680 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 681 682 ret = val & DISP_ENABLE; 683 684 if (DISPLAY_VER(dev_priv) >= 5) 685 *pipe = plane->pipe; 686 else 687 *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val); 688 689 intel_display_power_put(dev_priv, power_domain, wakeref); 690 691 return ret; 692 } 693 694 static unsigned int 695 hsw_primary_max_stride(struct intel_plane *plane, 696 u32 pixel_format, u64 modifier, 697 unsigned int rotation) 698 { 699 const struct drm_format_info *info = drm_format_info(pixel_format); 700 int cpp = info->cpp[0]; 701 702 /* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */ 703 return min(8192 * cpp, 32 * 1024); 704 } 705 706 static unsigned int 707 ilk_primary_max_stride(struct intel_plane *plane, 708 u32 pixel_format, u64 modifier, 709 unsigned int rotation) 710 { 711 const struct drm_format_info *info = drm_format_info(pixel_format); 712 int cpp = info->cpp[0]; 713 714 /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */ 715 if (modifier == I915_FORMAT_MOD_X_TILED) 716 return min(4096 * cpp, 32 * 1024); 717 else 718 return 32 * 1024; 719 } 720 721 unsigned int 722 i965_plane_max_stride(struct intel_plane *plane, 723 u32 pixel_format, u64 modifier, 724 unsigned int rotation) 725 { 726 const struct drm_format_info *info = drm_format_info(pixel_format); 727 int cpp = info->cpp[0]; 728 729 /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */ 730 if (modifier == I915_FORMAT_MOD_X_TILED) 731 return min(4096 * cpp, 16 * 1024); 732 else 733 return 32 * 1024; 734 } 735 736 static unsigned int 737 i9xx_plane_max_stride(struct intel_plane *plane, 738 u32 pixel_format, u64 modifier, 739 unsigned int rotation) 740 { 741 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 742 743 if (DISPLAY_VER(dev_priv) >= 3) { 744 if (modifier == I915_FORMAT_MOD_X_TILED) 745 return 8*1024; 746 else 747 return 16*1024; 748 } else { 749 if (plane->i9xx_plane == PLANE_C) 750 return 4*1024; 751 else 752 return 8*1024; 753 } 754 } 755 756 static const struct drm_plane_funcs i965_plane_funcs = { 757 .update_plane = drm_atomic_helper_update_plane, 758 .disable_plane = drm_atomic_helper_disable_plane, 759 .destroy = intel_plane_destroy, 760 .atomic_duplicate_state = intel_plane_duplicate_state, 761 .atomic_destroy_state = intel_plane_destroy_state, 762 .format_mod_supported = i965_plane_format_mod_supported, 763 }; 764 765 static const struct drm_plane_funcs i8xx_plane_funcs = { 766 .update_plane = drm_atomic_helper_update_plane, 767 .disable_plane = drm_atomic_helper_disable_plane, 768 .destroy = intel_plane_destroy, 769 .atomic_duplicate_state = intel_plane_duplicate_state, 770 .atomic_destroy_state = intel_plane_destroy_state, 771 .format_mod_supported = i8xx_plane_format_mod_supported, 772 }; 773 774 struct intel_plane * 775 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 776 { 777 struct intel_plane *plane; 778 const struct drm_plane_funcs *plane_funcs; 779 unsigned int supported_rotations; 780 const u64 *modifiers; 781 const u32 *formats; 782 int num_formats; 783 int ret, zpos; 784 785 plane = intel_plane_alloc(); 786 if (IS_ERR(plane)) 787 return plane; 788 789 plane->pipe = pipe; 790 /* 791 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS 792 * port is hooked to pipe B. Hence we want plane A feeding pipe B. 793 */ 794 if (HAS_FBC(dev_priv) && DISPLAY_VER(dev_priv) < 4 && 795 INTEL_NUM_PIPES(dev_priv) == 2) 796 plane->i9xx_plane = (enum i9xx_plane_id) !pipe; 797 else 798 plane->i9xx_plane = (enum i9xx_plane_id) pipe; 799 plane->id = PLANE_PRIMARY; 800 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); 801 802 intel_fbc_add_plane(i9xx_plane_fbc(dev_priv, plane->i9xx_plane), plane); 803 804 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 805 formats = vlv_primary_formats; 806 num_formats = ARRAY_SIZE(vlv_primary_formats); 807 } else if (DISPLAY_VER(dev_priv) >= 4) { 808 /* 809 * WaFP16GammaEnabling:ivb 810 * "Workaround : When using the 64-bit format, the plane 811 * output on each color channel has one quarter amplitude. 812 * It can be brought up to full amplitude by using pipe 813 * gamma correction or pipe color space conversion to 814 * multiply the plane output by four." 815 * 816 * There is no dedicated plane gamma for the primary plane, 817 * and using the pipe gamma/csc could conflict with other 818 * planes, so we choose not to expose fp16 on IVB primary 819 * planes. HSW primary planes no longer have this problem. 820 */ 821 if (IS_IVYBRIDGE(dev_priv)) { 822 formats = ivb_primary_formats; 823 num_formats = ARRAY_SIZE(ivb_primary_formats); 824 } else { 825 formats = i965_primary_formats; 826 num_formats = ARRAY_SIZE(i965_primary_formats); 827 } 828 } else { 829 formats = i8xx_primary_formats; 830 num_formats = ARRAY_SIZE(i8xx_primary_formats); 831 } 832 833 if (DISPLAY_VER(dev_priv) >= 4) 834 plane_funcs = &i965_plane_funcs; 835 else 836 plane_funcs = &i8xx_plane_funcs; 837 838 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 839 plane->min_cdclk = vlv_plane_min_cdclk; 840 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 841 plane->min_cdclk = hsw_plane_min_cdclk; 842 else if (IS_IVYBRIDGE(dev_priv)) 843 plane->min_cdclk = ivb_plane_min_cdclk; 844 else 845 plane->min_cdclk = i9xx_plane_min_cdclk; 846 847 if (HAS_GMCH(dev_priv)) { 848 if (DISPLAY_VER(dev_priv) >= 4) 849 plane->max_stride = i965_plane_max_stride; 850 else 851 plane->max_stride = i9xx_plane_max_stride; 852 } else { 853 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 854 plane->max_stride = hsw_primary_max_stride; 855 else 856 plane->max_stride = ilk_primary_max_stride; 857 } 858 859 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) { 860 plane->update_arm = i830_plane_update_arm; 861 } else { 862 plane->update_noarm = i9xx_plane_update_noarm; 863 plane->update_arm = i9xx_plane_update_arm; 864 } 865 plane->disable_arm = i9xx_plane_disable_arm; 866 plane->get_hw_state = i9xx_plane_get_hw_state; 867 plane->check_plane = i9xx_plane_check; 868 869 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 870 plane->async_flip = vlv_primary_async_flip; 871 plane->enable_flip_done = vlv_primary_enable_flip_done; 872 plane->disable_flip_done = vlv_primary_disable_flip_done; 873 } else if (IS_BROADWELL(dev_priv)) { 874 plane->need_async_flip_disable_wa = true; 875 plane->async_flip = g4x_primary_async_flip; 876 plane->enable_flip_done = bdw_primary_enable_flip_done; 877 plane->disable_flip_done = bdw_primary_disable_flip_done; 878 } else if (DISPLAY_VER(dev_priv) >= 7) { 879 plane->async_flip = g4x_primary_async_flip; 880 plane->enable_flip_done = ivb_primary_enable_flip_done; 881 plane->disable_flip_done = ivb_primary_disable_flip_done; 882 } else if (DISPLAY_VER(dev_priv) >= 5) { 883 plane->async_flip = g4x_primary_async_flip; 884 plane->enable_flip_done = ilk_primary_enable_flip_done; 885 plane->disable_flip_done = ilk_primary_disable_flip_done; 886 } 887 888 modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X); 889 890 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 891 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 892 0, plane_funcs, 893 formats, num_formats, 894 modifiers, 895 DRM_PLANE_TYPE_PRIMARY, 896 "primary %c", pipe_name(pipe)); 897 else 898 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 899 0, plane_funcs, 900 formats, num_formats, 901 modifiers, 902 DRM_PLANE_TYPE_PRIMARY, 903 "plane %c", 904 plane_name(plane->i9xx_plane)); 905 906 kfree(modifiers); 907 908 if (ret) 909 goto fail; 910 911 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 912 supported_rotations = 913 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | 914 DRM_MODE_REFLECT_X; 915 } else if (DISPLAY_VER(dev_priv) >= 4) { 916 supported_rotations = 917 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 918 } else { 919 supported_rotations = DRM_MODE_ROTATE_0; 920 } 921 922 if (DISPLAY_VER(dev_priv) >= 4) 923 drm_plane_create_rotation_property(&plane->base, 924 DRM_MODE_ROTATE_0, 925 supported_rotations); 926 927 zpos = 0; 928 drm_plane_create_zpos_immutable_property(&plane->base, zpos); 929 930 intel_plane_helper_add(plane); 931 932 return plane; 933 934 fail: 935 intel_plane_free(plane); 936 937 return ERR_PTR(ret); 938 } 939 940 static int i9xx_format_to_fourcc(int format) 941 { 942 switch (format) { 943 case DISP_FORMAT_8BPP: 944 return DRM_FORMAT_C8; 945 case DISP_FORMAT_BGRA555: 946 return DRM_FORMAT_ARGB1555; 947 case DISP_FORMAT_BGRX555: 948 return DRM_FORMAT_XRGB1555; 949 case DISP_FORMAT_BGRX565: 950 return DRM_FORMAT_RGB565; 951 default: 952 case DISP_FORMAT_BGRX888: 953 return DRM_FORMAT_XRGB8888; 954 case DISP_FORMAT_RGBX888: 955 return DRM_FORMAT_XBGR8888; 956 case DISP_FORMAT_BGRA888: 957 return DRM_FORMAT_ARGB8888; 958 case DISP_FORMAT_RGBA888: 959 return DRM_FORMAT_ABGR8888; 960 case DISP_FORMAT_BGRX101010: 961 return DRM_FORMAT_XRGB2101010; 962 case DISP_FORMAT_RGBX101010: 963 return DRM_FORMAT_XBGR2101010; 964 case DISP_FORMAT_BGRA101010: 965 return DRM_FORMAT_ARGB2101010; 966 case DISP_FORMAT_RGBA101010: 967 return DRM_FORMAT_ABGR2101010; 968 case DISP_FORMAT_RGBX161616: 969 return DRM_FORMAT_XBGR16161616F; 970 } 971 } 972 973 void 974 i9xx_get_initial_plane_config(struct intel_crtc *crtc, 975 struct intel_initial_plane_config *plane_config) 976 { 977 struct drm_device *dev = crtc->base.dev; 978 struct drm_i915_private *dev_priv = to_i915(dev); 979 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 980 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 981 enum pipe pipe; 982 u32 val, base, offset; 983 int fourcc, pixel_format; 984 unsigned int aligned_height; 985 struct drm_framebuffer *fb; 986 struct intel_framebuffer *intel_fb; 987 988 if (!plane->get_hw_state(plane, &pipe)) 989 return; 990 991 drm_WARN_ON(dev, pipe != crtc->pipe); 992 993 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 994 if (!intel_fb) { 995 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); 996 return; 997 } 998 999 fb = &intel_fb->base; 1000 1001 fb->dev = dev; 1002 1003 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 1004 1005 if (DISPLAY_VER(dev_priv) >= 4) { 1006 if (val & DISP_TILED) { 1007 plane_config->tiling = I915_TILING_X; 1008 fb->modifier = I915_FORMAT_MOD_X_TILED; 1009 } 1010 1011 if (val & DISP_ROTATE_180) 1012 plane_config->rotation = DRM_MODE_ROTATE_180; 1013 } 1014 1015 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && 1016 val & DISP_MIRROR) 1017 plane_config->rotation |= DRM_MODE_REFLECT_X; 1018 1019 pixel_format = val & DISP_FORMAT_MASK; 1020 fourcc = i9xx_format_to_fourcc(pixel_format); 1021 fb->format = drm_format_info(fourcc); 1022 1023 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 1024 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane)); 1025 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; 1026 } else if (DISPLAY_VER(dev_priv) >= 4) { 1027 if (plane_config->tiling) 1028 offset = intel_de_read(dev_priv, 1029 DSPTILEOFF(i9xx_plane)); 1030 else 1031 offset = intel_de_read(dev_priv, 1032 DSPLINOFF(i9xx_plane)); 1033 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; 1034 } else { 1035 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane)); 1036 } 1037 plane_config->base = base; 1038 1039 val = intel_de_read(dev_priv, PIPESRC(pipe)); 1040 fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1; 1041 fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1; 1042 1043 val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane)); 1044 fb->pitches[0] = val & 0xffffffc0; 1045 1046 aligned_height = intel_fb_align_height(fb, 0, fb->height); 1047 1048 plane_config->size = fb->pitches[0] * aligned_height; 1049 1050 drm_dbg_kms(&dev_priv->drm, 1051 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 1052 crtc->base.name, plane->base.name, fb->width, fb->height, 1053 fb->format->cpp[0] * 8, base, fb->pitches[0], 1054 plane_config->size); 1055 1056 plane_config->fb = intel_fb; 1057 } 1058