1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 #include <linux/kernel.h> 6 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_fourcc.h> 9 #include <drm/drm_plane_helper.h> 10 11 #include "intel_atomic.h" 12 #include "intel_atomic_plane.h" 13 #include "intel_de.h" 14 #include "intel_display_types.h" 15 #include "intel_fb.h" 16 #include "intel_fbc.h" 17 #include "intel_sprite.h" 18 #include "i9xx_plane.h" 19 20 /* Primary plane formats for gen <= 3 */ 21 static const u32 i8xx_primary_formats[] = { 22 DRM_FORMAT_C8, 23 DRM_FORMAT_XRGB1555, 24 DRM_FORMAT_RGB565, 25 DRM_FORMAT_XRGB8888, 26 }; 27 28 /* Primary plane formats for ivb (no fp16 due to hw issue) */ 29 static const u32 ivb_primary_formats[] = { 30 DRM_FORMAT_C8, 31 DRM_FORMAT_RGB565, 32 DRM_FORMAT_XRGB8888, 33 DRM_FORMAT_XBGR8888, 34 DRM_FORMAT_XRGB2101010, 35 DRM_FORMAT_XBGR2101010, 36 }; 37 38 /* Primary plane formats for gen >= 4, except ivb */ 39 static const u32 i965_primary_formats[] = { 40 DRM_FORMAT_C8, 41 DRM_FORMAT_RGB565, 42 DRM_FORMAT_XRGB8888, 43 DRM_FORMAT_XBGR8888, 44 DRM_FORMAT_XRGB2101010, 45 DRM_FORMAT_XBGR2101010, 46 DRM_FORMAT_XBGR16161616F, 47 }; 48 49 /* Primary plane formats for vlv/chv */ 50 static const u32 vlv_primary_formats[] = { 51 DRM_FORMAT_C8, 52 DRM_FORMAT_RGB565, 53 DRM_FORMAT_XRGB8888, 54 DRM_FORMAT_XBGR8888, 55 DRM_FORMAT_ARGB8888, 56 DRM_FORMAT_ABGR8888, 57 DRM_FORMAT_XRGB2101010, 58 DRM_FORMAT_XBGR2101010, 59 DRM_FORMAT_ARGB2101010, 60 DRM_FORMAT_ABGR2101010, 61 DRM_FORMAT_XBGR16161616F, 62 }; 63 64 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, 65 u32 format, u64 modifier) 66 { 67 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) 68 return false; 69 70 switch (format) { 71 case DRM_FORMAT_C8: 72 case DRM_FORMAT_RGB565: 73 case DRM_FORMAT_XRGB1555: 74 case DRM_FORMAT_XRGB8888: 75 return modifier == DRM_FORMAT_MOD_LINEAR || 76 modifier == I915_FORMAT_MOD_X_TILED; 77 default: 78 return false; 79 } 80 } 81 82 static bool i965_plane_format_mod_supported(struct drm_plane *_plane, 83 u32 format, u64 modifier) 84 { 85 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) 86 return false; 87 88 switch (format) { 89 case DRM_FORMAT_C8: 90 case DRM_FORMAT_RGB565: 91 case DRM_FORMAT_XRGB8888: 92 case DRM_FORMAT_XBGR8888: 93 case DRM_FORMAT_ARGB8888: 94 case DRM_FORMAT_ABGR8888: 95 case DRM_FORMAT_XRGB2101010: 96 case DRM_FORMAT_XBGR2101010: 97 case DRM_FORMAT_ARGB2101010: 98 case DRM_FORMAT_ABGR2101010: 99 case DRM_FORMAT_XBGR16161616F: 100 return modifier == DRM_FORMAT_MOD_LINEAR || 101 modifier == I915_FORMAT_MOD_X_TILED; 102 default: 103 return false; 104 } 105 } 106 107 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, 108 enum i9xx_plane_id i9xx_plane) 109 { 110 if (!HAS_FBC(dev_priv)) 111 return false; 112 113 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 114 return i9xx_plane == PLANE_A; /* tied to pipe A */ 115 else if (IS_IVYBRIDGE(dev_priv)) 116 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B || 117 i9xx_plane == PLANE_C; 118 else if (DISPLAY_VER(dev_priv) >= 4) 119 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B; 120 else 121 return i9xx_plane == PLANE_A; 122 } 123 124 static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv, 125 enum i9xx_plane_id i9xx_plane) 126 { 127 if (i9xx_plane_has_fbc(dev_priv, i9xx_plane)) 128 return dev_priv->fbc[INTEL_FBC_A]; 129 else 130 return NULL; 131 } 132 133 static bool i9xx_plane_has_windowing(struct intel_plane *plane) 134 { 135 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 136 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 137 138 if (IS_CHERRYVIEW(dev_priv)) 139 return i9xx_plane == PLANE_B; 140 else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 141 return false; 142 else if (DISPLAY_VER(dev_priv) == 4) 143 return i9xx_plane == PLANE_C; 144 else 145 return i9xx_plane == PLANE_B || 146 i9xx_plane == PLANE_C; 147 } 148 149 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, 150 const struct intel_plane_state *plane_state) 151 { 152 struct drm_i915_private *dev_priv = 153 to_i915(plane_state->uapi.plane->dev); 154 const struct drm_framebuffer *fb = plane_state->hw.fb; 155 unsigned int rotation = plane_state->hw.rotation; 156 u32 dspcntr; 157 158 dspcntr = DISP_ENABLE; 159 160 if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) || 161 IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) 162 dspcntr |= DISP_TRICKLE_FEED_DISABLE; 163 164 switch (fb->format->format) { 165 case DRM_FORMAT_C8: 166 dspcntr |= DISP_FORMAT_8BPP; 167 break; 168 case DRM_FORMAT_XRGB1555: 169 dspcntr |= DISP_FORMAT_BGRX555; 170 break; 171 case DRM_FORMAT_ARGB1555: 172 dspcntr |= DISP_FORMAT_BGRA555; 173 break; 174 case DRM_FORMAT_RGB565: 175 dspcntr |= DISP_FORMAT_BGRX565; 176 break; 177 case DRM_FORMAT_XRGB8888: 178 dspcntr |= DISP_FORMAT_BGRX888; 179 break; 180 case DRM_FORMAT_XBGR8888: 181 dspcntr |= DISP_FORMAT_RGBX888; 182 break; 183 case DRM_FORMAT_ARGB8888: 184 dspcntr |= DISP_FORMAT_BGRA888; 185 break; 186 case DRM_FORMAT_ABGR8888: 187 dspcntr |= DISP_FORMAT_RGBA888; 188 break; 189 case DRM_FORMAT_XRGB2101010: 190 dspcntr |= DISP_FORMAT_BGRX101010; 191 break; 192 case DRM_FORMAT_XBGR2101010: 193 dspcntr |= DISP_FORMAT_RGBX101010; 194 break; 195 case DRM_FORMAT_ARGB2101010: 196 dspcntr |= DISP_FORMAT_BGRA101010; 197 break; 198 case DRM_FORMAT_ABGR2101010: 199 dspcntr |= DISP_FORMAT_RGBA101010; 200 break; 201 case DRM_FORMAT_XBGR16161616F: 202 dspcntr |= DISP_FORMAT_RGBX161616; 203 break; 204 default: 205 MISSING_CASE(fb->format->format); 206 return 0; 207 } 208 209 if (DISPLAY_VER(dev_priv) >= 4 && 210 fb->modifier == I915_FORMAT_MOD_X_TILED) 211 dspcntr |= DISP_TILED; 212 213 if (rotation & DRM_MODE_ROTATE_180) 214 dspcntr |= DISP_ROTATE_180; 215 216 if (rotation & DRM_MODE_REFLECT_X) 217 dspcntr |= DISP_MIRROR; 218 219 return dspcntr; 220 } 221 222 int i9xx_check_plane_surface(struct intel_plane_state *plane_state) 223 { 224 struct drm_i915_private *dev_priv = 225 to_i915(plane_state->uapi.plane->dev); 226 const struct drm_framebuffer *fb = plane_state->hw.fb; 227 int src_x, src_y, src_w; 228 u32 offset; 229 int ret; 230 231 ret = intel_plane_compute_gtt(plane_state); 232 if (ret) 233 return ret; 234 235 if (!plane_state->uapi.visible) 236 return 0; 237 238 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 239 src_x = plane_state->uapi.src.x1 >> 16; 240 src_y = plane_state->uapi.src.y1 >> 16; 241 242 /* Undocumented hardware limit on i965/g4x/vlv/chv */ 243 if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048) 244 return -EINVAL; 245 246 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); 247 248 if (DISPLAY_VER(dev_priv) >= 4) 249 offset = intel_plane_compute_aligned_offset(&src_x, &src_y, 250 plane_state, 0); 251 else 252 offset = 0; 253 254 /* 255 * When using an X-tiled surface the plane starts to 256 * misbehave if the x offset + width exceeds the stride. 257 * hsw/bdw: underrun galore 258 * ilk/snb/ivb: wrap to the next tile row mid scanout 259 * i965/g4x: so far appear immune to this 260 * vlv/chv: TODO check 261 * 262 * Linear surfaces seem to work just fine, even on hsw/bdw 263 * despite them not using the linear offset anymore. 264 */ 265 if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { 266 u32 alignment = intel_surf_alignment(fb, 0); 267 int cpp = fb->format->cpp[0]; 268 269 while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) { 270 if (offset == 0) { 271 drm_dbg_kms(&dev_priv->drm, 272 "Unable to find suitable display surface offset due to X-tiling\n"); 273 return -EINVAL; 274 } 275 276 offset = intel_plane_adjust_aligned_offset(&src_x, &src_y, plane_state, 0, 277 offset, offset - alignment); 278 } 279 } 280 281 /* 282 * Put the final coordinates back so that the src 283 * coordinate checks will see the right values. 284 */ 285 drm_rect_translate_to(&plane_state->uapi.src, 286 src_x << 16, src_y << 16); 287 288 /* HSW/BDW do this automagically in hardware */ 289 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { 290 unsigned int rotation = plane_state->hw.rotation; 291 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 292 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 293 294 if (rotation & DRM_MODE_ROTATE_180) { 295 src_x += src_w - 1; 296 src_y += src_h - 1; 297 } else if (rotation & DRM_MODE_REFLECT_X) { 298 src_x += src_w - 1; 299 } 300 } 301 302 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 303 drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095); 304 } else if (DISPLAY_VER(dev_priv) >= 4 && 305 fb->modifier == I915_FORMAT_MOD_X_TILED) { 306 drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095); 307 } 308 309 plane_state->view.color_plane[0].offset = offset; 310 plane_state->view.color_plane[0].x = src_x; 311 plane_state->view.color_plane[0].y = src_y; 312 313 return 0; 314 } 315 316 static int 317 i9xx_plane_check(struct intel_crtc_state *crtc_state, 318 struct intel_plane_state *plane_state) 319 { 320 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 321 int ret; 322 323 ret = chv_plane_check_rotation(plane_state); 324 if (ret) 325 return ret; 326 327 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 328 DRM_PLANE_HELPER_NO_SCALING, 329 DRM_PLANE_HELPER_NO_SCALING, 330 i9xx_plane_has_windowing(plane)); 331 if (ret) 332 return ret; 333 334 ret = i9xx_check_plane_surface(plane_state); 335 if (ret) 336 return ret; 337 338 if (!plane_state->uapi.visible) 339 return 0; 340 341 ret = intel_plane_check_src_coordinates(plane_state); 342 if (ret) 343 return ret; 344 345 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state); 346 347 return 0; 348 } 349 350 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) 351 { 352 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 353 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 354 u32 dspcntr = 0; 355 356 if (crtc_state->gamma_enable) 357 dspcntr |= DISP_PIPE_GAMMA_ENABLE; 358 359 if (crtc_state->csc_enable) 360 dspcntr |= DISP_PIPE_CSC_ENABLE; 361 362 if (DISPLAY_VER(dev_priv) < 5) 363 dspcntr |= DISP_PIPE_SEL(crtc->pipe); 364 365 return dspcntr; 366 } 367 368 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state, 369 const struct intel_plane_state *plane_state, 370 unsigned int *num, unsigned int *den) 371 { 372 const struct drm_framebuffer *fb = plane_state->hw.fb; 373 unsigned int cpp = fb->format->cpp[0]; 374 375 /* 376 * g4x bspec says 64bpp pixel rate can't exceed 80% 377 * of cdclk when the sprite plane is enabled on the 378 * same pipe. ilk/snb bspec says 64bpp pixel rate is 379 * never allowed to exceed 80% of cdclk. Let's just go 380 * with the ilk/snb limit always. 381 */ 382 if (cpp == 8) { 383 *num = 10; 384 *den = 8; 385 } else { 386 *num = 1; 387 *den = 1; 388 } 389 } 390 391 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 392 const struct intel_plane_state *plane_state) 393 { 394 unsigned int pixel_rate; 395 unsigned int num, den; 396 397 /* 398 * Note that crtc_state->pixel_rate accounts for both 399 * horizontal and vertical panel fitter downscaling factors. 400 * Pre-HSW bspec tells us to only consider the horizontal 401 * downscaling factor here. We ignore that and just consider 402 * both for simplicity. 403 */ 404 pixel_rate = crtc_state->pixel_rate; 405 406 i9xx_plane_ratio(crtc_state, plane_state, &num, &den); 407 408 /* two pixels per clock with double wide pipe */ 409 if (crtc_state->double_wide) 410 den *= 2; 411 412 return DIV_ROUND_UP(pixel_rate * num, den); 413 } 414 415 static void i9xx_plane_update_noarm(struct intel_plane *plane, 416 const struct intel_crtc_state *crtc_state, 417 const struct intel_plane_state *plane_state) 418 { 419 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 420 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 421 unsigned long irqflags; 422 423 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 424 425 intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), 426 plane_state->view.color_plane[0].mapping_stride); 427 428 if (DISPLAY_VER(dev_priv) < 4) { 429 int crtc_x = plane_state->uapi.dst.x1; 430 int crtc_y = plane_state->uapi.dst.y1; 431 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 432 int crtc_h = drm_rect_height(&plane_state->uapi.dst); 433 434 /* 435 * PLANE_A doesn't actually have a full window 436 * generator but let's assume we still need to 437 * program whatever is there. 438 */ 439 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), 440 DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x)); 441 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), 442 DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1)); 443 } 444 445 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 446 } 447 448 static void i9xx_plane_update_arm(struct intel_plane *plane, 449 const struct intel_crtc_state *crtc_state, 450 const struct intel_plane_state *plane_state) 451 { 452 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 453 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 454 int x = plane_state->view.color_plane[0].x; 455 int y = plane_state->view.color_plane[0].y; 456 u32 dspcntr, dspaddr_offset, linear_offset; 457 unsigned long irqflags; 458 459 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); 460 461 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 462 463 if (DISPLAY_VER(dev_priv) >= 4) 464 dspaddr_offset = plane_state->view.color_plane[0].offset; 465 else 466 dspaddr_offset = linear_offset; 467 468 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 469 470 if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { 471 int crtc_x = plane_state->uapi.dst.x1; 472 int crtc_y = plane_state->uapi.dst.y1; 473 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 474 int crtc_h = drm_rect_height(&plane_state->uapi.dst); 475 476 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), 477 PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x)); 478 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), 479 PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); 480 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); 481 } 482 483 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 484 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), 485 DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); 486 } else if (DISPLAY_VER(dev_priv) >= 4) { 487 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), 488 linear_offset); 489 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), 490 DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); 491 } 492 493 /* 494 * The control register self-arms if the plane was previously 495 * disabled. Try to make the plane enable atomic by writing 496 * the control register just before the surface register. 497 */ 498 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); 499 if (DISPLAY_VER(dev_priv) >= 4) 500 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 501 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 502 else 503 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 504 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 505 506 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 507 } 508 509 static void i830_plane_update_arm(struct intel_plane *plane, 510 const struct intel_crtc_state *crtc_state, 511 const struct intel_plane_state *plane_state) 512 { 513 /* 514 * On i830/i845 all registers are self-arming [ALM040]. 515 * 516 * Additional breakage on i830 causes register reads to return 517 * the last latched value instead of the last written value [ALM026]. 518 */ 519 i9xx_plane_update_noarm(plane, crtc_state, plane_state); 520 i9xx_plane_update_arm(plane, crtc_state, plane_state); 521 } 522 523 static void i9xx_plane_disable_arm(struct intel_plane *plane, 524 const struct intel_crtc_state *crtc_state) 525 { 526 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 527 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 528 unsigned long irqflags; 529 u32 dspcntr; 530 531 /* 532 * DSPCNTR pipe gamma enable on g4x+ and pipe csc 533 * enable on ilk+ affect the pipe bottom color as 534 * well, so we must configure them even if the plane 535 * is disabled. 536 * 537 * On pre-g4x there is no way to gamma correct the 538 * pipe bottom color but we'll keep on doing this 539 * anyway so that the crtc state readout works correctly. 540 */ 541 dspcntr = i9xx_plane_ctl_crtc(crtc_state); 542 543 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 544 545 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); 546 if (DISPLAY_VER(dev_priv) >= 4) 547 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); 548 else 549 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0); 550 551 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 552 } 553 554 static void 555 g4x_primary_async_flip(struct intel_plane *plane, 556 const struct intel_crtc_state *crtc_state, 557 const struct intel_plane_state *plane_state, 558 bool async_flip) 559 { 560 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 561 u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); 562 u32 dspaddr_offset = plane_state->view.color_plane[0].offset; 563 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 564 unsigned long irqflags; 565 566 if (async_flip) 567 dspcntr |= DISP_ASYNC_FLIP; 568 569 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 570 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); 571 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 572 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 573 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 574 } 575 576 static void 577 vlv_primary_async_flip(struct intel_plane *plane, 578 const struct intel_crtc_state *crtc_state, 579 const struct intel_plane_state *plane_state, 580 bool async_flip) 581 { 582 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 583 u32 dspaddr_offset = plane_state->view.color_plane[0].offset; 584 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 585 unsigned long irqflags; 586 587 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 588 intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane), 589 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 590 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 591 } 592 593 static void 594 bdw_primary_enable_flip_done(struct intel_plane *plane) 595 { 596 struct drm_i915_private *i915 = to_i915(plane->base.dev); 597 enum pipe pipe = plane->pipe; 598 599 spin_lock_irq(&i915->irq_lock); 600 bdw_enable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE); 601 spin_unlock_irq(&i915->irq_lock); 602 } 603 604 static void 605 bdw_primary_disable_flip_done(struct intel_plane *plane) 606 { 607 struct drm_i915_private *i915 = to_i915(plane->base.dev); 608 enum pipe pipe = plane->pipe; 609 610 spin_lock_irq(&i915->irq_lock); 611 bdw_disable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE); 612 spin_unlock_irq(&i915->irq_lock); 613 } 614 615 static void 616 ivb_primary_enable_flip_done(struct intel_plane *plane) 617 { 618 struct drm_i915_private *i915 = to_i915(plane->base.dev); 619 620 spin_lock_irq(&i915->irq_lock); 621 ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); 622 spin_unlock_irq(&i915->irq_lock); 623 } 624 625 static void 626 ivb_primary_disable_flip_done(struct intel_plane *plane) 627 { 628 struct drm_i915_private *i915 = to_i915(plane->base.dev); 629 630 spin_lock_irq(&i915->irq_lock); 631 ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); 632 spin_unlock_irq(&i915->irq_lock); 633 } 634 635 static void 636 ilk_primary_enable_flip_done(struct intel_plane *plane) 637 { 638 struct drm_i915_private *i915 = to_i915(plane->base.dev); 639 640 spin_lock_irq(&i915->irq_lock); 641 ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); 642 spin_unlock_irq(&i915->irq_lock); 643 } 644 645 static void 646 ilk_primary_disable_flip_done(struct intel_plane *plane) 647 { 648 struct drm_i915_private *i915 = to_i915(plane->base.dev); 649 650 spin_lock_irq(&i915->irq_lock); 651 ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); 652 spin_unlock_irq(&i915->irq_lock); 653 } 654 655 static void 656 vlv_primary_enable_flip_done(struct intel_plane *plane) 657 { 658 struct drm_i915_private *i915 = to_i915(plane->base.dev); 659 enum pipe pipe = plane->pipe; 660 661 spin_lock_irq(&i915->irq_lock); 662 i915_enable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV); 663 spin_unlock_irq(&i915->irq_lock); 664 } 665 666 static void 667 vlv_primary_disable_flip_done(struct intel_plane *plane) 668 { 669 struct drm_i915_private *i915 = to_i915(plane->base.dev); 670 enum pipe pipe = plane->pipe; 671 672 spin_lock_irq(&i915->irq_lock); 673 i915_disable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV); 674 spin_unlock_irq(&i915->irq_lock); 675 } 676 677 static bool i9xx_plane_get_hw_state(struct intel_plane *plane, 678 enum pipe *pipe) 679 { 680 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 681 enum intel_display_power_domain power_domain; 682 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 683 intel_wakeref_t wakeref; 684 bool ret; 685 u32 val; 686 687 /* 688 * Not 100% correct for planes that can move between pipes, 689 * but that's only the case for gen2-4 which don't have any 690 * display power wells. 691 */ 692 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 693 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 694 if (!wakeref) 695 return false; 696 697 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 698 699 ret = val & DISP_ENABLE; 700 701 if (DISPLAY_VER(dev_priv) >= 5) 702 *pipe = plane->pipe; 703 else 704 *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val); 705 706 intel_display_power_put(dev_priv, power_domain, wakeref); 707 708 return ret; 709 } 710 711 static unsigned int 712 hsw_primary_max_stride(struct intel_plane *plane, 713 u32 pixel_format, u64 modifier, 714 unsigned int rotation) 715 { 716 const struct drm_format_info *info = drm_format_info(pixel_format); 717 int cpp = info->cpp[0]; 718 719 /* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */ 720 return min(8192 * cpp, 32 * 1024); 721 } 722 723 static unsigned int 724 ilk_primary_max_stride(struct intel_plane *plane, 725 u32 pixel_format, u64 modifier, 726 unsigned int rotation) 727 { 728 const struct drm_format_info *info = drm_format_info(pixel_format); 729 int cpp = info->cpp[0]; 730 731 /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */ 732 if (modifier == I915_FORMAT_MOD_X_TILED) 733 return min(4096 * cpp, 32 * 1024); 734 else 735 return 32 * 1024; 736 } 737 738 unsigned int 739 i965_plane_max_stride(struct intel_plane *plane, 740 u32 pixel_format, u64 modifier, 741 unsigned int rotation) 742 { 743 const struct drm_format_info *info = drm_format_info(pixel_format); 744 int cpp = info->cpp[0]; 745 746 /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */ 747 if (modifier == I915_FORMAT_MOD_X_TILED) 748 return min(4096 * cpp, 16 * 1024); 749 else 750 return 32 * 1024; 751 } 752 753 static unsigned int 754 i9xx_plane_max_stride(struct intel_plane *plane, 755 u32 pixel_format, u64 modifier, 756 unsigned int rotation) 757 { 758 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 759 760 if (DISPLAY_VER(dev_priv) >= 3) { 761 if (modifier == I915_FORMAT_MOD_X_TILED) 762 return 8*1024; 763 else 764 return 16*1024; 765 } else { 766 if (plane->i9xx_plane == PLANE_C) 767 return 4*1024; 768 else 769 return 8*1024; 770 } 771 } 772 773 static const struct drm_plane_funcs i965_plane_funcs = { 774 .update_plane = drm_atomic_helper_update_plane, 775 .disable_plane = drm_atomic_helper_disable_plane, 776 .destroy = intel_plane_destroy, 777 .atomic_duplicate_state = intel_plane_duplicate_state, 778 .atomic_destroy_state = intel_plane_destroy_state, 779 .format_mod_supported = i965_plane_format_mod_supported, 780 }; 781 782 static const struct drm_plane_funcs i8xx_plane_funcs = { 783 .update_plane = drm_atomic_helper_update_plane, 784 .disable_plane = drm_atomic_helper_disable_plane, 785 .destroy = intel_plane_destroy, 786 .atomic_duplicate_state = intel_plane_duplicate_state, 787 .atomic_destroy_state = intel_plane_destroy_state, 788 .format_mod_supported = i8xx_plane_format_mod_supported, 789 }; 790 791 struct intel_plane * 792 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 793 { 794 struct intel_plane *plane; 795 const struct drm_plane_funcs *plane_funcs; 796 unsigned int supported_rotations; 797 const u64 *modifiers; 798 const u32 *formats; 799 int num_formats; 800 int ret, zpos; 801 802 plane = intel_plane_alloc(); 803 if (IS_ERR(plane)) 804 return plane; 805 806 plane->pipe = pipe; 807 /* 808 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS 809 * port is hooked to pipe B. Hence we want plane A feeding pipe B. 810 */ 811 if (HAS_FBC(dev_priv) && DISPLAY_VER(dev_priv) < 4 && 812 INTEL_NUM_PIPES(dev_priv) == 2) 813 plane->i9xx_plane = (enum i9xx_plane_id) !pipe; 814 else 815 plane->i9xx_plane = (enum i9xx_plane_id) pipe; 816 plane->id = PLANE_PRIMARY; 817 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); 818 819 intel_fbc_add_plane(i9xx_plane_fbc(dev_priv, plane->i9xx_plane), plane); 820 821 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 822 formats = vlv_primary_formats; 823 num_formats = ARRAY_SIZE(vlv_primary_formats); 824 } else if (DISPLAY_VER(dev_priv) >= 4) { 825 /* 826 * WaFP16GammaEnabling:ivb 827 * "Workaround : When using the 64-bit format, the plane 828 * output on each color channel has one quarter amplitude. 829 * It can be brought up to full amplitude by using pipe 830 * gamma correction or pipe color space conversion to 831 * multiply the plane output by four." 832 * 833 * There is no dedicated plane gamma for the primary plane, 834 * and using the pipe gamma/csc could conflict with other 835 * planes, so we choose not to expose fp16 on IVB primary 836 * planes. HSW primary planes no longer have this problem. 837 */ 838 if (IS_IVYBRIDGE(dev_priv)) { 839 formats = ivb_primary_formats; 840 num_formats = ARRAY_SIZE(ivb_primary_formats); 841 } else { 842 formats = i965_primary_formats; 843 num_formats = ARRAY_SIZE(i965_primary_formats); 844 } 845 } else { 846 formats = i8xx_primary_formats; 847 num_formats = ARRAY_SIZE(i8xx_primary_formats); 848 } 849 850 if (DISPLAY_VER(dev_priv) >= 4) 851 plane_funcs = &i965_plane_funcs; 852 else 853 plane_funcs = &i8xx_plane_funcs; 854 855 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 856 plane->min_cdclk = vlv_plane_min_cdclk; 857 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 858 plane->min_cdclk = hsw_plane_min_cdclk; 859 else if (IS_IVYBRIDGE(dev_priv)) 860 plane->min_cdclk = ivb_plane_min_cdclk; 861 else 862 plane->min_cdclk = i9xx_plane_min_cdclk; 863 864 if (HAS_GMCH(dev_priv)) { 865 if (DISPLAY_VER(dev_priv) >= 4) 866 plane->max_stride = i965_plane_max_stride; 867 else 868 plane->max_stride = i9xx_plane_max_stride; 869 } else { 870 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 871 plane->max_stride = hsw_primary_max_stride; 872 else 873 plane->max_stride = ilk_primary_max_stride; 874 } 875 876 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) { 877 plane->update_arm = i830_plane_update_arm; 878 } else { 879 plane->update_noarm = i9xx_plane_update_noarm; 880 plane->update_arm = i9xx_plane_update_arm; 881 } 882 plane->disable_arm = i9xx_plane_disable_arm; 883 plane->get_hw_state = i9xx_plane_get_hw_state; 884 plane->check_plane = i9xx_plane_check; 885 886 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 887 plane->async_flip = vlv_primary_async_flip; 888 plane->enable_flip_done = vlv_primary_enable_flip_done; 889 plane->disable_flip_done = vlv_primary_disable_flip_done; 890 } else if (IS_BROADWELL(dev_priv)) { 891 plane->need_async_flip_disable_wa = true; 892 plane->async_flip = g4x_primary_async_flip; 893 plane->enable_flip_done = bdw_primary_enable_flip_done; 894 plane->disable_flip_done = bdw_primary_disable_flip_done; 895 } else if (DISPLAY_VER(dev_priv) >= 7) { 896 plane->async_flip = g4x_primary_async_flip; 897 plane->enable_flip_done = ivb_primary_enable_flip_done; 898 plane->disable_flip_done = ivb_primary_disable_flip_done; 899 } else if (DISPLAY_VER(dev_priv) >= 5) { 900 plane->async_flip = g4x_primary_async_flip; 901 plane->enable_flip_done = ilk_primary_enable_flip_done; 902 plane->disable_flip_done = ilk_primary_disable_flip_done; 903 } 904 905 modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X); 906 907 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 908 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 909 0, plane_funcs, 910 formats, num_formats, 911 modifiers, 912 DRM_PLANE_TYPE_PRIMARY, 913 "primary %c", pipe_name(pipe)); 914 else 915 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 916 0, plane_funcs, 917 formats, num_formats, 918 modifiers, 919 DRM_PLANE_TYPE_PRIMARY, 920 "plane %c", 921 plane_name(plane->i9xx_plane)); 922 923 kfree(modifiers); 924 925 if (ret) 926 goto fail; 927 928 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 929 supported_rotations = 930 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | 931 DRM_MODE_REFLECT_X; 932 } else if (DISPLAY_VER(dev_priv) >= 4) { 933 supported_rotations = 934 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 935 } else { 936 supported_rotations = DRM_MODE_ROTATE_0; 937 } 938 939 if (DISPLAY_VER(dev_priv) >= 4) 940 drm_plane_create_rotation_property(&plane->base, 941 DRM_MODE_ROTATE_0, 942 supported_rotations); 943 944 zpos = 0; 945 drm_plane_create_zpos_immutable_property(&plane->base, zpos); 946 947 intel_plane_helper_add(plane); 948 949 return plane; 950 951 fail: 952 intel_plane_free(plane); 953 954 return ERR_PTR(ret); 955 } 956 957 static int i9xx_format_to_fourcc(int format) 958 { 959 switch (format) { 960 case DISP_FORMAT_8BPP: 961 return DRM_FORMAT_C8; 962 case DISP_FORMAT_BGRA555: 963 return DRM_FORMAT_ARGB1555; 964 case DISP_FORMAT_BGRX555: 965 return DRM_FORMAT_XRGB1555; 966 case DISP_FORMAT_BGRX565: 967 return DRM_FORMAT_RGB565; 968 default: 969 case DISP_FORMAT_BGRX888: 970 return DRM_FORMAT_XRGB8888; 971 case DISP_FORMAT_RGBX888: 972 return DRM_FORMAT_XBGR8888; 973 case DISP_FORMAT_BGRA888: 974 return DRM_FORMAT_ARGB8888; 975 case DISP_FORMAT_RGBA888: 976 return DRM_FORMAT_ABGR8888; 977 case DISP_FORMAT_BGRX101010: 978 return DRM_FORMAT_XRGB2101010; 979 case DISP_FORMAT_RGBX101010: 980 return DRM_FORMAT_XBGR2101010; 981 case DISP_FORMAT_BGRA101010: 982 return DRM_FORMAT_ARGB2101010; 983 case DISP_FORMAT_RGBA101010: 984 return DRM_FORMAT_ABGR2101010; 985 case DISP_FORMAT_RGBX161616: 986 return DRM_FORMAT_XBGR16161616F; 987 } 988 } 989 990 void 991 i9xx_get_initial_plane_config(struct intel_crtc *crtc, 992 struct intel_initial_plane_config *plane_config) 993 { 994 struct drm_device *dev = crtc->base.dev; 995 struct drm_i915_private *dev_priv = to_i915(dev); 996 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 997 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 998 enum pipe pipe; 999 u32 val, base, offset; 1000 int fourcc, pixel_format; 1001 unsigned int aligned_height; 1002 struct drm_framebuffer *fb; 1003 struct intel_framebuffer *intel_fb; 1004 1005 if (!plane->get_hw_state(plane, &pipe)) 1006 return; 1007 1008 drm_WARN_ON(dev, pipe != crtc->pipe); 1009 1010 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 1011 if (!intel_fb) { 1012 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); 1013 return; 1014 } 1015 1016 fb = &intel_fb->base; 1017 1018 fb->dev = dev; 1019 1020 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 1021 1022 if (DISPLAY_VER(dev_priv) >= 4) { 1023 if (val & DISP_TILED) { 1024 plane_config->tiling = I915_TILING_X; 1025 fb->modifier = I915_FORMAT_MOD_X_TILED; 1026 } 1027 1028 if (val & DISP_ROTATE_180) 1029 plane_config->rotation = DRM_MODE_ROTATE_180; 1030 } 1031 1032 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && 1033 val & DISP_MIRROR) 1034 plane_config->rotation |= DRM_MODE_REFLECT_X; 1035 1036 pixel_format = val & DISP_FORMAT_MASK; 1037 fourcc = i9xx_format_to_fourcc(pixel_format); 1038 fb->format = drm_format_info(fourcc); 1039 1040 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 1041 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane)); 1042 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; 1043 } else if (DISPLAY_VER(dev_priv) >= 4) { 1044 if (plane_config->tiling) 1045 offset = intel_de_read(dev_priv, 1046 DSPTILEOFF(i9xx_plane)); 1047 else 1048 offset = intel_de_read(dev_priv, 1049 DSPLINOFF(i9xx_plane)); 1050 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; 1051 } else { 1052 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane)); 1053 } 1054 plane_config->base = base; 1055 1056 val = intel_de_read(dev_priv, PIPESRC(pipe)); 1057 fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1; 1058 fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1; 1059 1060 val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane)); 1061 fb->pitches[0] = val & 0xffffffc0; 1062 1063 aligned_height = intel_fb_align_height(fb, 0, fb->height); 1064 1065 plane_config->size = fb->pitches[0] * aligned_height; 1066 1067 drm_dbg_kms(&dev_priv->drm, 1068 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 1069 crtc->base.name, plane->base.name, fb->width, fb->height, 1070 fb->format->cpp[0] * 8, base, fb->pitches[0], 1071 plane_config->size); 1072 1073 plane_config->fb = intel_fb; 1074 } 1075