1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 #include <linux/kernel.h> 6 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_fourcc.h> 9 #include <drm/drm_plane_helper.h> 10 11 #include "intel_atomic.h" 12 #include "intel_atomic_plane.h" 13 #include "intel_display_types.h" 14 #include "intel_sprite.h" 15 #include "i9xx_plane.h" 16 17 /* Primary plane formats for gen <= 3 */ 18 static const u32 i8xx_primary_formats[] = { 19 DRM_FORMAT_C8, 20 DRM_FORMAT_XRGB1555, 21 DRM_FORMAT_RGB565, 22 DRM_FORMAT_XRGB8888, 23 }; 24 25 /* Primary plane formats for ivb (no fp16 due to hw issue) */ 26 static const u32 ivb_primary_formats[] = { 27 DRM_FORMAT_C8, 28 DRM_FORMAT_RGB565, 29 DRM_FORMAT_XRGB8888, 30 DRM_FORMAT_XBGR8888, 31 DRM_FORMAT_XRGB2101010, 32 DRM_FORMAT_XBGR2101010, 33 }; 34 35 /* Primary plane formats for gen >= 4, except ivb */ 36 static const u32 i965_primary_formats[] = { 37 DRM_FORMAT_C8, 38 DRM_FORMAT_RGB565, 39 DRM_FORMAT_XRGB8888, 40 DRM_FORMAT_XBGR8888, 41 DRM_FORMAT_XRGB2101010, 42 DRM_FORMAT_XBGR2101010, 43 DRM_FORMAT_XBGR16161616F, 44 }; 45 46 /* Primary plane formats for vlv/chv */ 47 static const u32 vlv_primary_formats[] = { 48 DRM_FORMAT_C8, 49 DRM_FORMAT_RGB565, 50 DRM_FORMAT_XRGB8888, 51 DRM_FORMAT_XBGR8888, 52 DRM_FORMAT_ARGB8888, 53 DRM_FORMAT_ABGR8888, 54 DRM_FORMAT_XRGB2101010, 55 DRM_FORMAT_XBGR2101010, 56 DRM_FORMAT_ARGB2101010, 57 DRM_FORMAT_ABGR2101010, 58 DRM_FORMAT_XBGR16161616F, 59 }; 60 61 static const u64 i9xx_format_modifiers[] = { 62 I915_FORMAT_MOD_X_TILED, 63 DRM_FORMAT_MOD_LINEAR, 64 DRM_FORMAT_MOD_INVALID 65 }; 66 67 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, 68 u32 format, u64 modifier) 69 { 70 switch (modifier) { 71 case DRM_FORMAT_MOD_LINEAR: 72 case I915_FORMAT_MOD_X_TILED: 73 break; 74 default: 75 return false; 76 } 77 78 switch (format) { 79 case DRM_FORMAT_C8: 80 case DRM_FORMAT_RGB565: 81 case DRM_FORMAT_XRGB1555: 82 case DRM_FORMAT_XRGB8888: 83 return modifier == DRM_FORMAT_MOD_LINEAR || 84 modifier == I915_FORMAT_MOD_X_TILED; 85 default: 86 return false; 87 } 88 } 89 90 static bool i965_plane_format_mod_supported(struct drm_plane *_plane, 91 u32 format, u64 modifier) 92 { 93 switch (modifier) { 94 case DRM_FORMAT_MOD_LINEAR: 95 case I915_FORMAT_MOD_X_TILED: 96 break; 97 default: 98 return false; 99 } 100 101 switch (format) { 102 case DRM_FORMAT_C8: 103 case DRM_FORMAT_RGB565: 104 case DRM_FORMAT_XRGB8888: 105 case DRM_FORMAT_XBGR8888: 106 case DRM_FORMAT_ARGB8888: 107 case DRM_FORMAT_ABGR8888: 108 case DRM_FORMAT_XRGB2101010: 109 case DRM_FORMAT_XBGR2101010: 110 case DRM_FORMAT_ARGB2101010: 111 case DRM_FORMAT_ABGR2101010: 112 case DRM_FORMAT_XBGR16161616F: 113 return modifier == DRM_FORMAT_MOD_LINEAR || 114 modifier == I915_FORMAT_MOD_X_TILED; 115 default: 116 return false; 117 } 118 } 119 120 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, 121 enum i9xx_plane_id i9xx_plane) 122 { 123 if (!HAS_FBC(dev_priv)) 124 return false; 125 126 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 127 return i9xx_plane == PLANE_A; /* tied to pipe A */ 128 else if (IS_IVYBRIDGE(dev_priv)) 129 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B || 130 i9xx_plane == PLANE_C; 131 else if (INTEL_GEN(dev_priv) >= 4) 132 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B; 133 else 134 return i9xx_plane == PLANE_A; 135 } 136 137 static bool i9xx_plane_has_windowing(struct intel_plane *plane) 138 { 139 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 140 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 141 142 if (IS_CHERRYVIEW(dev_priv)) 143 return i9xx_plane == PLANE_B; 144 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) 145 return false; 146 else if (IS_GEN(dev_priv, 4)) 147 return i9xx_plane == PLANE_C; 148 else 149 return i9xx_plane == PLANE_B || 150 i9xx_plane == PLANE_C; 151 } 152 153 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, 154 const struct intel_plane_state *plane_state) 155 { 156 struct drm_i915_private *dev_priv = 157 to_i915(plane_state->uapi.plane->dev); 158 const struct drm_framebuffer *fb = plane_state->hw.fb; 159 unsigned int rotation = plane_state->hw.rotation; 160 u32 dspcntr; 161 162 dspcntr = DISPLAY_PLANE_ENABLE; 163 164 if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) || 165 IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) 166 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 167 168 switch (fb->format->format) { 169 case DRM_FORMAT_C8: 170 dspcntr |= DISPPLANE_8BPP; 171 break; 172 case DRM_FORMAT_XRGB1555: 173 dspcntr |= DISPPLANE_BGRX555; 174 break; 175 case DRM_FORMAT_ARGB1555: 176 dspcntr |= DISPPLANE_BGRA555; 177 break; 178 case DRM_FORMAT_RGB565: 179 dspcntr |= DISPPLANE_BGRX565; 180 break; 181 case DRM_FORMAT_XRGB8888: 182 dspcntr |= DISPPLANE_BGRX888; 183 break; 184 case DRM_FORMAT_XBGR8888: 185 dspcntr |= DISPPLANE_RGBX888; 186 break; 187 case DRM_FORMAT_ARGB8888: 188 dspcntr |= DISPPLANE_BGRA888; 189 break; 190 case DRM_FORMAT_ABGR8888: 191 dspcntr |= DISPPLANE_RGBA888; 192 break; 193 case DRM_FORMAT_XRGB2101010: 194 dspcntr |= DISPPLANE_BGRX101010; 195 break; 196 case DRM_FORMAT_XBGR2101010: 197 dspcntr |= DISPPLANE_RGBX101010; 198 break; 199 case DRM_FORMAT_ARGB2101010: 200 dspcntr |= DISPPLANE_BGRA101010; 201 break; 202 case DRM_FORMAT_ABGR2101010: 203 dspcntr |= DISPPLANE_RGBA101010; 204 break; 205 case DRM_FORMAT_XBGR16161616F: 206 dspcntr |= DISPPLANE_RGBX161616; 207 break; 208 default: 209 MISSING_CASE(fb->format->format); 210 return 0; 211 } 212 213 if (INTEL_GEN(dev_priv) >= 4 && 214 fb->modifier == I915_FORMAT_MOD_X_TILED) 215 dspcntr |= DISPPLANE_TILED; 216 217 if (rotation & DRM_MODE_ROTATE_180) 218 dspcntr |= DISPPLANE_ROTATE_180; 219 220 if (rotation & DRM_MODE_REFLECT_X) 221 dspcntr |= DISPPLANE_MIRROR; 222 223 return dspcntr; 224 } 225 226 int i9xx_check_plane_surface(struct intel_plane_state *plane_state) 227 { 228 struct drm_i915_private *dev_priv = 229 to_i915(plane_state->uapi.plane->dev); 230 const struct drm_framebuffer *fb = plane_state->hw.fb; 231 int src_x, src_y, src_w; 232 u32 offset; 233 int ret; 234 235 ret = intel_plane_compute_gtt(plane_state); 236 if (ret) 237 return ret; 238 239 if (!plane_state->uapi.visible) 240 return 0; 241 242 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 243 src_x = plane_state->uapi.src.x1 >> 16; 244 src_y = plane_state->uapi.src.y1 >> 16; 245 246 /* Undocumented hardware limit on i965/g4x/vlv/chv */ 247 if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048) 248 return -EINVAL; 249 250 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); 251 252 if (INTEL_GEN(dev_priv) >= 4) 253 offset = intel_plane_compute_aligned_offset(&src_x, &src_y, 254 plane_state, 0); 255 else 256 offset = 0; 257 258 /* 259 * Put the final coordinates back so that the src 260 * coordinate checks will see the right values. 261 */ 262 drm_rect_translate_to(&plane_state->uapi.src, 263 src_x << 16, src_y << 16); 264 265 /* HSW/BDW do this automagically in hardware */ 266 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { 267 unsigned int rotation = plane_state->hw.rotation; 268 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 269 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 270 271 if (rotation & DRM_MODE_ROTATE_180) { 272 src_x += src_w - 1; 273 src_y += src_h - 1; 274 } else if (rotation & DRM_MODE_REFLECT_X) { 275 src_x += src_w - 1; 276 } 277 } 278 279 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 280 drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095); 281 } else if (INTEL_GEN(dev_priv) >= 4 && 282 fb->modifier == I915_FORMAT_MOD_X_TILED) { 283 drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095); 284 } 285 286 plane_state->color_plane[0].offset = offset; 287 plane_state->color_plane[0].x = src_x; 288 plane_state->color_plane[0].y = src_y; 289 290 return 0; 291 } 292 293 static int 294 i9xx_plane_check(struct intel_crtc_state *crtc_state, 295 struct intel_plane_state *plane_state) 296 { 297 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 298 int ret; 299 300 ret = chv_plane_check_rotation(plane_state); 301 if (ret) 302 return ret; 303 304 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 305 DRM_PLANE_HELPER_NO_SCALING, 306 DRM_PLANE_HELPER_NO_SCALING, 307 i9xx_plane_has_windowing(plane)); 308 if (ret) 309 return ret; 310 311 ret = i9xx_check_plane_surface(plane_state); 312 if (ret) 313 return ret; 314 315 if (!plane_state->uapi.visible) 316 return 0; 317 318 ret = intel_plane_check_src_coordinates(plane_state); 319 if (ret) 320 return ret; 321 322 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state); 323 324 return 0; 325 } 326 327 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) 328 { 329 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 330 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 331 u32 dspcntr = 0; 332 333 if (crtc_state->gamma_enable) 334 dspcntr |= DISPPLANE_GAMMA_ENABLE; 335 336 if (crtc_state->csc_enable) 337 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; 338 339 if (INTEL_GEN(dev_priv) < 5) 340 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); 341 342 return dspcntr; 343 } 344 345 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state, 346 const struct intel_plane_state *plane_state, 347 unsigned int *num, unsigned int *den) 348 { 349 const struct drm_framebuffer *fb = plane_state->hw.fb; 350 unsigned int cpp = fb->format->cpp[0]; 351 352 /* 353 * g4x bspec says 64bpp pixel rate can't exceed 80% 354 * of cdclk when the sprite plane is enabled on the 355 * same pipe. ilk/snb bspec says 64bpp pixel rate is 356 * never allowed to exceed 80% of cdclk. Let's just go 357 * with the ilk/snb limit always. 358 */ 359 if (cpp == 8) { 360 *num = 10; 361 *den = 8; 362 } else { 363 *num = 1; 364 *den = 1; 365 } 366 } 367 368 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 369 const struct intel_plane_state *plane_state) 370 { 371 unsigned int pixel_rate; 372 unsigned int num, den; 373 374 /* 375 * Note that crtc_state->pixel_rate accounts for both 376 * horizontal and vertical panel fitter downscaling factors. 377 * Pre-HSW bspec tells us to only consider the horizontal 378 * downscaling factor here. We ignore that and just consider 379 * both for simplicity. 380 */ 381 pixel_rate = crtc_state->pixel_rate; 382 383 i9xx_plane_ratio(crtc_state, plane_state, &num, &den); 384 385 /* two pixels per clock with double wide pipe */ 386 if (crtc_state->double_wide) 387 den *= 2; 388 389 return DIV_ROUND_UP(pixel_rate * num, den); 390 } 391 392 static void i9xx_update_plane(struct intel_plane *plane, 393 const struct intel_crtc_state *crtc_state, 394 const struct intel_plane_state *plane_state) 395 { 396 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 397 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 398 u32 linear_offset; 399 int x = plane_state->color_plane[0].x; 400 int y = plane_state->color_plane[0].y; 401 int crtc_x = plane_state->uapi.dst.x1; 402 int crtc_y = plane_state->uapi.dst.y1; 403 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 404 int crtc_h = drm_rect_height(&plane_state->uapi.dst); 405 unsigned long irqflags; 406 u32 dspaddr_offset; 407 u32 dspcntr; 408 409 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); 410 411 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 412 413 if (INTEL_GEN(dev_priv) >= 4) 414 dspaddr_offset = plane_state->color_plane[0].offset; 415 else 416 dspaddr_offset = linear_offset; 417 418 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 419 420 intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), 421 plane_state->color_plane[0].stride); 422 423 if (INTEL_GEN(dev_priv) < 4) { 424 /* 425 * PLANE_A doesn't actually have a full window 426 * generator but let's assume we still need to 427 * program whatever is there. 428 */ 429 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), 430 (crtc_y << 16) | crtc_x); 431 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), 432 ((crtc_h - 1) << 16) | (crtc_w - 1)); 433 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { 434 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), 435 (crtc_y << 16) | crtc_x); 436 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), 437 ((crtc_h - 1) << 16) | (crtc_w - 1)); 438 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); 439 } 440 441 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 442 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), 443 (y << 16) | x); 444 } else if (INTEL_GEN(dev_priv) >= 4) { 445 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), 446 linear_offset); 447 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), 448 (y << 16) | x); 449 } 450 451 /* 452 * The control register self-arms if the plane was previously 453 * disabled. Try to make the plane enable atomic by writing 454 * the control register just before the surface register. 455 */ 456 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); 457 if (INTEL_GEN(dev_priv) >= 4) 458 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 459 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 460 else 461 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 462 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 463 464 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 465 } 466 467 static void i9xx_disable_plane(struct intel_plane *plane, 468 const struct intel_crtc_state *crtc_state) 469 { 470 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 471 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 472 unsigned long irqflags; 473 u32 dspcntr; 474 475 /* 476 * DSPCNTR pipe gamma enable on g4x+ and pipe csc 477 * enable on ilk+ affect the pipe bottom color as 478 * well, so we must configure them even if the plane 479 * is disabled. 480 * 481 * On pre-g4x there is no way to gamma correct the 482 * pipe bottom color but we'll keep on doing this 483 * anyway so that the crtc state readout works correctly. 484 */ 485 dspcntr = i9xx_plane_ctl_crtc(crtc_state); 486 487 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 488 489 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); 490 if (INTEL_GEN(dev_priv) >= 4) 491 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); 492 else 493 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0); 494 495 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 496 } 497 498 static void 499 g4x_primary_async_flip(struct intel_plane *plane, 500 const struct intel_crtc_state *crtc_state, 501 const struct intel_plane_state *plane_state, 502 bool async_flip) 503 { 504 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 505 u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); 506 u32 dspaddr_offset = plane_state->color_plane[0].offset; 507 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 508 unsigned long irqflags; 509 510 if (async_flip) 511 dspcntr |= DISPPLANE_ASYNC_FLIP; 512 513 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 514 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); 515 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 516 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 517 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 518 } 519 520 static void 521 vlv_primary_async_flip(struct intel_plane *plane, 522 const struct intel_crtc_state *crtc_state, 523 const struct intel_plane_state *plane_state, 524 bool async_flip) 525 { 526 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 527 u32 dspaddr_offset = plane_state->color_plane[0].offset; 528 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 529 unsigned long irqflags; 530 531 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 532 intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane), 533 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 534 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 535 } 536 537 static void 538 bdw_primary_enable_flip_done(struct intel_plane *plane) 539 { 540 struct drm_i915_private *i915 = to_i915(plane->base.dev); 541 enum pipe pipe = plane->pipe; 542 543 spin_lock_irq(&i915->irq_lock); 544 bdw_enable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE); 545 spin_unlock_irq(&i915->irq_lock); 546 } 547 548 static void 549 bdw_primary_disable_flip_done(struct intel_plane *plane) 550 { 551 struct drm_i915_private *i915 = to_i915(plane->base.dev); 552 enum pipe pipe = plane->pipe; 553 554 spin_lock_irq(&i915->irq_lock); 555 bdw_disable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE); 556 spin_unlock_irq(&i915->irq_lock); 557 } 558 559 static void 560 ivb_primary_enable_flip_done(struct intel_plane *plane) 561 { 562 struct drm_i915_private *i915 = to_i915(plane->base.dev); 563 564 spin_lock_irq(&i915->irq_lock); 565 ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); 566 spin_unlock_irq(&i915->irq_lock); 567 } 568 569 static void 570 ivb_primary_disable_flip_done(struct intel_plane *plane) 571 { 572 struct drm_i915_private *i915 = to_i915(plane->base.dev); 573 574 spin_lock_irq(&i915->irq_lock); 575 ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); 576 spin_unlock_irq(&i915->irq_lock); 577 } 578 579 static void 580 ilk_primary_enable_flip_done(struct intel_plane *plane) 581 { 582 struct drm_i915_private *i915 = to_i915(plane->base.dev); 583 584 spin_lock_irq(&i915->irq_lock); 585 ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); 586 spin_unlock_irq(&i915->irq_lock); 587 } 588 589 static void 590 ilk_primary_disable_flip_done(struct intel_plane *plane) 591 { 592 struct drm_i915_private *i915 = to_i915(plane->base.dev); 593 594 spin_lock_irq(&i915->irq_lock); 595 ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); 596 spin_unlock_irq(&i915->irq_lock); 597 } 598 599 static void 600 vlv_primary_enable_flip_done(struct intel_plane *plane) 601 { 602 struct drm_i915_private *i915 = to_i915(plane->base.dev); 603 enum pipe pipe = plane->pipe; 604 605 spin_lock_irq(&i915->irq_lock); 606 i915_enable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV); 607 spin_unlock_irq(&i915->irq_lock); 608 } 609 610 static void 611 vlv_primary_disable_flip_done(struct intel_plane *plane) 612 { 613 struct drm_i915_private *i915 = to_i915(plane->base.dev); 614 enum pipe pipe = plane->pipe; 615 616 spin_lock_irq(&i915->irq_lock); 617 i915_disable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV); 618 spin_unlock_irq(&i915->irq_lock); 619 } 620 621 static bool i9xx_plane_get_hw_state(struct intel_plane *plane, 622 enum pipe *pipe) 623 { 624 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 625 enum intel_display_power_domain power_domain; 626 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 627 intel_wakeref_t wakeref; 628 bool ret; 629 u32 val; 630 631 /* 632 * Not 100% correct for planes that can move between pipes, 633 * but that's only the case for gen2-4 which don't have any 634 * display power wells. 635 */ 636 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 637 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 638 if (!wakeref) 639 return false; 640 641 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 642 643 ret = val & DISPLAY_PLANE_ENABLE; 644 645 if (INTEL_GEN(dev_priv) >= 5) 646 *pipe = plane->pipe; 647 else 648 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> 649 DISPPLANE_SEL_PIPE_SHIFT; 650 651 intel_display_power_put(dev_priv, power_domain, wakeref); 652 653 return ret; 654 } 655 656 static unsigned int 657 hsw_primary_max_stride(struct intel_plane *plane, 658 u32 pixel_format, u64 modifier, 659 unsigned int rotation) 660 { 661 const struct drm_format_info *info = drm_format_info(pixel_format); 662 int cpp = info->cpp[0]; 663 664 /* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */ 665 return min(8192 * cpp, 32 * 1024); 666 } 667 668 static unsigned int 669 ilk_primary_max_stride(struct intel_plane *plane, 670 u32 pixel_format, u64 modifier, 671 unsigned int rotation) 672 { 673 const struct drm_format_info *info = drm_format_info(pixel_format); 674 int cpp = info->cpp[0]; 675 676 /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */ 677 if (modifier == I915_FORMAT_MOD_X_TILED) 678 return min(4096 * cpp, 32 * 1024); 679 else 680 return 32 * 1024; 681 } 682 683 unsigned int 684 i965_plane_max_stride(struct intel_plane *plane, 685 u32 pixel_format, u64 modifier, 686 unsigned int rotation) 687 { 688 const struct drm_format_info *info = drm_format_info(pixel_format); 689 int cpp = info->cpp[0]; 690 691 /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */ 692 if (modifier == I915_FORMAT_MOD_X_TILED) 693 return min(4096 * cpp, 16 * 1024); 694 else 695 return 32 * 1024; 696 } 697 698 static unsigned int 699 i9xx_plane_max_stride(struct intel_plane *plane, 700 u32 pixel_format, u64 modifier, 701 unsigned int rotation) 702 { 703 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 704 705 if (INTEL_GEN(dev_priv) >= 3) { 706 if (modifier == I915_FORMAT_MOD_X_TILED) 707 return 8*1024; 708 else 709 return 16*1024; 710 } else { 711 if (plane->i9xx_plane == PLANE_C) 712 return 4*1024; 713 else 714 return 8*1024; 715 } 716 } 717 718 static const struct drm_plane_funcs i965_plane_funcs = { 719 .update_plane = drm_atomic_helper_update_plane, 720 .disable_plane = drm_atomic_helper_disable_plane, 721 .destroy = intel_plane_destroy, 722 .atomic_duplicate_state = intel_plane_duplicate_state, 723 .atomic_destroy_state = intel_plane_destroy_state, 724 .format_mod_supported = i965_plane_format_mod_supported, 725 }; 726 727 static const struct drm_plane_funcs i8xx_plane_funcs = { 728 .update_plane = drm_atomic_helper_update_plane, 729 .disable_plane = drm_atomic_helper_disable_plane, 730 .destroy = intel_plane_destroy, 731 .atomic_duplicate_state = intel_plane_duplicate_state, 732 .atomic_destroy_state = intel_plane_destroy_state, 733 .format_mod_supported = i8xx_plane_format_mod_supported, 734 }; 735 736 struct intel_plane * 737 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 738 { 739 struct intel_plane *plane; 740 const struct drm_plane_funcs *plane_funcs; 741 unsigned int supported_rotations; 742 const u32 *formats; 743 int num_formats; 744 int ret, zpos; 745 746 if (INTEL_GEN(dev_priv) >= 9) 747 return skl_universal_plane_create(dev_priv, pipe, 748 PLANE_PRIMARY); 749 750 plane = intel_plane_alloc(); 751 if (IS_ERR(plane)) 752 return plane; 753 754 plane->pipe = pipe; 755 /* 756 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS 757 * port is hooked to pipe B. Hence we want plane A feeding pipe B. 758 */ 759 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 && 760 INTEL_NUM_PIPES(dev_priv) == 2) 761 plane->i9xx_plane = (enum i9xx_plane_id) !pipe; 762 else 763 plane->i9xx_plane = (enum i9xx_plane_id) pipe; 764 plane->id = PLANE_PRIMARY; 765 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); 766 767 plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane); 768 if (plane->has_fbc) { 769 struct intel_fbc *fbc = &dev_priv->fbc; 770 771 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; 772 } 773 774 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 775 formats = vlv_primary_formats; 776 num_formats = ARRAY_SIZE(vlv_primary_formats); 777 } else if (INTEL_GEN(dev_priv) >= 4) { 778 /* 779 * WaFP16GammaEnabling:ivb 780 * "Workaround : When using the 64-bit format, the plane 781 * output on each color channel has one quarter amplitude. 782 * It can be brought up to full amplitude by using pipe 783 * gamma correction or pipe color space conversion to 784 * multiply the plane output by four." 785 * 786 * There is no dedicated plane gamma for the primary plane, 787 * and using the pipe gamma/csc could conflict with other 788 * planes, so we choose not to expose fp16 on IVB primary 789 * planes. HSW primary planes no longer have this problem. 790 */ 791 if (IS_IVYBRIDGE(dev_priv)) { 792 formats = ivb_primary_formats; 793 num_formats = ARRAY_SIZE(ivb_primary_formats); 794 } else { 795 formats = i965_primary_formats; 796 num_formats = ARRAY_SIZE(i965_primary_formats); 797 } 798 } else { 799 formats = i8xx_primary_formats; 800 num_formats = ARRAY_SIZE(i8xx_primary_formats); 801 } 802 803 if (INTEL_GEN(dev_priv) >= 4) 804 plane_funcs = &i965_plane_funcs; 805 else 806 plane_funcs = &i8xx_plane_funcs; 807 808 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 809 plane->min_cdclk = vlv_plane_min_cdclk; 810 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 811 plane->min_cdclk = hsw_plane_min_cdclk; 812 else if (IS_IVYBRIDGE(dev_priv)) 813 plane->min_cdclk = ivb_plane_min_cdclk; 814 else 815 plane->min_cdclk = i9xx_plane_min_cdclk; 816 817 if (HAS_GMCH(dev_priv)) { 818 if (INTEL_GEN(dev_priv) >= 4) 819 plane->max_stride = i965_plane_max_stride; 820 else 821 plane->max_stride = i9xx_plane_max_stride; 822 } else { 823 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 824 plane->max_stride = hsw_primary_max_stride; 825 else 826 plane->max_stride = ilk_primary_max_stride; 827 } 828 829 plane->update_plane = i9xx_update_plane; 830 plane->disable_plane = i9xx_disable_plane; 831 plane->get_hw_state = i9xx_plane_get_hw_state; 832 plane->check_plane = i9xx_plane_check; 833 834 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 835 plane->async_flip = vlv_primary_async_flip; 836 plane->enable_flip_done = vlv_primary_enable_flip_done; 837 plane->disable_flip_done = vlv_primary_disable_flip_done; 838 } else if (IS_BROADWELL(dev_priv)) { 839 plane->need_async_flip_disable_wa = true; 840 plane->async_flip = g4x_primary_async_flip; 841 plane->enable_flip_done = bdw_primary_enable_flip_done; 842 plane->disable_flip_done = bdw_primary_disable_flip_done; 843 } else if (INTEL_GEN(dev_priv) >= 7) { 844 plane->async_flip = g4x_primary_async_flip; 845 plane->enable_flip_done = ivb_primary_enable_flip_done; 846 plane->disable_flip_done = ivb_primary_disable_flip_done; 847 } else if (INTEL_GEN(dev_priv) >= 5) { 848 plane->async_flip = g4x_primary_async_flip; 849 plane->enable_flip_done = ilk_primary_enable_flip_done; 850 plane->disable_flip_done = ilk_primary_disable_flip_done; 851 } 852 853 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) 854 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 855 0, plane_funcs, 856 formats, num_formats, 857 i9xx_format_modifiers, 858 DRM_PLANE_TYPE_PRIMARY, 859 "primary %c", pipe_name(pipe)); 860 else 861 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 862 0, plane_funcs, 863 formats, num_formats, 864 i9xx_format_modifiers, 865 DRM_PLANE_TYPE_PRIMARY, 866 "plane %c", 867 plane_name(plane->i9xx_plane)); 868 if (ret) 869 goto fail; 870 871 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 872 supported_rotations = 873 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | 874 DRM_MODE_REFLECT_X; 875 } else if (INTEL_GEN(dev_priv) >= 4) { 876 supported_rotations = 877 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 878 } else { 879 supported_rotations = DRM_MODE_ROTATE_0; 880 } 881 882 if (INTEL_GEN(dev_priv) >= 4) 883 drm_plane_create_rotation_property(&plane->base, 884 DRM_MODE_ROTATE_0, 885 supported_rotations); 886 887 zpos = 0; 888 drm_plane_create_zpos_immutable_property(&plane->base, zpos); 889 890 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); 891 892 return plane; 893 894 fail: 895 intel_plane_free(plane); 896 897 return ERR_PTR(ret); 898 } 899 900