1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code). 6 */ 7 8 #include "g4x_hdmi.h" 9 #include "i915_reg.h" 10 #include "intel_audio.h" 11 #include "intel_connector.h" 12 #include "intel_crtc.h" 13 #include "intel_de.h" 14 #include "intel_display_power.h" 15 #include "intel_display_types.h" 16 #include "intel_dpio_phy.h" 17 #include "intel_fifo_underrun.h" 18 #include "intel_hdmi.h" 19 #include "intel_hotplug.h" 20 #include "intel_sdvo.h" 21 #include "vlv_sideband.h" 22 23 static void intel_hdmi_prepare(struct intel_encoder *encoder, 24 const struct intel_crtc_state *crtc_state) 25 { 26 struct drm_device *dev = encoder->base.dev; 27 struct drm_i915_private *dev_priv = to_i915(dev); 28 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 29 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 30 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 31 u32 hdmi_val; 32 33 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 34 35 hdmi_val = SDVO_ENCODING_HDMI; 36 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 37 hdmi_val |= HDMI_COLOR_RANGE_16_235; 38 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 39 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 40 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 41 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 42 43 if (crtc_state->pipe_bpp > 24) 44 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 45 else 46 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 47 48 if (crtc_state->has_hdmi_sink) 49 hdmi_val |= HDMI_MODE_SELECT_HDMI; 50 51 if (HAS_PCH_CPT(dev_priv)) 52 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 53 else if (IS_CHERRYVIEW(dev_priv)) 54 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 55 else 56 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 57 58 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); 59 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 60 } 61 62 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 63 enum pipe *pipe) 64 { 65 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 66 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 67 intel_wakeref_t wakeref; 68 bool ret; 69 70 wakeref = intel_display_power_get_if_enabled(dev_priv, 71 encoder->power_domain); 72 if (!wakeref) 73 return false; 74 75 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); 76 77 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 78 79 return ret; 80 } 81 82 static int g4x_hdmi_compute_config(struct intel_encoder *encoder, 83 struct intel_crtc_state *crtc_state, 84 struct drm_connector_state *conn_state) 85 { 86 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 87 88 if (HAS_PCH_SPLIT(i915)) 89 crtc_state->has_pch_encoder = true; 90 91 return intel_hdmi_compute_config(encoder, crtc_state, conn_state); 92 } 93 94 static void intel_hdmi_get_config(struct intel_encoder *encoder, 95 struct intel_crtc_state *pipe_config) 96 { 97 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 98 struct drm_device *dev = encoder->base.dev; 99 struct drm_i915_private *dev_priv = to_i915(dev); 100 u32 tmp, flags = 0; 101 int dotclock; 102 103 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 104 105 tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 106 107 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 108 flags |= DRM_MODE_FLAG_PHSYNC; 109 else 110 flags |= DRM_MODE_FLAG_NHSYNC; 111 112 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 113 flags |= DRM_MODE_FLAG_PVSYNC; 114 else 115 flags |= DRM_MODE_FLAG_NVSYNC; 116 117 if (tmp & HDMI_MODE_SELECT_HDMI) 118 pipe_config->has_hdmi_sink = true; 119 120 pipe_config->infoframes.enable |= 121 intel_hdmi_infoframes_enabled(encoder, pipe_config); 122 123 if (pipe_config->infoframes.enable) 124 pipe_config->has_infoframe = true; 125 126 if (tmp & HDMI_AUDIO_ENABLE) 127 pipe_config->has_audio = true; 128 129 if (!HAS_PCH_SPLIT(dev_priv) && 130 tmp & HDMI_COLOR_RANGE_16_235) 131 pipe_config->limited_color_range = true; 132 133 pipe_config->hw.adjusted_mode.flags |= flags; 134 135 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 136 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 2, 3); 137 else 138 dotclock = pipe_config->port_clock; 139 140 if (pipe_config->pixel_multiplier) 141 dotclock /= pipe_config->pixel_multiplier; 142 143 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 144 145 pipe_config->lane_count = 4; 146 147 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 148 149 intel_read_infoframe(encoder, pipe_config, 150 HDMI_INFOFRAME_TYPE_AVI, 151 &pipe_config->infoframes.avi); 152 intel_read_infoframe(encoder, pipe_config, 153 HDMI_INFOFRAME_TYPE_SPD, 154 &pipe_config->infoframes.spd); 155 intel_read_infoframe(encoder, pipe_config, 156 HDMI_INFOFRAME_TYPE_VENDOR, 157 &pipe_config->infoframes.hdmi); 158 } 159 160 static void g4x_enable_hdmi(struct intel_atomic_state *state, 161 struct intel_encoder *encoder, 162 const struct intel_crtc_state *pipe_config, 163 const struct drm_connector_state *conn_state) 164 { 165 struct drm_device *dev = encoder->base.dev; 166 struct drm_i915_private *dev_priv = to_i915(dev); 167 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 168 u32 temp; 169 170 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 171 172 temp |= SDVO_ENABLE; 173 if (pipe_config->has_audio) 174 temp |= HDMI_AUDIO_ENABLE; 175 176 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 177 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 178 179 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 180 !pipe_config->has_hdmi_sink); 181 intel_audio_codec_enable(encoder, pipe_config, conn_state); 182 } 183 184 static void ibx_enable_hdmi(struct intel_atomic_state *state, 185 struct intel_encoder *encoder, 186 const struct intel_crtc_state *pipe_config, 187 const struct drm_connector_state *conn_state) 188 { 189 struct drm_device *dev = encoder->base.dev; 190 struct drm_i915_private *dev_priv = to_i915(dev); 191 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 192 u32 temp; 193 194 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 195 196 temp |= SDVO_ENABLE; 197 if (pipe_config->has_audio) 198 temp |= HDMI_AUDIO_ENABLE; 199 200 /* 201 * HW workaround, need to write this twice for issue 202 * that may result in first write getting masked. 203 */ 204 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 205 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 206 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 207 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 208 209 /* 210 * HW workaround, need to toggle enable bit off and on 211 * for 12bpc with pixel repeat. 212 * 213 * FIXME: BSpec says this should be done at the end of 214 * the modeset sequence, so not sure if this isn't too soon. 215 */ 216 if (pipe_config->pipe_bpp > 24 && 217 pipe_config->pixel_multiplier > 1) { 218 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, 219 temp & ~SDVO_ENABLE); 220 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 221 222 /* 223 * HW workaround, need to write this twice for issue 224 * that may result in first write getting masked. 225 */ 226 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 227 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 228 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 229 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 230 } 231 232 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 233 !pipe_config->has_hdmi_sink); 234 intel_audio_codec_enable(encoder, pipe_config, conn_state); 235 } 236 237 static void cpt_enable_hdmi(struct intel_atomic_state *state, 238 struct intel_encoder *encoder, 239 const struct intel_crtc_state *pipe_config, 240 const struct drm_connector_state *conn_state) 241 { 242 struct drm_device *dev = encoder->base.dev; 243 struct drm_i915_private *dev_priv = to_i915(dev); 244 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 245 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 246 enum pipe pipe = crtc->pipe; 247 u32 temp; 248 249 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 250 251 temp |= SDVO_ENABLE; 252 if (pipe_config->has_audio) 253 temp |= HDMI_AUDIO_ENABLE; 254 255 /* 256 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 257 * 258 * The procedure for 12bpc is as follows: 259 * 1. disable HDMI clock gating 260 * 2. enable HDMI with 8bpc 261 * 3. enable HDMI with 12bpc 262 * 4. enable HDMI clock gating 263 */ 264 265 if (pipe_config->pipe_bpp > 24) { 266 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), 267 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 268 269 temp &= ~SDVO_COLOR_FORMAT_MASK; 270 temp |= SDVO_COLOR_FORMAT_8bpc; 271 } 272 273 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 274 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 275 276 if (pipe_config->pipe_bpp > 24) { 277 temp &= ~SDVO_COLOR_FORMAT_MASK; 278 temp |= HDMI_COLOR_FORMAT_12bpc; 279 280 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 281 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 282 283 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), 284 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 285 } 286 287 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 288 !pipe_config->has_hdmi_sink); 289 intel_audio_codec_enable(encoder, pipe_config, conn_state); 290 } 291 292 static void vlv_enable_hdmi(struct intel_atomic_state *state, 293 struct intel_encoder *encoder, 294 const struct intel_crtc_state *pipe_config, 295 const struct drm_connector_state *conn_state) 296 { 297 } 298 299 static void intel_disable_hdmi(struct intel_atomic_state *state, 300 struct intel_encoder *encoder, 301 const struct intel_crtc_state *old_crtc_state, 302 const struct drm_connector_state *old_conn_state) 303 { 304 struct drm_device *dev = encoder->base.dev; 305 struct drm_i915_private *dev_priv = to_i915(dev); 306 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 307 struct intel_digital_port *dig_port = 308 hdmi_to_dig_port(intel_hdmi); 309 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 310 u32 temp; 311 312 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 313 314 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); 315 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 316 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 317 318 /* 319 * HW workaround for IBX, we need to move the port 320 * to transcoder A after disabling it to allow the 321 * matching DP port to be enabled on transcoder A. 322 */ 323 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 324 /* 325 * We get CPU/PCH FIFO underruns on the other pipe when 326 * doing the workaround. Sweep them under the rug. 327 */ 328 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 329 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 330 331 temp &= ~SDVO_PIPE_SEL_MASK; 332 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 333 /* 334 * HW workaround, need to write this twice for issue 335 * that may result in first write getting masked. 336 */ 337 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 338 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 339 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 340 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 341 342 temp &= ~SDVO_ENABLE; 343 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 344 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 345 346 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 347 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 348 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 349 } 350 351 dig_port->set_infoframes(encoder, 352 false, 353 old_crtc_state, old_conn_state); 354 355 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 356 } 357 358 static void g4x_disable_hdmi(struct intel_atomic_state *state, 359 struct intel_encoder *encoder, 360 const struct intel_crtc_state *old_crtc_state, 361 const struct drm_connector_state *old_conn_state) 362 { 363 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 364 365 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 366 } 367 368 static void pch_disable_hdmi(struct intel_atomic_state *state, 369 struct intel_encoder *encoder, 370 const struct intel_crtc_state *old_crtc_state, 371 const struct drm_connector_state *old_conn_state) 372 { 373 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 374 } 375 376 static void pch_post_disable_hdmi(struct intel_atomic_state *state, 377 struct intel_encoder *encoder, 378 const struct intel_crtc_state *old_crtc_state, 379 const struct drm_connector_state *old_conn_state) 380 { 381 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 382 } 383 384 static void intel_hdmi_pre_enable(struct intel_atomic_state *state, 385 struct intel_encoder *encoder, 386 const struct intel_crtc_state *pipe_config, 387 const struct drm_connector_state *conn_state) 388 { 389 struct intel_digital_port *dig_port = 390 enc_to_dig_port(encoder); 391 392 intel_hdmi_prepare(encoder, pipe_config); 393 394 dig_port->set_infoframes(encoder, 395 pipe_config->has_infoframe, 396 pipe_config, conn_state); 397 } 398 399 static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, 400 struct intel_encoder *encoder, 401 const struct intel_crtc_state *pipe_config, 402 const struct drm_connector_state *conn_state) 403 { 404 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 405 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 406 407 vlv_phy_pre_encoder_enable(encoder, pipe_config); 408 409 /* HDMI 1.0V-2dB */ 410 vlv_set_phy_signal_level(encoder, pipe_config, 411 0x2b245f5f, 0x00002000, 412 0x5578b83a, 0x2b247878); 413 414 dig_port->set_infoframes(encoder, 415 pipe_config->has_infoframe, 416 pipe_config, conn_state); 417 418 g4x_enable_hdmi(state, encoder, pipe_config, conn_state); 419 420 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 421 } 422 423 static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 424 struct intel_encoder *encoder, 425 const struct intel_crtc_state *pipe_config, 426 const struct drm_connector_state *conn_state) 427 { 428 intel_hdmi_prepare(encoder, pipe_config); 429 430 vlv_phy_pre_pll_enable(encoder, pipe_config); 431 } 432 433 static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 434 struct intel_encoder *encoder, 435 const struct intel_crtc_state *pipe_config, 436 const struct drm_connector_state *conn_state) 437 { 438 intel_hdmi_prepare(encoder, pipe_config); 439 440 chv_phy_pre_pll_enable(encoder, pipe_config); 441 } 442 443 static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state, 444 struct intel_encoder *encoder, 445 const struct intel_crtc_state *old_crtc_state, 446 const struct drm_connector_state *old_conn_state) 447 { 448 chv_phy_post_pll_disable(encoder, old_crtc_state); 449 } 450 451 static void vlv_hdmi_post_disable(struct intel_atomic_state *state, 452 struct intel_encoder *encoder, 453 const struct intel_crtc_state *old_crtc_state, 454 const struct drm_connector_state *old_conn_state) 455 { 456 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 457 vlv_phy_reset_lanes(encoder, old_crtc_state); 458 } 459 460 static void chv_hdmi_post_disable(struct intel_atomic_state *state, 461 struct intel_encoder *encoder, 462 const struct intel_crtc_state *old_crtc_state, 463 const struct drm_connector_state *old_conn_state) 464 { 465 struct drm_device *dev = encoder->base.dev; 466 struct drm_i915_private *dev_priv = to_i915(dev); 467 468 vlv_dpio_get(dev_priv); 469 470 /* Assert data lane reset */ 471 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 472 473 vlv_dpio_put(dev_priv); 474 } 475 476 static void chv_hdmi_pre_enable(struct intel_atomic_state *state, 477 struct intel_encoder *encoder, 478 const struct intel_crtc_state *pipe_config, 479 const struct drm_connector_state *conn_state) 480 { 481 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 482 struct drm_device *dev = encoder->base.dev; 483 struct drm_i915_private *dev_priv = to_i915(dev); 484 485 chv_phy_pre_encoder_enable(encoder, pipe_config); 486 487 /* FIXME: Program the support xxx V-dB */ 488 /* Use 800mV-0dB */ 489 chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false); 490 491 dig_port->set_infoframes(encoder, 492 pipe_config->has_infoframe, 493 pipe_config, conn_state); 494 495 g4x_enable_hdmi(state, encoder, pipe_config, conn_state); 496 497 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 498 499 /* Second common lane will stay alive on its own now */ 500 chv_phy_release_cl2_override(encoder); 501 } 502 503 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 504 .destroy = intel_encoder_destroy, 505 }; 506 507 static enum intel_hotplug_state 508 intel_hdmi_hotplug(struct intel_encoder *encoder, 509 struct intel_connector *connector) 510 { 511 enum intel_hotplug_state state; 512 513 state = intel_encoder_hotplug(encoder, connector); 514 515 /* 516 * On many platforms the HDMI live state signal is known to be 517 * unreliable, so we can't use it to detect if a sink is connected or 518 * not. Instead we detect if it's connected based on whether we can 519 * read the EDID or not. That in turn has a problem during disconnect, 520 * since the HPD interrupt may be raised before the DDC lines get 521 * disconnected (due to how the required length of DDC vs. HPD 522 * connector pins are specified) and so we'll still be able to get a 523 * valid EDID. To solve this schedule another detection cycle if this 524 * time around we didn't detect any change in the sink's connection 525 * status. 526 */ 527 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 528 state = INTEL_HOTPLUG_RETRY; 529 530 return state; 531 } 532 533 void g4x_hdmi_init(struct drm_i915_private *dev_priv, 534 i915_reg_t hdmi_reg, enum port port) 535 { 536 struct intel_digital_port *dig_port; 537 struct intel_encoder *intel_encoder; 538 struct intel_connector *intel_connector; 539 540 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 541 if (!dig_port) 542 return; 543 544 intel_connector = intel_connector_alloc(); 545 if (!intel_connector) { 546 kfree(dig_port); 547 return; 548 } 549 550 intel_encoder = &dig_port->base; 551 552 mutex_init(&dig_port->hdcp_mutex); 553 554 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 555 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 556 "HDMI %c", port_name(port)); 557 558 intel_encoder->hotplug = intel_hdmi_hotplug; 559 intel_encoder->compute_config = g4x_hdmi_compute_config; 560 if (HAS_PCH_SPLIT(dev_priv)) { 561 intel_encoder->disable = pch_disable_hdmi; 562 intel_encoder->post_disable = pch_post_disable_hdmi; 563 } else { 564 intel_encoder->disable = g4x_disable_hdmi; 565 } 566 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 567 intel_encoder->get_config = intel_hdmi_get_config; 568 if (IS_CHERRYVIEW(dev_priv)) { 569 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 570 intel_encoder->pre_enable = chv_hdmi_pre_enable; 571 intel_encoder->enable = vlv_enable_hdmi; 572 intel_encoder->post_disable = chv_hdmi_post_disable; 573 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 574 } else if (IS_VALLEYVIEW(dev_priv)) { 575 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 576 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 577 intel_encoder->enable = vlv_enable_hdmi; 578 intel_encoder->post_disable = vlv_hdmi_post_disable; 579 } else { 580 intel_encoder->pre_enable = intel_hdmi_pre_enable; 581 if (HAS_PCH_CPT(dev_priv)) 582 intel_encoder->enable = cpt_enable_hdmi; 583 else if (HAS_PCH_IBX(dev_priv)) 584 intel_encoder->enable = ibx_enable_hdmi; 585 else 586 intel_encoder->enable = g4x_enable_hdmi; 587 } 588 intel_encoder->shutdown = intel_hdmi_encoder_shutdown; 589 590 intel_encoder->type = INTEL_OUTPUT_HDMI; 591 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 592 intel_encoder->port = port; 593 if (IS_CHERRYVIEW(dev_priv)) { 594 if (port == PORT_D) 595 intel_encoder->pipe_mask = BIT(PIPE_C); 596 else 597 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 598 } else { 599 intel_encoder->pipe_mask = ~0; 600 } 601 intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG); 602 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 603 /* 604 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 605 * to work on real hardware. And since g4x can send infoframes to 606 * only one port anyway, nothing is lost by allowing it. 607 */ 608 if (IS_G4X(dev_priv)) 609 intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI); 610 611 dig_port->hdmi.hdmi_reg = hdmi_reg; 612 dig_port->dp.output_reg = INVALID_MMIO_REG; 613 dig_port->max_lanes = 4; 614 615 intel_infoframe_init(dig_port); 616 617 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 618 intel_hdmi_init_connector(dig_port, intel_connector); 619 } 620