1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code). 6 */ 7 8 #include "g4x_hdmi.h" 9 #include "i915_reg.h" 10 #include "intel_audio.h" 11 #include "intel_connector.h" 12 #include "intel_crtc.h" 13 #include "intel_de.h" 14 #include "intel_display_power.h" 15 #include "intel_display_types.h" 16 #include "intel_dpio_phy.h" 17 #include "intel_fifo_underrun.h" 18 #include "intel_hdmi.h" 19 #include "intel_hotplug.h" 20 #include "intel_sdvo.h" 21 #include "vlv_sideband.h" 22 23 static void intel_hdmi_prepare(struct intel_encoder *encoder, 24 const struct intel_crtc_state *crtc_state) 25 { 26 struct drm_device *dev = encoder->base.dev; 27 struct drm_i915_private *dev_priv = to_i915(dev); 28 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 29 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 30 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 31 u32 hdmi_val; 32 33 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 34 35 hdmi_val = SDVO_ENCODING_HDMI; 36 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 37 hdmi_val |= HDMI_COLOR_RANGE_16_235; 38 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 39 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 40 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 41 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 42 43 if (crtc_state->pipe_bpp > 24) 44 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 45 else 46 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 47 48 if (crtc_state->has_hdmi_sink) 49 hdmi_val |= HDMI_MODE_SELECT_HDMI; 50 51 if (HAS_PCH_CPT(dev_priv)) 52 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 53 else if (IS_CHERRYVIEW(dev_priv)) 54 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 55 else 56 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 57 58 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); 59 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 60 } 61 62 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 63 enum pipe *pipe) 64 { 65 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 66 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 67 intel_wakeref_t wakeref; 68 bool ret; 69 70 wakeref = intel_display_power_get_if_enabled(dev_priv, 71 encoder->power_domain); 72 if (!wakeref) 73 return false; 74 75 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); 76 77 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 78 79 return ret; 80 } 81 82 static int g4x_hdmi_compute_config(struct intel_encoder *encoder, 83 struct intel_crtc_state *crtc_state, 84 struct drm_connector_state *conn_state) 85 { 86 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 87 88 if (HAS_PCH_SPLIT(i915)) 89 crtc_state->has_pch_encoder = true; 90 91 return intel_hdmi_compute_config(encoder, crtc_state, conn_state); 92 } 93 94 static void intel_hdmi_get_config(struct intel_encoder *encoder, 95 struct intel_crtc_state *pipe_config) 96 { 97 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 98 struct drm_device *dev = encoder->base.dev; 99 struct drm_i915_private *dev_priv = to_i915(dev); 100 u32 tmp, flags = 0; 101 int dotclock; 102 103 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 104 105 tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 106 107 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 108 flags |= DRM_MODE_FLAG_PHSYNC; 109 else 110 flags |= DRM_MODE_FLAG_NHSYNC; 111 112 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 113 flags |= DRM_MODE_FLAG_PVSYNC; 114 else 115 flags |= DRM_MODE_FLAG_NVSYNC; 116 117 if (tmp & HDMI_MODE_SELECT_HDMI) 118 pipe_config->has_hdmi_sink = true; 119 120 pipe_config->infoframes.enable |= 121 intel_hdmi_infoframes_enabled(encoder, pipe_config); 122 123 if (pipe_config->infoframes.enable) 124 pipe_config->has_infoframe = true; 125 126 if (tmp & HDMI_AUDIO_ENABLE) 127 pipe_config->has_audio = true; 128 129 if (!HAS_PCH_SPLIT(dev_priv) && 130 tmp & HDMI_COLOR_RANGE_16_235) 131 pipe_config->limited_color_range = true; 132 133 pipe_config->hw.adjusted_mode.flags |= flags; 134 135 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 136 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 2, 3); 137 else 138 dotclock = pipe_config->port_clock; 139 140 if (pipe_config->pixel_multiplier) 141 dotclock /= pipe_config->pixel_multiplier; 142 143 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 144 145 pipe_config->lane_count = 4; 146 147 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 148 149 intel_read_infoframe(encoder, pipe_config, 150 HDMI_INFOFRAME_TYPE_AVI, 151 &pipe_config->infoframes.avi); 152 intel_read_infoframe(encoder, pipe_config, 153 HDMI_INFOFRAME_TYPE_SPD, 154 &pipe_config->infoframes.spd); 155 intel_read_infoframe(encoder, pipe_config, 156 HDMI_INFOFRAME_TYPE_VENDOR, 157 &pipe_config->infoframes.hdmi); 158 159 intel_audio_codec_get_config(encoder, pipe_config); 160 } 161 162 static void g4x_hdmi_enable_port(struct intel_encoder *encoder, 163 const struct intel_crtc_state *pipe_config) 164 { 165 struct drm_device *dev = encoder->base.dev; 166 struct drm_i915_private *dev_priv = to_i915(dev); 167 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 168 u32 temp; 169 170 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 171 172 temp |= SDVO_ENABLE; 173 if (pipe_config->has_audio) 174 temp |= HDMI_AUDIO_ENABLE; 175 176 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 177 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 178 } 179 180 static void g4x_enable_hdmi(struct intel_atomic_state *state, 181 struct intel_encoder *encoder, 182 const struct intel_crtc_state *pipe_config, 183 const struct drm_connector_state *conn_state) 184 { 185 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 186 187 g4x_hdmi_enable_port(encoder, pipe_config); 188 189 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 190 !pipe_config->has_hdmi_sink); 191 intel_audio_codec_enable(encoder, pipe_config, conn_state); 192 } 193 194 static void ibx_enable_hdmi(struct intel_atomic_state *state, 195 struct intel_encoder *encoder, 196 const struct intel_crtc_state *pipe_config, 197 const struct drm_connector_state *conn_state) 198 { 199 struct drm_device *dev = encoder->base.dev; 200 struct drm_i915_private *dev_priv = to_i915(dev); 201 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 202 u32 temp; 203 204 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 205 206 temp |= SDVO_ENABLE; 207 if (pipe_config->has_audio) 208 temp |= HDMI_AUDIO_ENABLE; 209 210 /* 211 * HW workaround, need to write this twice for issue 212 * that may result in first write getting masked. 213 */ 214 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 215 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 216 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 217 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 218 219 /* 220 * HW workaround, need to toggle enable bit off and on 221 * for 12bpc with pixel repeat. 222 * 223 * FIXME: BSpec says this should be done at the end of 224 * the modeset sequence, so not sure if this isn't too soon. 225 */ 226 if (pipe_config->pipe_bpp > 24 && 227 pipe_config->pixel_multiplier > 1) { 228 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, 229 temp & ~SDVO_ENABLE); 230 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 231 232 /* 233 * HW workaround, need to write this twice for issue 234 * that may result in first write getting masked. 235 */ 236 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 237 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 238 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 239 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 240 } 241 242 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 243 !pipe_config->has_hdmi_sink); 244 intel_audio_codec_enable(encoder, pipe_config, conn_state); 245 } 246 247 static void cpt_enable_hdmi(struct intel_atomic_state *state, 248 struct intel_encoder *encoder, 249 const struct intel_crtc_state *pipe_config, 250 const struct drm_connector_state *conn_state) 251 { 252 struct drm_device *dev = encoder->base.dev; 253 struct drm_i915_private *dev_priv = to_i915(dev); 254 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 255 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 256 enum pipe pipe = crtc->pipe; 257 u32 temp; 258 259 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 260 261 temp |= SDVO_ENABLE; 262 if (pipe_config->has_audio) 263 temp |= HDMI_AUDIO_ENABLE; 264 265 /* 266 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 267 * 268 * The procedure for 12bpc is as follows: 269 * 1. disable HDMI clock gating 270 * 2. enable HDMI with 8bpc 271 * 3. enable HDMI with 12bpc 272 * 4. enable HDMI clock gating 273 */ 274 275 if (pipe_config->pipe_bpp > 24) { 276 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), 277 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 278 279 temp &= ~SDVO_COLOR_FORMAT_MASK; 280 temp |= SDVO_COLOR_FORMAT_8bpc; 281 } 282 283 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 284 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 285 286 if (pipe_config->pipe_bpp > 24) { 287 temp &= ~SDVO_COLOR_FORMAT_MASK; 288 temp |= HDMI_COLOR_FORMAT_12bpc; 289 290 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 291 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 292 293 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), 294 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 295 } 296 297 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 298 !pipe_config->has_hdmi_sink); 299 intel_audio_codec_enable(encoder, pipe_config, conn_state); 300 } 301 302 static void vlv_enable_hdmi(struct intel_atomic_state *state, 303 struct intel_encoder *encoder, 304 const struct intel_crtc_state *pipe_config, 305 const struct drm_connector_state *conn_state) 306 { 307 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 308 309 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 310 !pipe_config->has_hdmi_sink); 311 intel_audio_codec_enable(encoder, pipe_config, conn_state); 312 } 313 314 static void intel_disable_hdmi(struct intel_atomic_state *state, 315 struct intel_encoder *encoder, 316 const struct intel_crtc_state *old_crtc_state, 317 const struct drm_connector_state *old_conn_state) 318 { 319 struct drm_device *dev = encoder->base.dev; 320 struct drm_i915_private *dev_priv = to_i915(dev); 321 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 322 struct intel_digital_port *dig_port = 323 hdmi_to_dig_port(intel_hdmi); 324 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 325 u32 temp; 326 327 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 328 329 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); 330 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 331 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 332 333 /* 334 * HW workaround for IBX, we need to move the port 335 * to transcoder A after disabling it to allow the 336 * matching DP port to be enabled on transcoder A. 337 */ 338 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 339 /* 340 * We get CPU/PCH FIFO underruns on the other pipe when 341 * doing the workaround. Sweep them under the rug. 342 */ 343 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 344 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 345 346 temp &= ~SDVO_PIPE_SEL_MASK; 347 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 348 /* 349 * HW workaround, need to write this twice for issue 350 * that may result in first write getting masked. 351 */ 352 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 353 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 354 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 355 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 356 357 temp &= ~SDVO_ENABLE; 358 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 359 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 360 361 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 362 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 363 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 364 } 365 366 dig_port->set_infoframes(encoder, 367 false, 368 old_crtc_state, old_conn_state); 369 370 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 371 } 372 373 static void g4x_disable_hdmi(struct intel_atomic_state *state, 374 struct intel_encoder *encoder, 375 const struct intel_crtc_state *old_crtc_state, 376 const struct drm_connector_state *old_conn_state) 377 { 378 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 379 380 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 381 } 382 383 static void pch_disable_hdmi(struct intel_atomic_state *state, 384 struct intel_encoder *encoder, 385 const struct intel_crtc_state *old_crtc_state, 386 const struct drm_connector_state *old_conn_state) 387 { 388 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 389 } 390 391 static void pch_post_disable_hdmi(struct intel_atomic_state *state, 392 struct intel_encoder *encoder, 393 const struct intel_crtc_state *old_crtc_state, 394 const struct drm_connector_state *old_conn_state) 395 { 396 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 397 } 398 399 static void intel_hdmi_pre_enable(struct intel_atomic_state *state, 400 struct intel_encoder *encoder, 401 const struct intel_crtc_state *pipe_config, 402 const struct drm_connector_state *conn_state) 403 { 404 struct intel_digital_port *dig_port = 405 enc_to_dig_port(encoder); 406 407 intel_hdmi_prepare(encoder, pipe_config); 408 409 dig_port->set_infoframes(encoder, 410 pipe_config->has_infoframe, 411 pipe_config, conn_state); 412 } 413 414 static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, 415 struct intel_encoder *encoder, 416 const struct intel_crtc_state *pipe_config, 417 const struct drm_connector_state *conn_state) 418 { 419 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 420 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 421 422 vlv_phy_pre_encoder_enable(encoder, pipe_config); 423 424 /* HDMI 1.0V-2dB */ 425 vlv_set_phy_signal_level(encoder, pipe_config, 426 0x2b245f5f, 0x00002000, 427 0x5578b83a, 0x2b247878); 428 429 dig_port->set_infoframes(encoder, 430 pipe_config->has_infoframe, 431 pipe_config, conn_state); 432 433 g4x_hdmi_enable_port(encoder, pipe_config); 434 435 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 436 } 437 438 static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 439 struct intel_encoder *encoder, 440 const struct intel_crtc_state *pipe_config, 441 const struct drm_connector_state *conn_state) 442 { 443 intel_hdmi_prepare(encoder, pipe_config); 444 445 vlv_phy_pre_pll_enable(encoder, pipe_config); 446 } 447 448 static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 449 struct intel_encoder *encoder, 450 const struct intel_crtc_state *pipe_config, 451 const struct drm_connector_state *conn_state) 452 { 453 intel_hdmi_prepare(encoder, pipe_config); 454 455 chv_phy_pre_pll_enable(encoder, pipe_config); 456 } 457 458 static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state, 459 struct intel_encoder *encoder, 460 const struct intel_crtc_state *old_crtc_state, 461 const struct drm_connector_state *old_conn_state) 462 { 463 chv_phy_post_pll_disable(encoder, old_crtc_state); 464 } 465 466 static void vlv_hdmi_post_disable(struct intel_atomic_state *state, 467 struct intel_encoder *encoder, 468 const struct intel_crtc_state *old_crtc_state, 469 const struct drm_connector_state *old_conn_state) 470 { 471 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 472 vlv_phy_reset_lanes(encoder, old_crtc_state); 473 } 474 475 static void chv_hdmi_post_disable(struct intel_atomic_state *state, 476 struct intel_encoder *encoder, 477 const struct intel_crtc_state *old_crtc_state, 478 const struct drm_connector_state *old_conn_state) 479 { 480 struct drm_device *dev = encoder->base.dev; 481 struct drm_i915_private *dev_priv = to_i915(dev); 482 483 vlv_dpio_get(dev_priv); 484 485 /* Assert data lane reset */ 486 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 487 488 vlv_dpio_put(dev_priv); 489 } 490 491 static void chv_hdmi_pre_enable(struct intel_atomic_state *state, 492 struct intel_encoder *encoder, 493 const struct intel_crtc_state *pipe_config, 494 const struct drm_connector_state *conn_state) 495 { 496 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 497 struct drm_device *dev = encoder->base.dev; 498 struct drm_i915_private *dev_priv = to_i915(dev); 499 500 chv_phy_pre_encoder_enable(encoder, pipe_config); 501 502 /* FIXME: Program the support xxx V-dB */ 503 /* Use 800mV-0dB */ 504 chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false); 505 506 dig_port->set_infoframes(encoder, 507 pipe_config->has_infoframe, 508 pipe_config, conn_state); 509 510 g4x_hdmi_enable_port(encoder, pipe_config); 511 512 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 513 514 /* Second common lane will stay alive on its own now */ 515 chv_phy_release_cl2_override(encoder); 516 } 517 518 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 519 .destroy = intel_encoder_destroy, 520 }; 521 522 static enum intel_hotplug_state 523 intel_hdmi_hotplug(struct intel_encoder *encoder, 524 struct intel_connector *connector) 525 { 526 enum intel_hotplug_state state; 527 528 state = intel_encoder_hotplug(encoder, connector); 529 530 /* 531 * On many platforms the HDMI live state signal is known to be 532 * unreliable, so we can't use it to detect if a sink is connected or 533 * not. Instead we detect if it's connected based on whether we can 534 * read the EDID or not. That in turn has a problem during disconnect, 535 * since the HPD interrupt may be raised before the DDC lines get 536 * disconnected (due to how the required length of DDC vs. HPD 537 * connector pins are specified) and so we'll still be able to get a 538 * valid EDID. To solve this schedule another detection cycle if this 539 * time around we didn't detect any change in the sink's connection 540 * status. 541 */ 542 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 543 state = INTEL_HOTPLUG_RETRY; 544 545 return state; 546 } 547 548 void g4x_hdmi_init(struct drm_i915_private *dev_priv, 549 i915_reg_t hdmi_reg, enum port port) 550 { 551 struct intel_digital_port *dig_port; 552 struct intel_encoder *intel_encoder; 553 struct intel_connector *intel_connector; 554 555 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 556 if (!dig_port) 557 return; 558 559 intel_connector = intel_connector_alloc(); 560 if (!intel_connector) { 561 kfree(dig_port); 562 return; 563 } 564 565 intel_encoder = &dig_port->base; 566 567 mutex_init(&dig_port->hdcp_mutex); 568 569 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 570 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 571 "HDMI %c", port_name(port)); 572 573 intel_encoder->hotplug = intel_hdmi_hotplug; 574 intel_encoder->compute_config = g4x_hdmi_compute_config; 575 if (HAS_PCH_SPLIT(dev_priv)) { 576 intel_encoder->disable = pch_disable_hdmi; 577 intel_encoder->post_disable = pch_post_disable_hdmi; 578 } else { 579 intel_encoder->disable = g4x_disable_hdmi; 580 } 581 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 582 intel_encoder->get_config = intel_hdmi_get_config; 583 if (IS_CHERRYVIEW(dev_priv)) { 584 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 585 intel_encoder->pre_enable = chv_hdmi_pre_enable; 586 intel_encoder->enable = vlv_enable_hdmi; 587 intel_encoder->post_disable = chv_hdmi_post_disable; 588 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 589 } else if (IS_VALLEYVIEW(dev_priv)) { 590 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 591 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 592 intel_encoder->enable = vlv_enable_hdmi; 593 intel_encoder->post_disable = vlv_hdmi_post_disable; 594 } else { 595 intel_encoder->pre_enable = intel_hdmi_pre_enable; 596 if (HAS_PCH_CPT(dev_priv)) 597 intel_encoder->enable = cpt_enable_hdmi; 598 else if (HAS_PCH_IBX(dev_priv)) 599 intel_encoder->enable = ibx_enable_hdmi; 600 else 601 intel_encoder->enable = g4x_enable_hdmi; 602 } 603 intel_encoder->shutdown = intel_hdmi_encoder_shutdown; 604 605 intel_encoder->type = INTEL_OUTPUT_HDMI; 606 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 607 intel_encoder->port = port; 608 if (IS_CHERRYVIEW(dev_priv)) { 609 if (port == PORT_D) 610 intel_encoder->pipe_mask = BIT(PIPE_C); 611 else 612 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 613 } else { 614 intel_encoder->pipe_mask = ~0; 615 } 616 intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG); 617 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 618 /* 619 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 620 * to work on real hardware. And since g4x can send infoframes to 621 * only one port anyway, nothing is lost by allowing it. 622 */ 623 if (IS_G4X(dev_priv)) 624 intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI); 625 626 dig_port->hdmi.hdmi_reg = hdmi_reg; 627 dig_port->dp.output_reg = INVALID_MMIO_REG; 628 dig_port->max_lanes = 4; 629 630 intel_infoframe_init(dig_port); 631 632 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 633 intel_hdmi_init_connector(dig_port, intel_connector); 634 } 635