1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code). 6 */ 7 8 #include "g4x_hdmi.h" 9 #include "i915_reg.h" 10 #include "intel_audio.h" 11 #include "intel_connector.h" 12 #include "intel_crtc.h" 13 #include "intel_de.h" 14 #include "intel_display_power.h" 15 #include "intel_display_types.h" 16 #include "intel_dpio_phy.h" 17 #include "intel_fifo_underrun.h" 18 #include "intel_hdmi.h" 19 #include "intel_hotplug.h" 20 #include "intel_sdvo.h" 21 #include "vlv_sideband.h" 22 23 static void intel_hdmi_prepare(struct intel_encoder *encoder, 24 const struct intel_crtc_state *crtc_state) 25 { 26 struct drm_device *dev = encoder->base.dev; 27 struct drm_i915_private *dev_priv = to_i915(dev); 28 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 29 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 30 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 31 u32 hdmi_val; 32 33 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 34 35 hdmi_val = SDVO_ENCODING_HDMI; 36 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 37 hdmi_val |= HDMI_COLOR_RANGE_16_235; 38 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 39 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 40 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 41 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 42 43 if (crtc_state->pipe_bpp > 24) 44 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 45 else 46 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 47 48 if (crtc_state->has_hdmi_sink) 49 hdmi_val |= HDMI_MODE_SELECT_HDMI; 50 51 if (HAS_PCH_CPT(dev_priv)) 52 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 53 else if (IS_CHERRYVIEW(dev_priv)) 54 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 55 else 56 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 57 58 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); 59 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 60 } 61 62 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 63 enum pipe *pipe) 64 { 65 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 66 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 67 intel_wakeref_t wakeref; 68 bool ret; 69 70 wakeref = intel_display_power_get_if_enabled(dev_priv, 71 encoder->power_domain); 72 if (!wakeref) 73 return false; 74 75 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); 76 77 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 78 79 return ret; 80 } 81 82 static void intel_hdmi_get_config(struct intel_encoder *encoder, 83 struct intel_crtc_state *pipe_config) 84 { 85 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 86 struct drm_device *dev = encoder->base.dev; 87 struct drm_i915_private *dev_priv = to_i915(dev); 88 u32 tmp, flags = 0; 89 int dotclock; 90 91 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 92 93 tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 94 95 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 96 flags |= DRM_MODE_FLAG_PHSYNC; 97 else 98 flags |= DRM_MODE_FLAG_NHSYNC; 99 100 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 101 flags |= DRM_MODE_FLAG_PVSYNC; 102 else 103 flags |= DRM_MODE_FLAG_NVSYNC; 104 105 if (tmp & HDMI_MODE_SELECT_HDMI) 106 pipe_config->has_hdmi_sink = true; 107 108 pipe_config->infoframes.enable |= 109 intel_hdmi_infoframes_enabled(encoder, pipe_config); 110 111 if (pipe_config->infoframes.enable) 112 pipe_config->has_infoframe = true; 113 114 if (tmp & HDMI_AUDIO_ENABLE) 115 pipe_config->has_audio = true; 116 117 if (!HAS_PCH_SPLIT(dev_priv) && 118 tmp & HDMI_COLOR_RANGE_16_235) 119 pipe_config->limited_color_range = true; 120 121 pipe_config->hw.adjusted_mode.flags |= flags; 122 123 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 124 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 2, 3); 125 else 126 dotclock = pipe_config->port_clock; 127 128 if (pipe_config->pixel_multiplier) 129 dotclock /= pipe_config->pixel_multiplier; 130 131 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 132 133 pipe_config->lane_count = 4; 134 135 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 136 137 intel_read_infoframe(encoder, pipe_config, 138 HDMI_INFOFRAME_TYPE_AVI, 139 &pipe_config->infoframes.avi); 140 intel_read_infoframe(encoder, pipe_config, 141 HDMI_INFOFRAME_TYPE_SPD, 142 &pipe_config->infoframes.spd); 143 intel_read_infoframe(encoder, pipe_config, 144 HDMI_INFOFRAME_TYPE_VENDOR, 145 &pipe_config->infoframes.hdmi); 146 } 147 148 static void g4x_enable_hdmi(struct intel_atomic_state *state, 149 struct intel_encoder *encoder, 150 const struct intel_crtc_state *pipe_config, 151 const struct drm_connector_state *conn_state) 152 { 153 struct drm_device *dev = encoder->base.dev; 154 struct drm_i915_private *dev_priv = to_i915(dev); 155 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 156 u32 temp; 157 158 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 159 160 temp |= SDVO_ENABLE; 161 if (pipe_config->has_audio) 162 temp |= HDMI_AUDIO_ENABLE; 163 164 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 165 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 166 167 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 168 !pipe_config->has_hdmi_sink); 169 intel_audio_codec_enable(encoder, pipe_config, conn_state); 170 } 171 172 static void ibx_enable_hdmi(struct intel_atomic_state *state, 173 struct intel_encoder *encoder, 174 const struct intel_crtc_state *pipe_config, 175 const struct drm_connector_state *conn_state) 176 { 177 struct drm_device *dev = encoder->base.dev; 178 struct drm_i915_private *dev_priv = to_i915(dev); 179 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 180 u32 temp; 181 182 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 183 184 temp |= SDVO_ENABLE; 185 if (pipe_config->has_audio) 186 temp |= HDMI_AUDIO_ENABLE; 187 188 /* 189 * HW workaround, need to write this twice for issue 190 * that may result in first write getting masked. 191 */ 192 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 193 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 194 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 195 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 196 197 /* 198 * HW workaround, need to toggle enable bit off and on 199 * for 12bpc with pixel repeat. 200 * 201 * FIXME: BSpec says this should be done at the end of 202 * the modeset sequence, so not sure if this isn't too soon. 203 */ 204 if (pipe_config->pipe_bpp > 24 && 205 pipe_config->pixel_multiplier > 1) { 206 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, 207 temp & ~SDVO_ENABLE); 208 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 209 210 /* 211 * HW workaround, need to write this twice for issue 212 * that may result in first write getting masked. 213 */ 214 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 215 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 216 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 217 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 218 } 219 220 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 221 !pipe_config->has_hdmi_sink); 222 intel_audio_codec_enable(encoder, pipe_config, conn_state); 223 } 224 225 static void cpt_enable_hdmi(struct intel_atomic_state *state, 226 struct intel_encoder *encoder, 227 const struct intel_crtc_state *pipe_config, 228 const struct drm_connector_state *conn_state) 229 { 230 struct drm_device *dev = encoder->base.dev; 231 struct drm_i915_private *dev_priv = to_i915(dev); 232 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 233 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 234 enum pipe pipe = crtc->pipe; 235 u32 temp; 236 237 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 238 239 temp |= SDVO_ENABLE; 240 if (pipe_config->has_audio) 241 temp |= HDMI_AUDIO_ENABLE; 242 243 /* 244 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 245 * 246 * The procedure for 12bpc is as follows: 247 * 1. disable HDMI clock gating 248 * 2. enable HDMI with 8bpc 249 * 3. enable HDMI with 12bpc 250 * 4. enable HDMI clock gating 251 */ 252 253 if (pipe_config->pipe_bpp > 24) { 254 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), 255 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 256 257 temp &= ~SDVO_COLOR_FORMAT_MASK; 258 temp |= SDVO_COLOR_FORMAT_8bpc; 259 } 260 261 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 262 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 263 264 if (pipe_config->pipe_bpp > 24) { 265 temp &= ~SDVO_COLOR_FORMAT_MASK; 266 temp |= HDMI_COLOR_FORMAT_12bpc; 267 268 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 269 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 270 271 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), 272 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 273 } 274 275 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 276 !pipe_config->has_hdmi_sink); 277 intel_audio_codec_enable(encoder, pipe_config, conn_state); 278 } 279 280 static void vlv_enable_hdmi(struct intel_atomic_state *state, 281 struct intel_encoder *encoder, 282 const struct intel_crtc_state *pipe_config, 283 const struct drm_connector_state *conn_state) 284 { 285 } 286 287 static void intel_disable_hdmi(struct intel_atomic_state *state, 288 struct intel_encoder *encoder, 289 const struct intel_crtc_state *old_crtc_state, 290 const struct drm_connector_state *old_conn_state) 291 { 292 struct drm_device *dev = encoder->base.dev; 293 struct drm_i915_private *dev_priv = to_i915(dev); 294 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 295 struct intel_digital_port *dig_port = 296 hdmi_to_dig_port(intel_hdmi); 297 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 298 u32 temp; 299 300 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 301 302 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); 303 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 304 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 305 306 /* 307 * HW workaround for IBX, we need to move the port 308 * to transcoder A after disabling it to allow the 309 * matching DP port to be enabled on transcoder A. 310 */ 311 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 312 /* 313 * We get CPU/PCH FIFO underruns on the other pipe when 314 * doing the workaround. Sweep them under the rug. 315 */ 316 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 317 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 318 319 temp &= ~SDVO_PIPE_SEL_MASK; 320 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 321 /* 322 * HW workaround, need to write this twice for issue 323 * that may result in first write getting masked. 324 */ 325 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 326 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 327 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 328 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 329 330 temp &= ~SDVO_ENABLE; 331 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 332 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 333 334 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 335 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 336 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 337 } 338 339 dig_port->set_infoframes(encoder, 340 false, 341 old_crtc_state, old_conn_state); 342 343 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 344 } 345 346 static void g4x_disable_hdmi(struct intel_atomic_state *state, 347 struct intel_encoder *encoder, 348 const struct intel_crtc_state *old_crtc_state, 349 const struct drm_connector_state *old_conn_state) 350 { 351 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 352 353 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 354 } 355 356 static void pch_disable_hdmi(struct intel_atomic_state *state, 357 struct intel_encoder *encoder, 358 const struct intel_crtc_state *old_crtc_state, 359 const struct drm_connector_state *old_conn_state) 360 { 361 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 362 } 363 364 static void pch_post_disable_hdmi(struct intel_atomic_state *state, 365 struct intel_encoder *encoder, 366 const struct intel_crtc_state *old_crtc_state, 367 const struct drm_connector_state *old_conn_state) 368 { 369 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 370 } 371 372 static void intel_hdmi_pre_enable(struct intel_atomic_state *state, 373 struct intel_encoder *encoder, 374 const struct intel_crtc_state *pipe_config, 375 const struct drm_connector_state *conn_state) 376 { 377 struct intel_digital_port *dig_port = 378 enc_to_dig_port(encoder); 379 380 intel_hdmi_prepare(encoder, pipe_config); 381 382 dig_port->set_infoframes(encoder, 383 pipe_config->has_infoframe, 384 pipe_config, conn_state); 385 } 386 387 static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, 388 struct intel_encoder *encoder, 389 const struct intel_crtc_state *pipe_config, 390 const struct drm_connector_state *conn_state) 391 { 392 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 393 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 394 395 vlv_phy_pre_encoder_enable(encoder, pipe_config); 396 397 /* HDMI 1.0V-2dB */ 398 vlv_set_phy_signal_level(encoder, pipe_config, 399 0x2b245f5f, 0x00002000, 400 0x5578b83a, 0x2b247878); 401 402 dig_port->set_infoframes(encoder, 403 pipe_config->has_infoframe, 404 pipe_config, conn_state); 405 406 g4x_enable_hdmi(state, encoder, pipe_config, conn_state); 407 408 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 409 } 410 411 static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 412 struct intel_encoder *encoder, 413 const struct intel_crtc_state *pipe_config, 414 const struct drm_connector_state *conn_state) 415 { 416 intel_hdmi_prepare(encoder, pipe_config); 417 418 vlv_phy_pre_pll_enable(encoder, pipe_config); 419 } 420 421 static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 422 struct intel_encoder *encoder, 423 const struct intel_crtc_state *pipe_config, 424 const struct drm_connector_state *conn_state) 425 { 426 intel_hdmi_prepare(encoder, pipe_config); 427 428 chv_phy_pre_pll_enable(encoder, pipe_config); 429 } 430 431 static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state, 432 struct intel_encoder *encoder, 433 const struct intel_crtc_state *old_crtc_state, 434 const struct drm_connector_state *old_conn_state) 435 { 436 chv_phy_post_pll_disable(encoder, old_crtc_state); 437 } 438 439 static void vlv_hdmi_post_disable(struct intel_atomic_state *state, 440 struct intel_encoder *encoder, 441 const struct intel_crtc_state *old_crtc_state, 442 const struct drm_connector_state *old_conn_state) 443 { 444 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 445 vlv_phy_reset_lanes(encoder, old_crtc_state); 446 } 447 448 static void chv_hdmi_post_disable(struct intel_atomic_state *state, 449 struct intel_encoder *encoder, 450 const struct intel_crtc_state *old_crtc_state, 451 const struct drm_connector_state *old_conn_state) 452 { 453 struct drm_device *dev = encoder->base.dev; 454 struct drm_i915_private *dev_priv = to_i915(dev); 455 456 vlv_dpio_get(dev_priv); 457 458 /* Assert data lane reset */ 459 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 460 461 vlv_dpio_put(dev_priv); 462 } 463 464 static void chv_hdmi_pre_enable(struct intel_atomic_state *state, 465 struct intel_encoder *encoder, 466 const struct intel_crtc_state *pipe_config, 467 const struct drm_connector_state *conn_state) 468 { 469 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 470 struct drm_device *dev = encoder->base.dev; 471 struct drm_i915_private *dev_priv = to_i915(dev); 472 473 chv_phy_pre_encoder_enable(encoder, pipe_config); 474 475 /* FIXME: Program the support xxx V-dB */ 476 /* Use 800mV-0dB */ 477 chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false); 478 479 dig_port->set_infoframes(encoder, 480 pipe_config->has_infoframe, 481 pipe_config, conn_state); 482 483 g4x_enable_hdmi(state, encoder, pipe_config, conn_state); 484 485 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 486 487 /* Second common lane will stay alive on its own now */ 488 chv_phy_release_cl2_override(encoder); 489 } 490 491 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 492 .destroy = intel_encoder_destroy, 493 }; 494 495 static enum intel_hotplug_state 496 intel_hdmi_hotplug(struct intel_encoder *encoder, 497 struct intel_connector *connector) 498 { 499 enum intel_hotplug_state state; 500 501 state = intel_encoder_hotplug(encoder, connector); 502 503 /* 504 * On many platforms the HDMI live state signal is known to be 505 * unreliable, so we can't use it to detect if a sink is connected or 506 * not. Instead we detect if it's connected based on whether we can 507 * read the EDID or not. That in turn has a problem during disconnect, 508 * since the HPD interrupt may be raised before the DDC lines get 509 * disconnected (due to how the required length of DDC vs. HPD 510 * connector pins are specified) and so we'll still be able to get a 511 * valid EDID. To solve this schedule another detection cycle if this 512 * time around we didn't detect any change in the sink's connection 513 * status. 514 */ 515 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 516 state = INTEL_HOTPLUG_RETRY; 517 518 return state; 519 } 520 521 void g4x_hdmi_init(struct drm_i915_private *dev_priv, 522 i915_reg_t hdmi_reg, enum port port) 523 { 524 struct intel_digital_port *dig_port; 525 struct intel_encoder *intel_encoder; 526 struct intel_connector *intel_connector; 527 528 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 529 if (!dig_port) 530 return; 531 532 intel_connector = intel_connector_alloc(); 533 if (!intel_connector) { 534 kfree(dig_port); 535 return; 536 } 537 538 intel_encoder = &dig_port->base; 539 540 mutex_init(&dig_port->hdcp_mutex); 541 542 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 543 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 544 "HDMI %c", port_name(port)); 545 546 intel_encoder->hotplug = intel_hdmi_hotplug; 547 intel_encoder->compute_config = intel_hdmi_compute_config; 548 if (HAS_PCH_SPLIT(dev_priv)) { 549 intel_encoder->disable = pch_disable_hdmi; 550 intel_encoder->post_disable = pch_post_disable_hdmi; 551 } else { 552 intel_encoder->disable = g4x_disable_hdmi; 553 } 554 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 555 intel_encoder->get_config = intel_hdmi_get_config; 556 if (IS_CHERRYVIEW(dev_priv)) { 557 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 558 intel_encoder->pre_enable = chv_hdmi_pre_enable; 559 intel_encoder->enable = vlv_enable_hdmi; 560 intel_encoder->post_disable = chv_hdmi_post_disable; 561 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 562 } else if (IS_VALLEYVIEW(dev_priv)) { 563 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 564 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 565 intel_encoder->enable = vlv_enable_hdmi; 566 intel_encoder->post_disable = vlv_hdmi_post_disable; 567 } else { 568 intel_encoder->pre_enable = intel_hdmi_pre_enable; 569 if (HAS_PCH_CPT(dev_priv)) 570 intel_encoder->enable = cpt_enable_hdmi; 571 else if (HAS_PCH_IBX(dev_priv)) 572 intel_encoder->enable = ibx_enable_hdmi; 573 else 574 intel_encoder->enable = g4x_enable_hdmi; 575 } 576 intel_encoder->shutdown = intel_hdmi_encoder_shutdown; 577 578 intel_encoder->type = INTEL_OUTPUT_HDMI; 579 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 580 intel_encoder->port = port; 581 if (IS_CHERRYVIEW(dev_priv)) { 582 if (port == PORT_D) 583 intel_encoder->pipe_mask = BIT(PIPE_C); 584 else 585 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 586 } else { 587 intel_encoder->pipe_mask = ~0; 588 } 589 intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG); 590 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 591 /* 592 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 593 * to work on real hardware. And since g4x can send infoframes to 594 * only one port anyway, nothing is lost by allowing it. 595 */ 596 if (IS_G4X(dev_priv)) 597 intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI); 598 599 dig_port->hdmi.hdmi_reg = hdmi_reg; 600 dig_port->dp.output_reg = INVALID_MMIO_REG; 601 dig_port->max_lanes = 4; 602 603 intel_infoframe_init(dig_port); 604 605 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 606 intel_hdmi_init_connector(dig_port, intel_connector); 607 } 608