1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code). 6 */ 7 8 #include "g4x_hdmi.h" 9 #include "i915_reg.h" 10 #include "intel_audio.h" 11 #include "intel_connector.h" 12 #include "intel_crtc.h" 13 #include "intel_de.h" 14 #include "intel_display_power.h" 15 #include "intel_display_types.h" 16 #include "intel_dp_aux.h" 17 #include "intel_dpio_phy.h" 18 #include "intel_fifo_underrun.h" 19 #include "intel_hdmi.h" 20 #include "intel_hotplug.h" 21 #include "intel_sdvo.h" 22 #include "vlv_sideband.h" 23 24 static void intel_hdmi_prepare(struct intel_encoder *encoder, 25 const struct intel_crtc_state *crtc_state) 26 { 27 struct drm_device *dev = encoder->base.dev; 28 struct drm_i915_private *dev_priv = to_i915(dev); 29 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 30 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 31 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 32 u32 hdmi_val; 33 34 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 35 36 hdmi_val = SDVO_ENCODING_HDMI; 37 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 38 hdmi_val |= HDMI_COLOR_RANGE_16_235; 39 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 40 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 41 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 42 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 43 44 if (crtc_state->pipe_bpp > 24) 45 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 46 else 47 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 48 49 if (crtc_state->has_hdmi_sink) 50 hdmi_val |= HDMI_MODE_SELECT_HDMI; 51 52 if (HAS_PCH_CPT(dev_priv)) 53 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 54 else if (IS_CHERRYVIEW(dev_priv)) 55 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 56 else 57 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 58 59 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); 60 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 61 } 62 63 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 64 enum pipe *pipe) 65 { 66 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 67 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 68 intel_wakeref_t wakeref; 69 bool ret; 70 71 wakeref = intel_display_power_get_if_enabled(dev_priv, 72 encoder->power_domain); 73 if (!wakeref) 74 return false; 75 76 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); 77 78 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 79 80 return ret; 81 } 82 83 static int g4x_hdmi_compute_config(struct intel_encoder *encoder, 84 struct intel_crtc_state *crtc_state, 85 struct drm_connector_state *conn_state) 86 { 87 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 88 89 if (HAS_PCH_SPLIT(i915)) 90 crtc_state->has_pch_encoder = true; 91 92 return intel_hdmi_compute_config(encoder, crtc_state, conn_state); 93 } 94 95 static void intel_hdmi_get_config(struct intel_encoder *encoder, 96 struct intel_crtc_state *pipe_config) 97 { 98 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 99 struct drm_device *dev = encoder->base.dev; 100 struct drm_i915_private *dev_priv = to_i915(dev); 101 u32 tmp, flags = 0; 102 int dotclock; 103 104 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 105 106 tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 107 108 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 109 flags |= DRM_MODE_FLAG_PHSYNC; 110 else 111 flags |= DRM_MODE_FLAG_NHSYNC; 112 113 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 114 flags |= DRM_MODE_FLAG_PVSYNC; 115 else 116 flags |= DRM_MODE_FLAG_NVSYNC; 117 118 if (tmp & HDMI_MODE_SELECT_HDMI) 119 pipe_config->has_hdmi_sink = true; 120 121 pipe_config->infoframes.enable |= 122 intel_hdmi_infoframes_enabled(encoder, pipe_config); 123 124 if (pipe_config->infoframes.enable) 125 pipe_config->has_infoframe = true; 126 127 if (tmp & HDMI_AUDIO_ENABLE) 128 pipe_config->has_audio = true; 129 130 if (!HAS_PCH_SPLIT(dev_priv) && 131 tmp & HDMI_COLOR_RANGE_16_235) 132 pipe_config->limited_color_range = true; 133 134 pipe_config->hw.adjusted_mode.flags |= flags; 135 136 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 137 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 2, 3); 138 else 139 dotclock = pipe_config->port_clock; 140 141 if (pipe_config->pixel_multiplier) 142 dotclock /= pipe_config->pixel_multiplier; 143 144 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 145 146 pipe_config->lane_count = 4; 147 148 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 149 150 intel_read_infoframe(encoder, pipe_config, 151 HDMI_INFOFRAME_TYPE_AVI, 152 &pipe_config->infoframes.avi); 153 intel_read_infoframe(encoder, pipe_config, 154 HDMI_INFOFRAME_TYPE_SPD, 155 &pipe_config->infoframes.spd); 156 intel_read_infoframe(encoder, pipe_config, 157 HDMI_INFOFRAME_TYPE_VENDOR, 158 &pipe_config->infoframes.hdmi); 159 160 intel_audio_codec_get_config(encoder, pipe_config); 161 } 162 163 static void g4x_hdmi_enable_port(struct intel_encoder *encoder, 164 const struct intel_crtc_state *pipe_config) 165 { 166 struct drm_device *dev = encoder->base.dev; 167 struct drm_i915_private *dev_priv = to_i915(dev); 168 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 169 u32 temp; 170 171 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 172 173 temp |= SDVO_ENABLE; 174 if (pipe_config->has_audio) 175 temp |= HDMI_AUDIO_ENABLE; 176 177 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 178 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 179 } 180 181 static void g4x_enable_hdmi(struct intel_atomic_state *state, 182 struct intel_encoder *encoder, 183 const struct intel_crtc_state *pipe_config, 184 const struct drm_connector_state *conn_state) 185 { 186 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 187 188 g4x_hdmi_enable_port(encoder, pipe_config); 189 190 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 191 !pipe_config->has_hdmi_sink); 192 intel_audio_codec_enable(encoder, pipe_config, conn_state); 193 } 194 195 static void ibx_enable_hdmi(struct intel_atomic_state *state, 196 struct intel_encoder *encoder, 197 const struct intel_crtc_state *pipe_config, 198 const struct drm_connector_state *conn_state) 199 { 200 struct drm_device *dev = encoder->base.dev; 201 struct drm_i915_private *dev_priv = to_i915(dev); 202 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 203 u32 temp; 204 205 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 206 207 temp |= SDVO_ENABLE; 208 if (pipe_config->has_audio) 209 temp |= HDMI_AUDIO_ENABLE; 210 211 /* 212 * HW workaround, need to write this twice for issue 213 * that may result in first write getting masked. 214 */ 215 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 216 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 217 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 218 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 219 220 /* 221 * HW workaround, need to toggle enable bit off and on 222 * for 12bpc with pixel repeat. 223 * 224 * FIXME: BSpec says this should be done at the end of 225 * the modeset sequence, so not sure if this isn't too soon. 226 */ 227 if (pipe_config->pipe_bpp > 24 && 228 pipe_config->pixel_multiplier > 1) { 229 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, 230 temp & ~SDVO_ENABLE); 231 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 232 233 /* 234 * HW workaround, need to write this twice for issue 235 * that may result in first write getting masked. 236 */ 237 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 238 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 239 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 240 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 241 } 242 243 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 244 !pipe_config->has_hdmi_sink); 245 intel_audio_codec_enable(encoder, pipe_config, conn_state); 246 } 247 248 static void cpt_enable_hdmi(struct intel_atomic_state *state, 249 struct intel_encoder *encoder, 250 const struct intel_crtc_state *pipe_config, 251 const struct drm_connector_state *conn_state) 252 { 253 struct drm_device *dev = encoder->base.dev; 254 struct drm_i915_private *dev_priv = to_i915(dev); 255 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 256 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 257 enum pipe pipe = crtc->pipe; 258 u32 temp; 259 260 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 261 262 temp |= SDVO_ENABLE; 263 if (pipe_config->has_audio) 264 temp |= HDMI_AUDIO_ENABLE; 265 266 /* 267 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 268 * 269 * The procedure for 12bpc is as follows: 270 * 1. disable HDMI clock gating 271 * 2. enable HDMI with 8bpc 272 * 3. enable HDMI with 12bpc 273 * 4. enable HDMI clock gating 274 */ 275 276 if (pipe_config->pipe_bpp > 24) { 277 intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe), 278 0, TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 279 280 temp &= ~SDVO_COLOR_FORMAT_MASK; 281 temp |= SDVO_COLOR_FORMAT_8bpc; 282 } 283 284 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 285 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 286 287 if (pipe_config->pipe_bpp > 24) { 288 temp &= ~SDVO_COLOR_FORMAT_MASK; 289 temp |= HDMI_COLOR_FORMAT_12bpc; 290 291 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 292 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 293 294 intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe), 295 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE, 0); 296 } 297 298 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 299 !pipe_config->has_hdmi_sink); 300 intel_audio_codec_enable(encoder, pipe_config, conn_state); 301 } 302 303 static void vlv_enable_hdmi(struct intel_atomic_state *state, 304 struct intel_encoder *encoder, 305 const struct intel_crtc_state *pipe_config, 306 const struct drm_connector_state *conn_state) 307 { 308 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 309 310 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 311 !pipe_config->has_hdmi_sink); 312 intel_audio_codec_enable(encoder, pipe_config, conn_state); 313 } 314 315 static void intel_disable_hdmi(struct intel_atomic_state *state, 316 struct intel_encoder *encoder, 317 const struct intel_crtc_state *old_crtc_state, 318 const struct drm_connector_state *old_conn_state) 319 { 320 struct drm_device *dev = encoder->base.dev; 321 struct drm_i915_private *dev_priv = to_i915(dev); 322 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 323 struct intel_digital_port *dig_port = 324 hdmi_to_dig_port(intel_hdmi); 325 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 326 u32 temp; 327 328 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 329 330 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); 331 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 332 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 333 334 /* 335 * HW workaround for IBX, we need to move the port 336 * to transcoder A after disabling it to allow the 337 * matching DP port to be enabled on transcoder A. 338 */ 339 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 340 /* 341 * We get CPU/PCH FIFO underruns on the other pipe when 342 * doing the workaround. Sweep them under the rug. 343 */ 344 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 345 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 346 347 temp &= ~SDVO_PIPE_SEL_MASK; 348 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 349 /* 350 * HW workaround, need to write this twice for issue 351 * that may result in first write getting masked. 352 */ 353 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 354 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 355 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 356 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 357 358 temp &= ~SDVO_ENABLE; 359 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 360 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 361 362 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 363 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 364 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 365 } 366 367 dig_port->set_infoframes(encoder, 368 false, 369 old_crtc_state, old_conn_state); 370 371 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 372 } 373 374 static void g4x_disable_hdmi(struct intel_atomic_state *state, 375 struct intel_encoder *encoder, 376 const struct intel_crtc_state *old_crtc_state, 377 const struct drm_connector_state *old_conn_state) 378 { 379 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 380 381 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 382 } 383 384 static void pch_disable_hdmi(struct intel_atomic_state *state, 385 struct intel_encoder *encoder, 386 const struct intel_crtc_state *old_crtc_state, 387 const struct drm_connector_state *old_conn_state) 388 { 389 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 390 } 391 392 static void pch_post_disable_hdmi(struct intel_atomic_state *state, 393 struct intel_encoder *encoder, 394 const struct intel_crtc_state *old_crtc_state, 395 const struct drm_connector_state *old_conn_state) 396 { 397 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 398 } 399 400 static void intel_hdmi_pre_enable(struct intel_atomic_state *state, 401 struct intel_encoder *encoder, 402 const struct intel_crtc_state *pipe_config, 403 const struct drm_connector_state *conn_state) 404 { 405 struct intel_digital_port *dig_port = 406 enc_to_dig_port(encoder); 407 408 intel_hdmi_prepare(encoder, pipe_config); 409 410 dig_port->set_infoframes(encoder, 411 pipe_config->has_infoframe, 412 pipe_config, conn_state); 413 } 414 415 static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, 416 struct intel_encoder *encoder, 417 const struct intel_crtc_state *pipe_config, 418 const struct drm_connector_state *conn_state) 419 { 420 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 421 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 422 423 vlv_phy_pre_encoder_enable(encoder, pipe_config); 424 425 /* HDMI 1.0V-2dB */ 426 vlv_set_phy_signal_level(encoder, pipe_config, 427 0x2b245f5f, 0x00002000, 428 0x5578b83a, 0x2b247878); 429 430 dig_port->set_infoframes(encoder, 431 pipe_config->has_infoframe, 432 pipe_config, conn_state); 433 434 g4x_hdmi_enable_port(encoder, pipe_config); 435 436 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 437 } 438 439 static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 440 struct intel_encoder *encoder, 441 const struct intel_crtc_state *pipe_config, 442 const struct drm_connector_state *conn_state) 443 { 444 intel_hdmi_prepare(encoder, pipe_config); 445 446 vlv_phy_pre_pll_enable(encoder, pipe_config); 447 } 448 449 static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 450 struct intel_encoder *encoder, 451 const struct intel_crtc_state *pipe_config, 452 const struct drm_connector_state *conn_state) 453 { 454 intel_hdmi_prepare(encoder, pipe_config); 455 456 chv_phy_pre_pll_enable(encoder, pipe_config); 457 } 458 459 static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state, 460 struct intel_encoder *encoder, 461 const struct intel_crtc_state *old_crtc_state, 462 const struct drm_connector_state *old_conn_state) 463 { 464 chv_phy_post_pll_disable(encoder, old_crtc_state); 465 } 466 467 static void vlv_hdmi_post_disable(struct intel_atomic_state *state, 468 struct intel_encoder *encoder, 469 const struct intel_crtc_state *old_crtc_state, 470 const struct drm_connector_state *old_conn_state) 471 { 472 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 473 vlv_phy_reset_lanes(encoder, old_crtc_state); 474 } 475 476 static void chv_hdmi_post_disable(struct intel_atomic_state *state, 477 struct intel_encoder *encoder, 478 const struct intel_crtc_state *old_crtc_state, 479 const struct drm_connector_state *old_conn_state) 480 { 481 struct drm_device *dev = encoder->base.dev; 482 struct drm_i915_private *dev_priv = to_i915(dev); 483 484 vlv_dpio_get(dev_priv); 485 486 /* Assert data lane reset */ 487 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 488 489 vlv_dpio_put(dev_priv); 490 } 491 492 static void chv_hdmi_pre_enable(struct intel_atomic_state *state, 493 struct intel_encoder *encoder, 494 const struct intel_crtc_state *pipe_config, 495 const struct drm_connector_state *conn_state) 496 { 497 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 498 struct drm_device *dev = encoder->base.dev; 499 struct drm_i915_private *dev_priv = to_i915(dev); 500 501 chv_phy_pre_encoder_enable(encoder, pipe_config); 502 503 /* FIXME: Program the support xxx V-dB */ 504 /* Use 800mV-0dB */ 505 chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false); 506 507 dig_port->set_infoframes(encoder, 508 pipe_config->has_infoframe, 509 pipe_config, conn_state); 510 511 g4x_hdmi_enable_port(encoder, pipe_config); 512 513 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 514 515 /* Second common lane will stay alive on its own now */ 516 chv_phy_release_cl2_override(encoder); 517 } 518 519 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 520 .destroy = intel_encoder_destroy, 521 }; 522 523 static enum intel_hotplug_state 524 intel_hdmi_hotplug(struct intel_encoder *encoder, 525 struct intel_connector *connector) 526 { 527 enum intel_hotplug_state state; 528 529 state = intel_encoder_hotplug(encoder, connector); 530 531 /* 532 * On many platforms the HDMI live state signal is known to be 533 * unreliable, so we can't use it to detect if a sink is connected or 534 * not. Instead we detect if it's connected based on whether we can 535 * read the EDID or not. That in turn has a problem during disconnect, 536 * since the HPD interrupt may be raised before the DDC lines get 537 * disconnected (due to how the required length of DDC vs. HPD 538 * connector pins are specified) and so we'll still be able to get a 539 * valid EDID. To solve this schedule another detection cycle if this 540 * time around we didn't detect any change in the sink's connection 541 * status. 542 */ 543 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 544 state = INTEL_HOTPLUG_RETRY; 545 546 return state; 547 } 548 549 void g4x_hdmi_init(struct drm_i915_private *dev_priv, 550 i915_reg_t hdmi_reg, enum port port) 551 { 552 const struct intel_bios_encoder_data *devdata; 553 struct intel_digital_port *dig_port; 554 struct intel_encoder *intel_encoder; 555 struct intel_connector *intel_connector; 556 557 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 558 559 /* FIXME bail? */ 560 if (!devdata) 561 drm_dbg_kms(&dev_priv->drm, "No VBT child device for HDMI-%c\n", 562 port_name(port)); 563 564 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 565 if (!dig_port) 566 return; 567 568 intel_connector = intel_connector_alloc(); 569 if (!intel_connector) { 570 kfree(dig_port); 571 return; 572 } 573 574 intel_encoder = &dig_port->base; 575 576 intel_encoder->devdata = devdata; 577 578 mutex_init(&dig_port->hdcp_mutex); 579 580 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 581 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 582 "HDMI %c", port_name(port)); 583 584 intel_encoder->hotplug = intel_hdmi_hotplug; 585 intel_encoder->compute_config = g4x_hdmi_compute_config; 586 if (HAS_PCH_SPLIT(dev_priv)) { 587 intel_encoder->disable = pch_disable_hdmi; 588 intel_encoder->post_disable = pch_post_disable_hdmi; 589 } else { 590 intel_encoder->disable = g4x_disable_hdmi; 591 } 592 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 593 intel_encoder->get_config = intel_hdmi_get_config; 594 if (IS_CHERRYVIEW(dev_priv)) { 595 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 596 intel_encoder->pre_enable = chv_hdmi_pre_enable; 597 intel_encoder->enable = vlv_enable_hdmi; 598 intel_encoder->post_disable = chv_hdmi_post_disable; 599 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 600 } else if (IS_VALLEYVIEW(dev_priv)) { 601 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 602 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 603 intel_encoder->enable = vlv_enable_hdmi; 604 intel_encoder->post_disable = vlv_hdmi_post_disable; 605 } else { 606 intel_encoder->pre_enable = intel_hdmi_pre_enable; 607 if (HAS_PCH_CPT(dev_priv)) 608 intel_encoder->enable = cpt_enable_hdmi; 609 else if (HAS_PCH_IBX(dev_priv)) 610 intel_encoder->enable = ibx_enable_hdmi; 611 else 612 intel_encoder->enable = g4x_enable_hdmi; 613 } 614 intel_encoder->shutdown = intel_hdmi_encoder_shutdown; 615 616 intel_encoder->type = INTEL_OUTPUT_HDMI; 617 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 618 intel_encoder->port = port; 619 if (IS_CHERRYVIEW(dev_priv)) { 620 if (port == PORT_D) 621 intel_encoder->pipe_mask = BIT(PIPE_C); 622 else 623 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 624 } else { 625 intel_encoder->pipe_mask = ~0; 626 } 627 intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG); 628 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 629 /* 630 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 631 * to work on real hardware. And since g4x can send infoframes to 632 * only one port anyway, nothing is lost by allowing it. 633 */ 634 if (IS_G4X(dev_priv)) 635 intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI); 636 637 dig_port->hdmi.hdmi_reg = hdmi_reg; 638 dig_port->dp.output_reg = INVALID_MMIO_REG; 639 dig_port->max_lanes = 4; 640 641 intel_infoframe_init(dig_port); 642 643 dig_port->aux_ch = intel_dp_aux_ch(intel_encoder); 644 intel_hdmi_init_connector(dig_port, intel_connector); 645 } 646