1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 * DisplayPort support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code). 6 */ 7 8 #include <linux/string_helpers.h> 9 10 #include "g4x_dp.h" 11 #include "i915_reg.h" 12 #include "intel_audio.h" 13 #include "intel_backlight.h" 14 #include "intel_connector.h" 15 #include "intel_crtc.h" 16 #include "intel_de.h" 17 #include "intel_display_power.h" 18 #include "intel_display_types.h" 19 #include "intel_dp.h" 20 #include "intel_dp_link_training.h" 21 #include "intel_dpio_phy.h" 22 #include "intel_fifo_underrun.h" 23 #include "intel_hdmi.h" 24 #include "intel_hotplug.h" 25 #include "intel_pch_display.h" 26 #include "intel_pps.h" 27 #include "vlv_sideband.h" 28 29 static const struct dpll g4x_dpll[] = { 30 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, }, 31 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, }, 32 }; 33 34 static const struct dpll pch_dpll[] = { 35 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, }, 36 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, }, 37 }; 38 39 static const struct dpll vlv_dpll[] = { 40 { .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, }, 41 { .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, }, 42 }; 43 44 static const struct dpll chv_dpll[] = { 45 /* m2 is .22 binary fixed point */ 46 { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ }, 47 { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ }, 48 }; 49 50 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) 51 { 52 return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0]; 53 } 54 55 void g4x_dp_set_clock(struct intel_encoder *encoder, 56 struct intel_crtc_state *pipe_config) 57 { 58 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 59 const struct dpll *divisor = NULL; 60 int i, count = 0; 61 62 if (IS_G4X(dev_priv)) { 63 divisor = g4x_dpll; 64 count = ARRAY_SIZE(g4x_dpll); 65 } else if (HAS_PCH_SPLIT(dev_priv)) { 66 divisor = pch_dpll; 67 count = ARRAY_SIZE(pch_dpll); 68 } else if (IS_CHERRYVIEW(dev_priv)) { 69 divisor = chv_dpll; 70 count = ARRAY_SIZE(chv_dpll); 71 } else if (IS_VALLEYVIEW(dev_priv)) { 72 divisor = vlv_dpll; 73 count = ARRAY_SIZE(vlv_dpll); 74 } 75 76 if (divisor && count) { 77 for (i = 0; i < count; i++) { 78 if (pipe_config->port_clock == divisor[i].dot) { 79 pipe_config->dpll = divisor[i]; 80 pipe_config->clock_set = true; 81 break; 82 } 83 } 84 } 85 } 86 87 static void intel_dp_prepare(struct intel_encoder *encoder, 88 const struct intel_crtc_state *pipe_config) 89 { 90 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 91 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 92 enum port port = encoder->port; 93 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 94 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 95 96 intel_dp_set_link_params(intel_dp, 97 pipe_config->port_clock, 98 pipe_config->lane_count); 99 100 /* 101 * There are four kinds of DP registers: 102 * IBX PCH 103 * SNB CPU 104 * IVB CPU 105 * CPT PCH 106 * 107 * IBX PCH and CPU are the same for almost everything, 108 * except that the CPU DP PLL is configured in this 109 * register 110 * 111 * CPT PCH is quite different, having many bits moved 112 * to the TRANS_DP_CTL register instead. That 113 * configuration happens (oddly) in ilk_pch_enable 114 */ 115 116 /* Preserve the BIOS-computed detected bit. This is 117 * supposed to be read-only. 118 */ 119 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; 120 121 /* Handle DP bits in common between all three register formats */ 122 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 123 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); 124 125 /* Split out the IBX/CPU vs CPT settings */ 126 127 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { 128 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 129 intel_dp->DP |= DP_SYNC_HS_HIGH; 130 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 131 intel_dp->DP |= DP_SYNC_VS_HIGH; 132 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 133 134 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 135 intel_dp->DP |= DP_ENHANCED_FRAMING; 136 137 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe); 138 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { 139 u32 trans_dp; 140 141 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 142 143 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe)); 144 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 145 trans_dp |= TRANS_DP_ENH_FRAMING; 146 else 147 trans_dp &= ~TRANS_DP_ENH_FRAMING; 148 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp); 149 } else { 150 if (IS_G4X(dev_priv) && pipe_config->limited_color_range) 151 intel_dp->DP |= DP_COLOR_RANGE_16_235; 152 153 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 154 intel_dp->DP |= DP_SYNC_HS_HIGH; 155 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 156 intel_dp->DP |= DP_SYNC_VS_HIGH; 157 intel_dp->DP |= DP_LINK_TRAIN_OFF; 158 159 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 160 intel_dp->DP |= DP_ENHANCED_FRAMING; 161 162 if (IS_CHERRYVIEW(dev_priv)) 163 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe); 164 else 165 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe); 166 } 167 } 168 169 static void assert_dp_port(struct intel_dp *intel_dp, bool state) 170 { 171 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 172 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 173 bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN; 174 175 I915_STATE_WARN(cur_state != state, 176 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n", 177 dig_port->base.base.base.id, dig_port->base.base.name, 178 str_on_off(state), str_on_off(cur_state)); 179 } 180 #define assert_dp_port_disabled(d) assert_dp_port((d), false) 181 182 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) 183 { 184 bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE; 185 186 I915_STATE_WARN(cur_state != state, 187 "eDP PLL state assertion failure (expected %s, current %s)\n", 188 str_on_off(state), str_on_off(cur_state)); 189 } 190 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) 191 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) 192 193 static void ilk_edp_pll_on(struct intel_dp *intel_dp, 194 const struct intel_crtc_state *pipe_config) 195 { 196 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 197 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 198 199 assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder); 200 assert_dp_port_disabled(intel_dp); 201 assert_edp_pll_disabled(dev_priv); 202 203 drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n", 204 pipe_config->port_clock); 205 206 intel_dp->DP &= ~DP_PLL_FREQ_MASK; 207 208 if (pipe_config->port_clock == 162000) 209 intel_dp->DP |= DP_PLL_FREQ_162MHZ; 210 else 211 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 212 213 intel_de_write(dev_priv, DP_A, intel_dp->DP); 214 intel_de_posting_read(dev_priv, DP_A); 215 udelay(500); 216 217 /* 218 * [DevILK] Work around required when enabling DP PLL 219 * while a pipe is enabled going to FDI: 220 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI 221 * 2. Program DP PLL enable 222 */ 223 if (IS_IRONLAKE(dev_priv)) 224 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); 225 226 intel_dp->DP |= DP_PLL_ENABLE; 227 228 intel_de_write(dev_priv, DP_A, intel_dp->DP); 229 intel_de_posting_read(dev_priv, DP_A); 230 udelay(200); 231 } 232 233 static void ilk_edp_pll_off(struct intel_dp *intel_dp, 234 const struct intel_crtc_state *old_crtc_state) 235 { 236 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 237 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 238 239 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 240 assert_dp_port_disabled(intel_dp); 241 assert_edp_pll_enabled(dev_priv); 242 243 drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n"); 244 245 intel_dp->DP &= ~DP_PLL_ENABLE; 246 247 intel_de_write(dev_priv, DP_A, intel_dp->DP); 248 intel_de_posting_read(dev_priv, DP_A); 249 udelay(200); 250 } 251 252 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv, 253 enum port port, enum pipe *pipe) 254 { 255 enum pipe p; 256 257 for_each_pipe(dev_priv, p) { 258 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p)); 259 260 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) { 261 *pipe = p; 262 return true; 263 } 264 } 265 266 drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n", 267 port_name(port)); 268 269 /* must initialize pipe to something for the asserts */ 270 *pipe = PIPE_A; 271 272 return false; 273 } 274 275 bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv, 276 i915_reg_t dp_reg, enum port port, 277 enum pipe *pipe) 278 { 279 bool ret; 280 u32 val; 281 282 val = intel_de_read(dev_priv, dp_reg); 283 284 ret = val & DP_PORT_EN; 285 286 /* asserts want to know the pipe even if the port is disabled */ 287 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) 288 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB; 289 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) 290 ret &= cpt_dp_port_selected(dev_priv, port, pipe); 291 else if (IS_CHERRYVIEW(dev_priv)) 292 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV; 293 else 294 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT; 295 296 return ret; 297 } 298 299 static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 300 enum pipe *pipe) 301 { 302 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 303 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 304 intel_wakeref_t wakeref; 305 bool ret; 306 307 wakeref = intel_display_power_get_if_enabled(dev_priv, 308 encoder->power_domain); 309 if (!wakeref) 310 return false; 311 312 ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg, 313 encoder->port, pipe); 314 315 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 316 317 return ret; 318 } 319 320 static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state) 321 { 322 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 323 324 if (crtc_state->has_pch_encoder) { 325 intel_pch_transcoder_get_m1_n1(crtc, &crtc_state->dp_m_n); 326 intel_pch_transcoder_get_m2_n2(crtc, &crtc_state->dp_m2_n2); 327 } else { 328 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, 329 &crtc_state->dp_m_n); 330 intel_cpu_transcoder_get_m2_n2(crtc, crtc_state->cpu_transcoder, 331 &crtc_state->dp_m2_n2); 332 } 333 } 334 335 static void intel_dp_get_config(struct intel_encoder *encoder, 336 struct intel_crtc_state *pipe_config) 337 { 338 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 339 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 340 u32 tmp, flags = 0; 341 enum port port = encoder->port; 342 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 343 344 if (encoder->type == INTEL_OUTPUT_EDP) 345 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 346 else 347 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 348 349 tmp = intel_de_read(dev_priv, intel_dp->output_reg); 350 351 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; 352 353 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { 354 u32 trans_dp = intel_de_read(dev_priv, 355 TRANS_DP_CTL(crtc->pipe)); 356 357 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) 358 flags |= DRM_MODE_FLAG_PHSYNC; 359 else 360 flags |= DRM_MODE_FLAG_NHSYNC; 361 362 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) 363 flags |= DRM_MODE_FLAG_PVSYNC; 364 else 365 flags |= DRM_MODE_FLAG_NVSYNC; 366 } else { 367 if (tmp & DP_SYNC_HS_HIGH) 368 flags |= DRM_MODE_FLAG_PHSYNC; 369 else 370 flags |= DRM_MODE_FLAG_NHSYNC; 371 372 if (tmp & DP_SYNC_VS_HIGH) 373 flags |= DRM_MODE_FLAG_PVSYNC; 374 else 375 flags |= DRM_MODE_FLAG_NVSYNC; 376 } 377 378 pipe_config->hw.adjusted_mode.flags |= flags; 379 380 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) 381 pipe_config->limited_color_range = true; 382 383 pipe_config->lane_count = 384 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; 385 386 g4x_dp_get_m_n(pipe_config); 387 388 if (port == PORT_A) { 389 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) 390 pipe_config->port_clock = 162000; 391 else 392 pipe_config->port_clock = 270000; 393 } 394 395 pipe_config->hw.adjusted_mode.crtc_clock = 396 intel_dotclock_calculate(pipe_config->port_clock, 397 &pipe_config->dp_m_n); 398 399 if (intel_dp_is_edp(intel_dp)) 400 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 401 402 intel_audio_codec_get_config(encoder, pipe_config); 403 } 404 405 static void 406 intel_dp_link_down(struct intel_encoder *encoder, 407 const struct intel_crtc_state *old_crtc_state) 408 { 409 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 410 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 411 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 412 enum port port = encoder->port; 413 414 if (drm_WARN_ON(&dev_priv->drm, 415 (intel_de_read(dev_priv, intel_dp->output_reg) & 416 DP_PORT_EN) == 0)) 417 return; 418 419 drm_dbg_kms(&dev_priv->drm, "\n"); 420 421 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || 422 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { 423 intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT; 424 intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; 425 } else { 426 intel_dp->DP &= ~DP_LINK_TRAIN_MASK; 427 intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE; 428 } 429 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 430 intel_de_posting_read(dev_priv, intel_dp->output_reg); 431 432 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 433 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 434 intel_de_posting_read(dev_priv, intel_dp->output_reg); 435 436 /* 437 * HW workaround for IBX, we need to move the port 438 * to transcoder A after disabling it to allow the 439 * matching HDMI port to be enabled on transcoder A. 440 */ 441 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { 442 /* 443 * We get CPU/PCH FIFO underruns on the other pipe when 444 * doing the workaround. Sweep them under the rug. 445 */ 446 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 447 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 448 449 /* always enable with pattern 1 (as per spec) */ 450 intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK); 451 intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | 452 DP_LINK_TRAIN_PAT_1; 453 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 454 intel_de_posting_read(dev_priv, intel_dp->output_reg); 455 456 intel_dp->DP &= ~DP_PORT_EN; 457 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 458 intel_de_posting_read(dev_priv, intel_dp->output_reg); 459 460 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 461 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 462 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 463 } 464 465 msleep(intel_dp->pps.panel_power_down_delay); 466 467 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 468 intel_wakeref_t wakeref; 469 470 with_intel_pps_lock(intel_dp, wakeref) 471 intel_dp->pps.active_pipe = INVALID_PIPE; 472 } 473 } 474 475 static void intel_disable_dp(struct intel_atomic_state *state, 476 struct intel_encoder *encoder, 477 const struct intel_crtc_state *old_crtc_state, 478 const struct drm_connector_state *old_conn_state) 479 { 480 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 481 482 intel_dp->link_trained = false; 483 484 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 485 486 /* 487 * Make sure the panel is off before trying to change the mode. 488 * But also ensure that we have vdd while we switch off the panel. 489 */ 490 intel_pps_vdd_on(intel_dp); 491 intel_edp_backlight_off(old_conn_state); 492 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 493 intel_pps_off(intel_dp); 494 } 495 496 static void g4x_disable_dp(struct intel_atomic_state *state, 497 struct intel_encoder *encoder, 498 const struct intel_crtc_state *old_crtc_state, 499 const struct drm_connector_state *old_conn_state) 500 { 501 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); 502 } 503 504 static void vlv_disable_dp(struct intel_atomic_state *state, 505 struct intel_encoder *encoder, 506 const struct intel_crtc_state *old_crtc_state, 507 const struct drm_connector_state *old_conn_state) 508 { 509 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); 510 } 511 512 static void g4x_post_disable_dp(struct intel_atomic_state *state, 513 struct intel_encoder *encoder, 514 const struct intel_crtc_state *old_crtc_state, 515 const struct drm_connector_state *old_conn_state) 516 { 517 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 518 enum port port = encoder->port; 519 520 /* 521 * Bspec does not list a specific disable sequence for g4x DP. 522 * Follow the ilk+ sequence (disable pipe before the port) for 523 * g4x DP as it does not suffer from underruns like the normal 524 * g4x modeset sequence (disable pipe after the port). 525 */ 526 intel_dp_link_down(encoder, old_crtc_state); 527 528 /* Only ilk+ has port A */ 529 if (port == PORT_A) 530 ilk_edp_pll_off(intel_dp, old_crtc_state); 531 } 532 533 static void vlv_post_disable_dp(struct intel_atomic_state *state, 534 struct intel_encoder *encoder, 535 const struct intel_crtc_state *old_crtc_state, 536 const struct drm_connector_state *old_conn_state) 537 { 538 intel_dp_link_down(encoder, old_crtc_state); 539 } 540 541 static void chv_post_disable_dp(struct intel_atomic_state *state, 542 struct intel_encoder *encoder, 543 const struct intel_crtc_state *old_crtc_state, 544 const struct drm_connector_state *old_conn_state) 545 { 546 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 547 548 intel_dp_link_down(encoder, old_crtc_state); 549 550 vlv_dpio_get(dev_priv); 551 552 /* Assert data lane reset */ 553 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 554 555 vlv_dpio_put(dev_priv); 556 } 557 558 static void 559 cpt_set_link_train(struct intel_dp *intel_dp, 560 const struct intel_crtc_state *crtc_state, 561 u8 dp_train_pat) 562 { 563 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 564 565 intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT; 566 567 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 568 case DP_TRAINING_PATTERN_DISABLE: 569 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 570 break; 571 case DP_TRAINING_PATTERN_1: 572 intel_dp->DP |= DP_LINK_TRAIN_PAT_1_CPT; 573 break; 574 case DP_TRAINING_PATTERN_2: 575 intel_dp->DP |= DP_LINK_TRAIN_PAT_2_CPT; 576 break; 577 default: 578 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat)); 579 return; 580 } 581 582 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 583 intel_de_posting_read(dev_priv, intel_dp->output_reg); 584 } 585 586 static void 587 g4x_set_link_train(struct intel_dp *intel_dp, 588 const struct intel_crtc_state *crtc_state, 589 u8 dp_train_pat) 590 { 591 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 592 593 intel_dp->DP &= ~DP_LINK_TRAIN_MASK; 594 595 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 596 case DP_TRAINING_PATTERN_DISABLE: 597 intel_dp->DP |= DP_LINK_TRAIN_OFF; 598 break; 599 case DP_TRAINING_PATTERN_1: 600 intel_dp->DP |= DP_LINK_TRAIN_PAT_1; 601 break; 602 case DP_TRAINING_PATTERN_2: 603 intel_dp->DP |= DP_LINK_TRAIN_PAT_2; 604 break; 605 default: 606 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat)); 607 return; 608 } 609 610 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 611 intel_de_posting_read(dev_priv, intel_dp->output_reg); 612 } 613 614 static void intel_dp_enable_port(struct intel_dp *intel_dp, 615 const struct intel_crtc_state *crtc_state) 616 { 617 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 618 619 /* enable with pattern 1 (as per spec) */ 620 621 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 622 DP_PHY_DPRX, DP_TRAINING_PATTERN_1); 623 624 /* 625 * Magic for VLV/CHV. We _must_ first set up the register 626 * without actually enabling the port, and then do another 627 * write to enable the port. Otherwise link training will 628 * fail when the power sequencer is freshly used for this port. 629 */ 630 intel_dp->DP |= DP_PORT_EN; 631 if (crtc_state->has_audio) 632 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 633 634 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 635 intel_de_posting_read(dev_priv, intel_dp->output_reg); 636 } 637 638 static void intel_enable_dp(struct intel_atomic_state *state, 639 struct intel_encoder *encoder, 640 const struct intel_crtc_state *pipe_config, 641 const struct drm_connector_state *conn_state) 642 { 643 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 644 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 645 u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg); 646 intel_wakeref_t wakeref; 647 648 if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN)) 649 return; 650 651 with_intel_pps_lock(intel_dp, wakeref) { 652 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 653 vlv_pps_init(encoder, pipe_config); 654 655 intel_dp_enable_port(intel_dp, pipe_config); 656 657 intel_pps_vdd_on_unlocked(intel_dp); 658 intel_pps_on_unlocked(intel_dp); 659 intel_pps_vdd_off_unlocked(intel_dp, true); 660 } 661 662 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 663 unsigned int lane_mask = 0x0; 664 665 if (IS_CHERRYVIEW(dev_priv)) 666 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); 667 668 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), 669 lane_mask); 670 } 671 672 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 673 intel_dp_configure_protocol_converter(intel_dp, pipe_config); 674 intel_dp_check_frl_training(intel_dp); 675 intel_dp_pcon_dsc_configure(intel_dp, pipe_config); 676 intel_dp_start_link_train(intel_dp, pipe_config); 677 intel_dp_stop_link_train(intel_dp, pipe_config); 678 } 679 680 static void g4x_enable_dp(struct intel_atomic_state *state, 681 struct intel_encoder *encoder, 682 const struct intel_crtc_state *pipe_config, 683 const struct drm_connector_state *conn_state) 684 { 685 intel_enable_dp(state, encoder, pipe_config, conn_state); 686 intel_audio_codec_enable(encoder, pipe_config, conn_state); 687 intel_edp_backlight_on(pipe_config, conn_state); 688 } 689 690 static void vlv_enable_dp(struct intel_atomic_state *state, 691 struct intel_encoder *encoder, 692 const struct intel_crtc_state *pipe_config, 693 const struct drm_connector_state *conn_state) 694 { 695 intel_audio_codec_enable(encoder, pipe_config, conn_state); 696 intel_edp_backlight_on(pipe_config, conn_state); 697 } 698 699 static void g4x_pre_enable_dp(struct intel_atomic_state *state, 700 struct intel_encoder *encoder, 701 const struct intel_crtc_state *pipe_config, 702 const struct drm_connector_state *conn_state) 703 { 704 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 705 enum port port = encoder->port; 706 707 intel_dp_prepare(encoder, pipe_config); 708 709 /* Only ilk+ has port A */ 710 if (port == PORT_A) 711 ilk_edp_pll_on(intel_dp, pipe_config); 712 } 713 714 static void vlv_pre_enable_dp(struct intel_atomic_state *state, 715 struct intel_encoder *encoder, 716 const struct intel_crtc_state *pipe_config, 717 const struct drm_connector_state *conn_state) 718 { 719 vlv_phy_pre_encoder_enable(encoder, pipe_config); 720 721 intel_enable_dp(state, encoder, pipe_config, conn_state); 722 } 723 724 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state, 725 struct intel_encoder *encoder, 726 const struct intel_crtc_state *pipe_config, 727 const struct drm_connector_state *conn_state) 728 { 729 intel_dp_prepare(encoder, pipe_config); 730 731 vlv_phy_pre_pll_enable(encoder, pipe_config); 732 } 733 734 static void chv_pre_enable_dp(struct intel_atomic_state *state, 735 struct intel_encoder *encoder, 736 const struct intel_crtc_state *pipe_config, 737 const struct drm_connector_state *conn_state) 738 { 739 chv_phy_pre_encoder_enable(encoder, pipe_config); 740 741 intel_enable_dp(state, encoder, pipe_config, conn_state); 742 743 /* Second common lane will stay alive on its own now */ 744 chv_phy_release_cl2_override(encoder); 745 } 746 747 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state, 748 struct intel_encoder *encoder, 749 const struct intel_crtc_state *pipe_config, 750 const struct drm_connector_state *conn_state) 751 { 752 intel_dp_prepare(encoder, pipe_config); 753 754 chv_phy_pre_pll_enable(encoder, pipe_config); 755 } 756 757 static void chv_dp_post_pll_disable(struct intel_atomic_state *state, 758 struct intel_encoder *encoder, 759 const struct intel_crtc_state *old_crtc_state, 760 const struct drm_connector_state *old_conn_state) 761 { 762 chv_phy_post_pll_disable(encoder, old_crtc_state); 763 } 764 765 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp, 766 const struct intel_crtc_state *crtc_state) 767 { 768 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 769 } 770 771 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp, 772 const struct intel_crtc_state *crtc_state) 773 { 774 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 775 } 776 777 static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp) 778 { 779 return DP_TRAIN_PRE_EMPH_LEVEL_2; 780 } 781 782 static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp) 783 { 784 return DP_TRAIN_PRE_EMPH_LEVEL_3; 785 } 786 787 static void vlv_set_signal_levels(struct intel_encoder *encoder, 788 const struct intel_crtc_state *crtc_state) 789 { 790 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 791 unsigned long demph_reg_value, preemph_reg_value, 792 uniqtranscale_reg_value; 793 u8 train_set = intel_dp->train_set[0]; 794 795 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 796 case DP_TRAIN_PRE_EMPH_LEVEL_0: 797 preemph_reg_value = 0x0004000; 798 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 799 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 800 demph_reg_value = 0x2B405555; 801 uniqtranscale_reg_value = 0x552AB83A; 802 break; 803 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 804 demph_reg_value = 0x2B404040; 805 uniqtranscale_reg_value = 0x5548B83A; 806 break; 807 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 808 demph_reg_value = 0x2B245555; 809 uniqtranscale_reg_value = 0x5560B83A; 810 break; 811 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 812 demph_reg_value = 0x2B405555; 813 uniqtranscale_reg_value = 0x5598DA3A; 814 break; 815 default: 816 return; 817 } 818 break; 819 case DP_TRAIN_PRE_EMPH_LEVEL_1: 820 preemph_reg_value = 0x0002000; 821 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 822 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 823 demph_reg_value = 0x2B404040; 824 uniqtranscale_reg_value = 0x5552B83A; 825 break; 826 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 827 demph_reg_value = 0x2B404848; 828 uniqtranscale_reg_value = 0x5580B83A; 829 break; 830 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 831 demph_reg_value = 0x2B404040; 832 uniqtranscale_reg_value = 0x55ADDA3A; 833 break; 834 default: 835 return; 836 } 837 break; 838 case DP_TRAIN_PRE_EMPH_LEVEL_2: 839 preemph_reg_value = 0x0000000; 840 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 841 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 842 demph_reg_value = 0x2B305555; 843 uniqtranscale_reg_value = 0x5570B83A; 844 break; 845 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 846 demph_reg_value = 0x2B2B4040; 847 uniqtranscale_reg_value = 0x55ADDA3A; 848 break; 849 default: 850 return; 851 } 852 break; 853 case DP_TRAIN_PRE_EMPH_LEVEL_3: 854 preemph_reg_value = 0x0006000; 855 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 856 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 857 demph_reg_value = 0x1B405555; 858 uniqtranscale_reg_value = 0x55ADDA3A; 859 break; 860 default: 861 return; 862 } 863 break; 864 default: 865 return; 866 } 867 868 vlv_set_phy_signal_level(encoder, crtc_state, 869 demph_reg_value, preemph_reg_value, 870 uniqtranscale_reg_value, 0); 871 } 872 873 static void chv_set_signal_levels(struct intel_encoder *encoder, 874 const struct intel_crtc_state *crtc_state) 875 { 876 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 877 u32 deemph_reg_value, margin_reg_value; 878 bool uniq_trans_scale = false; 879 u8 train_set = intel_dp->train_set[0]; 880 881 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 882 case DP_TRAIN_PRE_EMPH_LEVEL_0: 883 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 884 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 885 deemph_reg_value = 128; 886 margin_reg_value = 52; 887 break; 888 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 889 deemph_reg_value = 128; 890 margin_reg_value = 77; 891 break; 892 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 893 deemph_reg_value = 128; 894 margin_reg_value = 102; 895 break; 896 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 897 deemph_reg_value = 128; 898 margin_reg_value = 154; 899 uniq_trans_scale = true; 900 break; 901 default: 902 return; 903 } 904 break; 905 case DP_TRAIN_PRE_EMPH_LEVEL_1: 906 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 907 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 908 deemph_reg_value = 85; 909 margin_reg_value = 78; 910 break; 911 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 912 deemph_reg_value = 85; 913 margin_reg_value = 116; 914 break; 915 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 916 deemph_reg_value = 85; 917 margin_reg_value = 154; 918 break; 919 default: 920 return; 921 } 922 break; 923 case DP_TRAIN_PRE_EMPH_LEVEL_2: 924 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 925 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 926 deemph_reg_value = 64; 927 margin_reg_value = 104; 928 break; 929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 930 deemph_reg_value = 64; 931 margin_reg_value = 154; 932 break; 933 default: 934 return; 935 } 936 break; 937 case DP_TRAIN_PRE_EMPH_LEVEL_3: 938 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 940 deemph_reg_value = 43; 941 margin_reg_value = 154; 942 break; 943 default: 944 return; 945 } 946 break; 947 default: 948 return; 949 } 950 951 chv_set_phy_signal_level(encoder, crtc_state, 952 deemph_reg_value, margin_reg_value, 953 uniq_trans_scale); 954 } 955 956 static u32 g4x_signal_levels(u8 train_set) 957 { 958 u32 signal_levels = 0; 959 960 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 961 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 962 default: 963 signal_levels |= DP_VOLTAGE_0_4; 964 break; 965 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 966 signal_levels |= DP_VOLTAGE_0_6; 967 break; 968 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 969 signal_levels |= DP_VOLTAGE_0_8; 970 break; 971 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 972 signal_levels |= DP_VOLTAGE_1_2; 973 break; 974 } 975 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 976 case DP_TRAIN_PRE_EMPH_LEVEL_0: 977 default: 978 signal_levels |= DP_PRE_EMPHASIS_0; 979 break; 980 case DP_TRAIN_PRE_EMPH_LEVEL_1: 981 signal_levels |= DP_PRE_EMPHASIS_3_5; 982 break; 983 case DP_TRAIN_PRE_EMPH_LEVEL_2: 984 signal_levels |= DP_PRE_EMPHASIS_6; 985 break; 986 case DP_TRAIN_PRE_EMPH_LEVEL_3: 987 signal_levels |= DP_PRE_EMPHASIS_9_5; 988 break; 989 } 990 return signal_levels; 991 } 992 993 static void 994 g4x_set_signal_levels(struct intel_encoder *encoder, 995 const struct intel_crtc_state *crtc_state) 996 { 997 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 998 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 999 u8 train_set = intel_dp->train_set[0]; 1000 u32 signal_levels; 1001 1002 signal_levels = g4x_signal_levels(train_set); 1003 1004 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1005 signal_levels); 1006 1007 intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK); 1008 intel_dp->DP |= signal_levels; 1009 1010 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 1011 intel_de_posting_read(dev_priv, intel_dp->output_reg); 1012 } 1013 1014 /* SNB CPU eDP voltage swing and pre-emphasis control */ 1015 static u32 snb_cpu_edp_signal_levels(u8 train_set) 1016 { 1017 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1018 DP_TRAIN_PRE_EMPHASIS_MASK); 1019 1020 switch (signal_levels) { 1021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1023 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1024 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1025 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 1026 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1028 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 1029 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1030 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1031 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 1032 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1034 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 1035 default: 1036 MISSING_CASE(signal_levels); 1037 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1038 } 1039 } 1040 1041 static void 1042 snb_cpu_edp_set_signal_levels(struct intel_encoder *encoder, 1043 const struct intel_crtc_state *crtc_state) 1044 { 1045 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1046 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1047 u8 train_set = intel_dp->train_set[0]; 1048 u32 signal_levels; 1049 1050 signal_levels = snb_cpu_edp_signal_levels(train_set); 1051 1052 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1053 signal_levels); 1054 1055 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 1056 intel_dp->DP |= signal_levels; 1057 1058 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 1059 intel_de_posting_read(dev_priv, intel_dp->output_reg); 1060 } 1061 1062 /* IVB CPU eDP voltage swing and pre-emphasis control */ 1063 static u32 ivb_cpu_edp_signal_levels(u8 train_set) 1064 { 1065 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1066 DP_TRAIN_PRE_EMPHASIS_MASK); 1067 1068 switch (signal_levels) { 1069 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1070 return EDP_LINK_TRAIN_400MV_0DB_IVB; 1071 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1072 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 1073 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1074 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1075 return EDP_LINK_TRAIN_400MV_6DB_IVB; 1076 1077 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1078 return EDP_LINK_TRAIN_600MV_0DB_IVB; 1079 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1080 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 1081 1082 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1083 return EDP_LINK_TRAIN_800MV_0DB_IVB; 1084 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1085 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 1086 1087 default: 1088 MISSING_CASE(signal_levels); 1089 return EDP_LINK_TRAIN_500MV_0DB_IVB; 1090 } 1091 } 1092 1093 static void 1094 ivb_cpu_edp_set_signal_levels(struct intel_encoder *encoder, 1095 const struct intel_crtc_state *crtc_state) 1096 { 1097 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1098 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1099 u8 train_set = intel_dp->train_set[0]; 1100 u32 signal_levels; 1101 1102 signal_levels = ivb_cpu_edp_signal_levels(train_set); 1103 1104 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1105 signal_levels); 1106 1107 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 1108 intel_dp->DP |= signal_levels; 1109 1110 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 1111 intel_de_posting_read(dev_priv, intel_dp->output_reg); 1112 } 1113 1114 /* 1115 * If display is now connected check links status, 1116 * there has been known issues of link loss triggering 1117 * long pulse. 1118 * 1119 * Some sinks (eg. ASUS PB287Q) seem to perform some 1120 * weird HPD ping pong during modesets. So we can apparently 1121 * end up with HPD going low during a modeset, and then 1122 * going back up soon after. And once that happens we must 1123 * retrain the link to get a picture. That's in case no 1124 * userspace component reacted to intermittent HPD dip. 1125 */ 1126 static enum intel_hotplug_state 1127 intel_dp_hotplug(struct intel_encoder *encoder, 1128 struct intel_connector *connector) 1129 { 1130 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1131 struct drm_modeset_acquire_ctx ctx; 1132 enum intel_hotplug_state state; 1133 int ret; 1134 1135 if (intel_dp->compliance.test_active && 1136 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 1137 intel_dp_phy_test(encoder); 1138 /* just do the PHY test and nothing else */ 1139 return INTEL_HOTPLUG_UNCHANGED; 1140 } 1141 1142 state = intel_encoder_hotplug(encoder, connector); 1143 1144 drm_modeset_acquire_init(&ctx, 0); 1145 1146 for (;;) { 1147 ret = intel_dp_retrain_link(encoder, &ctx); 1148 1149 if (ret == -EDEADLK) { 1150 drm_modeset_backoff(&ctx); 1151 continue; 1152 } 1153 1154 break; 1155 } 1156 1157 drm_modeset_drop_locks(&ctx); 1158 drm_modeset_acquire_fini(&ctx); 1159 drm_WARN(encoder->base.dev, ret, 1160 "Acquiring modeset locks failed with %i\n", ret); 1161 1162 /* 1163 * Keeping it consistent with intel_ddi_hotplug() and 1164 * intel_hdmi_hotplug(). 1165 */ 1166 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 1167 state = INTEL_HOTPLUG_RETRY; 1168 1169 return state; 1170 } 1171 1172 static bool ibx_digital_port_connected(struct intel_encoder *encoder) 1173 { 1174 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1175 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 1176 1177 return intel_de_read(dev_priv, SDEISR) & bit; 1178 } 1179 1180 static bool g4x_digital_port_connected(struct intel_encoder *encoder) 1181 { 1182 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1183 u32 bit; 1184 1185 switch (encoder->hpd_pin) { 1186 case HPD_PORT_B: 1187 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 1188 break; 1189 case HPD_PORT_C: 1190 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 1191 break; 1192 case HPD_PORT_D: 1193 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 1194 break; 1195 default: 1196 MISSING_CASE(encoder->hpd_pin); 1197 return false; 1198 } 1199 1200 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; 1201 } 1202 1203 static bool gm45_digital_port_connected(struct intel_encoder *encoder) 1204 { 1205 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1206 u32 bit; 1207 1208 switch (encoder->hpd_pin) { 1209 case HPD_PORT_B: 1210 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; 1211 break; 1212 case HPD_PORT_C: 1213 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; 1214 break; 1215 case HPD_PORT_D: 1216 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; 1217 break; 1218 default: 1219 MISSING_CASE(encoder->hpd_pin); 1220 return false; 1221 } 1222 1223 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; 1224 } 1225 1226 static bool ilk_digital_port_connected(struct intel_encoder *encoder) 1227 { 1228 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1229 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 1230 1231 return intel_de_read(dev_priv, DEISR) & bit; 1232 } 1233 1234 static void intel_dp_encoder_destroy(struct drm_encoder *encoder) 1235 { 1236 intel_dp_encoder_flush_work(encoder); 1237 1238 drm_encoder_cleanup(encoder); 1239 kfree(enc_to_dig_port(to_intel_encoder(encoder))); 1240 } 1241 1242 enum pipe vlv_active_pipe(struct intel_dp *intel_dp) 1243 { 1244 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1245 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1246 enum pipe pipe; 1247 1248 if (g4x_dp_port_enabled(dev_priv, intel_dp->output_reg, 1249 encoder->port, &pipe)) 1250 return pipe; 1251 1252 return INVALID_PIPE; 1253 } 1254 1255 static void intel_dp_encoder_reset(struct drm_encoder *encoder) 1256 { 1257 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 1258 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 1259 1260 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); 1261 1262 intel_dp->reset_link_params = true; 1263 1264 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1265 intel_wakeref_t wakeref; 1266 1267 with_intel_pps_lock(intel_dp, wakeref) 1268 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp); 1269 } 1270 1271 intel_pps_encoder_reset(intel_dp); 1272 } 1273 1274 static const struct drm_encoder_funcs intel_dp_enc_funcs = { 1275 .reset = intel_dp_encoder_reset, 1276 .destroy = intel_dp_encoder_destroy, 1277 }; 1278 1279 bool g4x_dp_init(struct drm_i915_private *dev_priv, 1280 i915_reg_t output_reg, enum port port) 1281 { 1282 struct intel_digital_port *dig_port; 1283 struct intel_encoder *intel_encoder; 1284 struct drm_encoder *encoder; 1285 struct intel_connector *intel_connector; 1286 1287 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 1288 if (!dig_port) 1289 return false; 1290 1291 intel_connector = intel_connector_alloc(); 1292 if (!intel_connector) 1293 goto err_connector_alloc; 1294 1295 intel_encoder = &dig_port->base; 1296 encoder = &intel_encoder->base; 1297 1298 mutex_init(&dig_port->hdcp_mutex); 1299 1300 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 1301 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, 1302 "DP %c", port_name(port))) 1303 goto err_encoder_init; 1304 1305 intel_encoder->hotplug = intel_dp_hotplug; 1306 intel_encoder->compute_config = intel_dp_compute_config; 1307 intel_encoder->get_hw_state = intel_dp_get_hw_state; 1308 intel_encoder->get_config = intel_dp_get_config; 1309 intel_encoder->sync_state = intel_dp_sync_state; 1310 intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check; 1311 intel_encoder->update_pipe = intel_backlight_update; 1312 intel_encoder->suspend = intel_dp_encoder_suspend; 1313 intel_encoder->shutdown = intel_dp_encoder_shutdown; 1314 if (IS_CHERRYVIEW(dev_priv)) { 1315 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; 1316 intel_encoder->pre_enable = chv_pre_enable_dp; 1317 intel_encoder->enable = vlv_enable_dp; 1318 intel_encoder->disable = vlv_disable_dp; 1319 intel_encoder->post_disable = chv_post_disable_dp; 1320 intel_encoder->post_pll_disable = chv_dp_post_pll_disable; 1321 } else if (IS_VALLEYVIEW(dev_priv)) { 1322 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 1323 intel_encoder->pre_enable = vlv_pre_enable_dp; 1324 intel_encoder->enable = vlv_enable_dp; 1325 intel_encoder->disable = vlv_disable_dp; 1326 intel_encoder->post_disable = vlv_post_disable_dp; 1327 } else { 1328 intel_encoder->pre_enable = g4x_pre_enable_dp; 1329 intel_encoder->enable = g4x_enable_dp; 1330 intel_encoder->disable = g4x_disable_dp; 1331 intel_encoder->post_disable = g4x_post_disable_dp; 1332 } 1333 1334 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || 1335 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) 1336 dig_port->dp.set_link_train = cpt_set_link_train; 1337 else 1338 dig_port->dp.set_link_train = g4x_set_link_train; 1339 1340 if (IS_CHERRYVIEW(dev_priv)) 1341 intel_encoder->set_signal_levels = chv_set_signal_levels; 1342 else if (IS_VALLEYVIEW(dev_priv)) 1343 intel_encoder->set_signal_levels = vlv_set_signal_levels; 1344 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) 1345 intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels; 1346 else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A) 1347 intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels; 1348 else 1349 intel_encoder->set_signal_levels = g4x_set_signal_levels; 1350 1351 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || 1352 (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) { 1353 dig_port->dp.preemph_max = intel_dp_preemph_max_3; 1354 dig_port->dp.voltage_max = intel_dp_voltage_max_3; 1355 } else { 1356 dig_port->dp.preemph_max = intel_dp_preemph_max_2; 1357 dig_port->dp.voltage_max = intel_dp_voltage_max_2; 1358 } 1359 1360 dig_port->dp.output_reg = output_reg; 1361 dig_port->max_lanes = 4; 1362 1363 intel_encoder->type = INTEL_OUTPUT_DP; 1364 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 1365 if (IS_CHERRYVIEW(dev_priv)) { 1366 if (port == PORT_D) 1367 intel_encoder->pipe_mask = BIT(PIPE_C); 1368 else 1369 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 1370 } else { 1371 intel_encoder->pipe_mask = ~0; 1372 } 1373 intel_encoder->cloneable = 0; 1374 intel_encoder->port = port; 1375 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 1376 1377 dig_port->hpd_pulse = intel_dp_hpd_pulse; 1378 1379 if (HAS_GMCH(dev_priv)) { 1380 if (IS_GM45(dev_priv)) 1381 dig_port->connected = gm45_digital_port_connected; 1382 else 1383 dig_port->connected = g4x_digital_port_connected; 1384 } else { 1385 if (port == PORT_A) 1386 dig_port->connected = ilk_digital_port_connected; 1387 else 1388 dig_port->connected = ibx_digital_port_connected; 1389 } 1390 1391 if (port != PORT_A) 1392 intel_infoframe_init(dig_port); 1393 1394 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 1395 if (!intel_dp_init_connector(dig_port, intel_connector)) 1396 goto err_init_connector; 1397 1398 return true; 1399 1400 err_init_connector: 1401 drm_encoder_cleanup(encoder); 1402 err_encoder_init: 1403 kfree(intel_connector); 1404 err_connector_alloc: 1405 kfree(dig_port); 1406 return false; 1407 } 1408