1*917c2899SVille Syrjälä // SPDX-License-Identifier: MIT 2*917c2899SVille Syrjälä /* 3*917c2899SVille Syrjälä * Copyright © 2020 Intel Corporation 4*917c2899SVille Syrjälä * 5*917c2899SVille Syrjälä * DisplayPort support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code). 6*917c2899SVille Syrjälä */ 7*917c2899SVille Syrjälä 8*917c2899SVille Syrjälä #include "g4x_dp.h" 9*917c2899SVille Syrjälä #include "intel_audio.h" 10*917c2899SVille Syrjälä #include "intel_connector.h" 11*917c2899SVille Syrjälä #include "intel_display_types.h" 12*917c2899SVille Syrjälä #include "intel_dp.h" 13*917c2899SVille Syrjälä #include "intel_dp_link_training.h" 14*917c2899SVille Syrjälä #include "intel_dpio_phy.h" 15*917c2899SVille Syrjälä #include "intel_fifo_underrun.h" 16*917c2899SVille Syrjälä #include "intel_hdmi.h" 17*917c2899SVille Syrjälä #include "intel_hotplug.h" 18*917c2899SVille Syrjälä #include "intel_panel.h" 19*917c2899SVille Syrjälä #include "intel_pps.h" 20*917c2899SVille Syrjälä #include "intel_sideband.h" 21*917c2899SVille Syrjälä 22*917c2899SVille Syrjälä struct dp_link_dpll { 23*917c2899SVille Syrjälä int clock; 24*917c2899SVille Syrjälä struct dpll dpll; 25*917c2899SVille Syrjälä }; 26*917c2899SVille Syrjälä 27*917c2899SVille Syrjälä static const struct dp_link_dpll g4x_dpll[] = { 28*917c2899SVille Syrjälä { 162000, 29*917c2899SVille Syrjälä { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 30*917c2899SVille Syrjälä { 270000, 31*917c2899SVille Syrjälä { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 32*917c2899SVille Syrjälä }; 33*917c2899SVille Syrjälä 34*917c2899SVille Syrjälä static const struct dp_link_dpll pch_dpll[] = { 35*917c2899SVille Syrjälä { 162000, 36*917c2899SVille Syrjälä { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 37*917c2899SVille Syrjälä { 270000, 38*917c2899SVille Syrjälä { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 39*917c2899SVille Syrjälä }; 40*917c2899SVille Syrjälä 41*917c2899SVille Syrjälä static const struct dp_link_dpll vlv_dpll[] = { 42*917c2899SVille Syrjälä { 162000, 43*917c2899SVille Syrjälä { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 44*917c2899SVille Syrjälä { 270000, 45*917c2899SVille Syrjälä { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 46*917c2899SVille Syrjälä }; 47*917c2899SVille Syrjälä 48*917c2899SVille Syrjälä /* 49*917c2899SVille Syrjälä * CHV supports eDP 1.4 that have more link rates. 50*917c2899SVille Syrjälä * Below only provides the fixed rate but exclude variable rate. 51*917c2899SVille Syrjälä */ 52*917c2899SVille Syrjälä static const struct dp_link_dpll chv_dpll[] = { 53*917c2899SVille Syrjälä /* 54*917c2899SVille Syrjälä * CHV requires to program fractional division for m2. 55*917c2899SVille Syrjälä * m2 is stored in fixed point format using formula below 56*917c2899SVille Syrjälä * (m2_int << 22) | m2_fraction 57*917c2899SVille Syrjälä */ 58*917c2899SVille Syrjälä { 162000, /* m2_int = 32, m2_fraction = 1677722 */ 59*917c2899SVille Syrjälä { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, 60*917c2899SVille Syrjälä { 270000, /* m2_int = 27, m2_fraction = 0 */ 61*917c2899SVille Syrjälä { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, 62*917c2899SVille Syrjälä }; 63*917c2899SVille Syrjälä 64*917c2899SVille Syrjälä const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) 65*917c2899SVille Syrjälä { 66*917c2899SVille Syrjälä return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll; 67*917c2899SVille Syrjälä } 68*917c2899SVille Syrjälä 69*917c2899SVille Syrjälä void intel_dp_set_clock(struct intel_encoder *encoder, 70*917c2899SVille Syrjälä struct intel_crtc_state *pipe_config) 71*917c2899SVille Syrjälä { 72*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 73*917c2899SVille Syrjälä const struct dp_link_dpll *divisor = NULL; 74*917c2899SVille Syrjälä int i, count = 0; 75*917c2899SVille Syrjälä 76*917c2899SVille Syrjälä if (IS_G4X(dev_priv)) { 77*917c2899SVille Syrjälä divisor = g4x_dpll; 78*917c2899SVille Syrjälä count = ARRAY_SIZE(g4x_dpll); 79*917c2899SVille Syrjälä } else if (HAS_PCH_SPLIT(dev_priv)) { 80*917c2899SVille Syrjälä divisor = pch_dpll; 81*917c2899SVille Syrjälä count = ARRAY_SIZE(pch_dpll); 82*917c2899SVille Syrjälä } else if (IS_CHERRYVIEW(dev_priv)) { 83*917c2899SVille Syrjälä divisor = chv_dpll; 84*917c2899SVille Syrjälä count = ARRAY_SIZE(chv_dpll); 85*917c2899SVille Syrjälä } else if (IS_VALLEYVIEW(dev_priv)) { 86*917c2899SVille Syrjälä divisor = vlv_dpll; 87*917c2899SVille Syrjälä count = ARRAY_SIZE(vlv_dpll); 88*917c2899SVille Syrjälä } 89*917c2899SVille Syrjälä 90*917c2899SVille Syrjälä if (divisor && count) { 91*917c2899SVille Syrjälä for (i = 0; i < count; i++) { 92*917c2899SVille Syrjälä if (pipe_config->port_clock == divisor[i].clock) { 93*917c2899SVille Syrjälä pipe_config->dpll = divisor[i].dpll; 94*917c2899SVille Syrjälä pipe_config->clock_set = true; 95*917c2899SVille Syrjälä break; 96*917c2899SVille Syrjälä } 97*917c2899SVille Syrjälä } 98*917c2899SVille Syrjälä } 99*917c2899SVille Syrjälä } 100*917c2899SVille Syrjälä 101*917c2899SVille Syrjälä static void intel_dp_prepare(struct intel_encoder *encoder, 102*917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config) 103*917c2899SVille Syrjälä { 104*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 105*917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 106*917c2899SVille Syrjälä enum port port = encoder->port; 107*917c2899SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 108*917c2899SVille Syrjälä const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 109*917c2899SVille Syrjälä 110*917c2899SVille Syrjälä intel_dp_set_link_params(intel_dp, 111*917c2899SVille Syrjälä pipe_config->port_clock, 112*917c2899SVille Syrjälä pipe_config->lane_count); 113*917c2899SVille Syrjälä 114*917c2899SVille Syrjälä /* 115*917c2899SVille Syrjälä * There are four kinds of DP registers: 116*917c2899SVille Syrjälä * IBX PCH 117*917c2899SVille Syrjälä * SNB CPU 118*917c2899SVille Syrjälä * IVB CPU 119*917c2899SVille Syrjälä * CPT PCH 120*917c2899SVille Syrjälä * 121*917c2899SVille Syrjälä * IBX PCH and CPU are the same for almost everything, 122*917c2899SVille Syrjälä * except that the CPU DP PLL is configured in this 123*917c2899SVille Syrjälä * register 124*917c2899SVille Syrjälä * 125*917c2899SVille Syrjälä * CPT PCH is quite different, having many bits moved 126*917c2899SVille Syrjälä * to the TRANS_DP_CTL register instead. That 127*917c2899SVille Syrjälä * configuration happens (oddly) in ilk_pch_enable 128*917c2899SVille Syrjälä */ 129*917c2899SVille Syrjälä 130*917c2899SVille Syrjälä /* Preserve the BIOS-computed detected bit. This is 131*917c2899SVille Syrjälä * supposed to be read-only. 132*917c2899SVille Syrjälä */ 133*917c2899SVille Syrjälä intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; 134*917c2899SVille Syrjälä 135*917c2899SVille Syrjälä /* Handle DP bits in common between all three register formats */ 136*917c2899SVille Syrjälä intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 137*917c2899SVille Syrjälä intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); 138*917c2899SVille Syrjälä 139*917c2899SVille Syrjälä /* Split out the IBX/CPU vs CPT settings */ 140*917c2899SVille Syrjälä 141*917c2899SVille Syrjälä if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { 142*917c2899SVille Syrjälä if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 143*917c2899SVille Syrjälä intel_dp->DP |= DP_SYNC_HS_HIGH; 144*917c2899SVille Syrjälä if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 145*917c2899SVille Syrjälä intel_dp->DP |= DP_SYNC_VS_HIGH; 146*917c2899SVille Syrjälä intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 147*917c2899SVille Syrjälä 148*917c2899SVille Syrjälä if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 149*917c2899SVille Syrjälä intel_dp->DP |= DP_ENHANCED_FRAMING; 150*917c2899SVille Syrjälä 151*917c2899SVille Syrjälä intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe); 152*917c2899SVille Syrjälä } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { 153*917c2899SVille Syrjälä u32 trans_dp; 154*917c2899SVille Syrjälä 155*917c2899SVille Syrjälä intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 156*917c2899SVille Syrjälä 157*917c2899SVille Syrjälä trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe)); 158*917c2899SVille Syrjälä if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 159*917c2899SVille Syrjälä trans_dp |= TRANS_DP_ENH_FRAMING; 160*917c2899SVille Syrjälä else 161*917c2899SVille Syrjälä trans_dp &= ~TRANS_DP_ENH_FRAMING; 162*917c2899SVille Syrjälä intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp); 163*917c2899SVille Syrjälä } else { 164*917c2899SVille Syrjälä if (IS_G4X(dev_priv) && pipe_config->limited_color_range) 165*917c2899SVille Syrjälä intel_dp->DP |= DP_COLOR_RANGE_16_235; 166*917c2899SVille Syrjälä 167*917c2899SVille Syrjälä if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 168*917c2899SVille Syrjälä intel_dp->DP |= DP_SYNC_HS_HIGH; 169*917c2899SVille Syrjälä if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 170*917c2899SVille Syrjälä intel_dp->DP |= DP_SYNC_VS_HIGH; 171*917c2899SVille Syrjälä intel_dp->DP |= DP_LINK_TRAIN_OFF; 172*917c2899SVille Syrjälä 173*917c2899SVille Syrjälä if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 174*917c2899SVille Syrjälä intel_dp->DP |= DP_ENHANCED_FRAMING; 175*917c2899SVille Syrjälä 176*917c2899SVille Syrjälä if (IS_CHERRYVIEW(dev_priv)) 177*917c2899SVille Syrjälä intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe); 178*917c2899SVille Syrjälä else 179*917c2899SVille Syrjälä intel_dp->DP |= DP_PIPE_SEL(crtc->pipe); 180*917c2899SVille Syrjälä } 181*917c2899SVille Syrjälä } 182*917c2899SVille Syrjälä 183*917c2899SVille Syrjälä static void assert_dp_port(struct intel_dp *intel_dp, bool state) 184*917c2899SVille Syrjälä { 185*917c2899SVille Syrjälä struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 186*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 187*917c2899SVille Syrjälä bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN; 188*917c2899SVille Syrjälä 189*917c2899SVille Syrjälä I915_STATE_WARN(cur_state != state, 190*917c2899SVille Syrjälä "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n", 191*917c2899SVille Syrjälä dig_port->base.base.base.id, dig_port->base.base.name, 192*917c2899SVille Syrjälä onoff(state), onoff(cur_state)); 193*917c2899SVille Syrjälä } 194*917c2899SVille Syrjälä #define assert_dp_port_disabled(d) assert_dp_port((d), false) 195*917c2899SVille Syrjälä 196*917c2899SVille Syrjälä static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) 197*917c2899SVille Syrjälä { 198*917c2899SVille Syrjälä bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE; 199*917c2899SVille Syrjälä 200*917c2899SVille Syrjälä I915_STATE_WARN(cur_state != state, 201*917c2899SVille Syrjälä "eDP PLL state assertion failure (expected %s, current %s)\n", 202*917c2899SVille Syrjälä onoff(state), onoff(cur_state)); 203*917c2899SVille Syrjälä } 204*917c2899SVille Syrjälä #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) 205*917c2899SVille Syrjälä #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) 206*917c2899SVille Syrjälä 207*917c2899SVille Syrjälä static void ilk_edp_pll_on(struct intel_dp *intel_dp, 208*917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config) 209*917c2899SVille Syrjälä { 210*917c2899SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 211*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 212*917c2899SVille Syrjälä 213*917c2899SVille Syrjälä assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); 214*917c2899SVille Syrjälä assert_dp_port_disabled(intel_dp); 215*917c2899SVille Syrjälä assert_edp_pll_disabled(dev_priv); 216*917c2899SVille Syrjälä 217*917c2899SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n", 218*917c2899SVille Syrjälä pipe_config->port_clock); 219*917c2899SVille Syrjälä 220*917c2899SVille Syrjälä intel_dp->DP &= ~DP_PLL_FREQ_MASK; 221*917c2899SVille Syrjälä 222*917c2899SVille Syrjälä if (pipe_config->port_clock == 162000) 223*917c2899SVille Syrjälä intel_dp->DP |= DP_PLL_FREQ_162MHZ; 224*917c2899SVille Syrjälä else 225*917c2899SVille Syrjälä intel_dp->DP |= DP_PLL_FREQ_270MHZ; 226*917c2899SVille Syrjälä 227*917c2899SVille Syrjälä intel_de_write(dev_priv, DP_A, intel_dp->DP); 228*917c2899SVille Syrjälä intel_de_posting_read(dev_priv, DP_A); 229*917c2899SVille Syrjälä udelay(500); 230*917c2899SVille Syrjälä 231*917c2899SVille Syrjälä /* 232*917c2899SVille Syrjälä * [DevILK] Work around required when enabling DP PLL 233*917c2899SVille Syrjälä * while a pipe is enabled going to FDI: 234*917c2899SVille Syrjälä * 1. Wait for the start of vertical blank on the enabled pipe going to FDI 235*917c2899SVille Syrjälä * 2. Program DP PLL enable 236*917c2899SVille Syrjälä */ 237*917c2899SVille Syrjälä if (IS_GEN(dev_priv, 5)) 238*917c2899SVille Syrjälä intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); 239*917c2899SVille Syrjälä 240*917c2899SVille Syrjälä intel_dp->DP |= DP_PLL_ENABLE; 241*917c2899SVille Syrjälä 242*917c2899SVille Syrjälä intel_de_write(dev_priv, DP_A, intel_dp->DP); 243*917c2899SVille Syrjälä intel_de_posting_read(dev_priv, DP_A); 244*917c2899SVille Syrjälä udelay(200); 245*917c2899SVille Syrjälä } 246*917c2899SVille Syrjälä 247*917c2899SVille Syrjälä static void ilk_edp_pll_off(struct intel_dp *intel_dp, 248*917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state) 249*917c2899SVille Syrjälä { 250*917c2899SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 251*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 252*917c2899SVille Syrjälä 253*917c2899SVille Syrjälä assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder); 254*917c2899SVille Syrjälä assert_dp_port_disabled(intel_dp); 255*917c2899SVille Syrjälä assert_edp_pll_enabled(dev_priv); 256*917c2899SVille Syrjälä 257*917c2899SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n"); 258*917c2899SVille Syrjälä 259*917c2899SVille Syrjälä intel_dp->DP &= ~DP_PLL_ENABLE; 260*917c2899SVille Syrjälä 261*917c2899SVille Syrjälä intel_de_write(dev_priv, DP_A, intel_dp->DP); 262*917c2899SVille Syrjälä intel_de_posting_read(dev_priv, DP_A); 263*917c2899SVille Syrjälä udelay(200); 264*917c2899SVille Syrjälä } 265*917c2899SVille Syrjälä 266*917c2899SVille Syrjälä static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv, 267*917c2899SVille Syrjälä enum port port, enum pipe *pipe) 268*917c2899SVille Syrjälä { 269*917c2899SVille Syrjälä enum pipe p; 270*917c2899SVille Syrjälä 271*917c2899SVille Syrjälä for_each_pipe(dev_priv, p) { 272*917c2899SVille Syrjälä u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p)); 273*917c2899SVille Syrjälä 274*917c2899SVille Syrjälä if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) { 275*917c2899SVille Syrjälä *pipe = p; 276*917c2899SVille Syrjälä return true; 277*917c2899SVille Syrjälä } 278*917c2899SVille Syrjälä } 279*917c2899SVille Syrjälä 280*917c2899SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n", 281*917c2899SVille Syrjälä port_name(port)); 282*917c2899SVille Syrjälä 283*917c2899SVille Syrjälä /* must initialize pipe to something for the asserts */ 284*917c2899SVille Syrjälä *pipe = PIPE_A; 285*917c2899SVille Syrjälä 286*917c2899SVille Syrjälä return false; 287*917c2899SVille Syrjälä } 288*917c2899SVille Syrjälä 289*917c2899SVille Syrjälä bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, 290*917c2899SVille Syrjälä i915_reg_t dp_reg, enum port port, 291*917c2899SVille Syrjälä enum pipe *pipe) 292*917c2899SVille Syrjälä { 293*917c2899SVille Syrjälä bool ret; 294*917c2899SVille Syrjälä u32 val; 295*917c2899SVille Syrjälä 296*917c2899SVille Syrjälä val = intel_de_read(dev_priv, dp_reg); 297*917c2899SVille Syrjälä 298*917c2899SVille Syrjälä ret = val & DP_PORT_EN; 299*917c2899SVille Syrjälä 300*917c2899SVille Syrjälä /* asserts want to know the pipe even if the port is disabled */ 301*917c2899SVille Syrjälä if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) 302*917c2899SVille Syrjälä *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB; 303*917c2899SVille Syrjälä else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) 304*917c2899SVille Syrjälä ret &= cpt_dp_port_selected(dev_priv, port, pipe); 305*917c2899SVille Syrjälä else if (IS_CHERRYVIEW(dev_priv)) 306*917c2899SVille Syrjälä *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV; 307*917c2899SVille Syrjälä else 308*917c2899SVille Syrjälä *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT; 309*917c2899SVille Syrjälä 310*917c2899SVille Syrjälä return ret; 311*917c2899SVille Syrjälä } 312*917c2899SVille Syrjälä 313*917c2899SVille Syrjälä static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 314*917c2899SVille Syrjälä enum pipe *pipe) 315*917c2899SVille Syrjälä { 316*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 317*917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 318*917c2899SVille Syrjälä intel_wakeref_t wakeref; 319*917c2899SVille Syrjälä bool ret; 320*917c2899SVille Syrjälä 321*917c2899SVille Syrjälä wakeref = intel_display_power_get_if_enabled(dev_priv, 322*917c2899SVille Syrjälä encoder->power_domain); 323*917c2899SVille Syrjälä if (!wakeref) 324*917c2899SVille Syrjälä return false; 325*917c2899SVille Syrjälä 326*917c2899SVille Syrjälä ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg, 327*917c2899SVille Syrjälä encoder->port, pipe); 328*917c2899SVille Syrjälä 329*917c2899SVille Syrjälä intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 330*917c2899SVille Syrjälä 331*917c2899SVille Syrjälä return ret; 332*917c2899SVille Syrjälä } 333*917c2899SVille Syrjälä 334*917c2899SVille Syrjälä static void intel_dp_get_config(struct intel_encoder *encoder, 335*917c2899SVille Syrjälä struct intel_crtc_state *pipe_config) 336*917c2899SVille Syrjälä { 337*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 338*917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 339*917c2899SVille Syrjälä u32 tmp, flags = 0; 340*917c2899SVille Syrjälä enum port port = encoder->port; 341*917c2899SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 342*917c2899SVille Syrjälä 343*917c2899SVille Syrjälä if (encoder->type == INTEL_OUTPUT_EDP) 344*917c2899SVille Syrjälä pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 345*917c2899SVille Syrjälä else 346*917c2899SVille Syrjälä pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 347*917c2899SVille Syrjälä 348*917c2899SVille Syrjälä tmp = intel_de_read(dev_priv, intel_dp->output_reg); 349*917c2899SVille Syrjälä 350*917c2899SVille Syrjälä pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; 351*917c2899SVille Syrjälä 352*917c2899SVille Syrjälä if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { 353*917c2899SVille Syrjälä u32 trans_dp = intel_de_read(dev_priv, 354*917c2899SVille Syrjälä TRANS_DP_CTL(crtc->pipe)); 355*917c2899SVille Syrjälä 356*917c2899SVille Syrjälä if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) 357*917c2899SVille Syrjälä flags |= DRM_MODE_FLAG_PHSYNC; 358*917c2899SVille Syrjälä else 359*917c2899SVille Syrjälä flags |= DRM_MODE_FLAG_NHSYNC; 360*917c2899SVille Syrjälä 361*917c2899SVille Syrjälä if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) 362*917c2899SVille Syrjälä flags |= DRM_MODE_FLAG_PVSYNC; 363*917c2899SVille Syrjälä else 364*917c2899SVille Syrjälä flags |= DRM_MODE_FLAG_NVSYNC; 365*917c2899SVille Syrjälä } else { 366*917c2899SVille Syrjälä if (tmp & DP_SYNC_HS_HIGH) 367*917c2899SVille Syrjälä flags |= DRM_MODE_FLAG_PHSYNC; 368*917c2899SVille Syrjälä else 369*917c2899SVille Syrjälä flags |= DRM_MODE_FLAG_NHSYNC; 370*917c2899SVille Syrjälä 371*917c2899SVille Syrjälä if (tmp & DP_SYNC_VS_HIGH) 372*917c2899SVille Syrjälä flags |= DRM_MODE_FLAG_PVSYNC; 373*917c2899SVille Syrjälä else 374*917c2899SVille Syrjälä flags |= DRM_MODE_FLAG_NVSYNC; 375*917c2899SVille Syrjälä } 376*917c2899SVille Syrjälä 377*917c2899SVille Syrjälä pipe_config->hw.adjusted_mode.flags |= flags; 378*917c2899SVille Syrjälä 379*917c2899SVille Syrjälä if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) 380*917c2899SVille Syrjälä pipe_config->limited_color_range = true; 381*917c2899SVille Syrjälä 382*917c2899SVille Syrjälä pipe_config->lane_count = 383*917c2899SVille Syrjälä ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; 384*917c2899SVille Syrjälä 385*917c2899SVille Syrjälä intel_dp_get_m_n(crtc, pipe_config); 386*917c2899SVille Syrjälä 387*917c2899SVille Syrjälä if (port == PORT_A) { 388*917c2899SVille Syrjälä if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) 389*917c2899SVille Syrjälä pipe_config->port_clock = 162000; 390*917c2899SVille Syrjälä else 391*917c2899SVille Syrjälä pipe_config->port_clock = 270000; 392*917c2899SVille Syrjälä } 393*917c2899SVille Syrjälä 394*917c2899SVille Syrjälä pipe_config->hw.adjusted_mode.crtc_clock = 395*917c2899SVille Syrjälä intel_dotclock_calculate(pipe_config->port_clock, 396*917c2899SVille Syrjälä &pipe_config->dp_m_n); 397*917c2899SVille Syrjälä 398*917c2899SVille Syrjälä if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp && 399*917c2899SVille Syrjälä pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 400*917c2899SVille Syrjälä /* 401*917c2899SVille Syrjälä * This is a big fat ugly hack. 402*917c2899SVille Syrjälä * 403*917c2899SVille Syrjälä * Some machines in UEFI boot mode provide us a VBT that has 18 404*917c2899SVille Syrjälä * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 405*917c2899SVille Syrjälä * unknown we fail to light up. Yet the same BIOS boots up with 406*917c2899SVille Syrjälä * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 407*917c2899SVille Syrjälä * max, not what it tells us to use. 408*917c2899SVille Syrjälä * 409*917c2899SVille Syrjälä * Note: This will still be broken if the eDP panel is not lit 410*917c2899SVille Syrjälä * up by the BIOS, and thus we can't get the mode at module 411*917c2899SVille Syrjälä * load. 412*917c2899SVille Syrjälä */ 413*917c2899SVille Syrjälä drm_dbg_kms(&dev_priv->drm, 414*917c2899SVille Syrjälä "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 415*917c2899SVille Syrjälä pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 416*917c2899SVille Syrjälä dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 417*917c2899SVille Syrjälä } 418*917c2899SVille Syrjälä } 419*917c2899SVille Syrjälä 420*917c2899SVille Syrjälä static void 421*917c2899SVille Syrjälä intel_dp_link_down(struct intel_encoder *encoder, 422*917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state) 423*917c2899SVille Syrjälä { 424*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 425*917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 426*917c2899SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 427*917c2899SVille Syrjälä enum port port = encoder->port; 428*917c2899SVille Syrjälä u32 DP = intel_dp->DP; 429*917c2899SVille Syrjälä 430*917c2899SVille Syrjälä if (drm_WARN_ON(&dev_priv->drm, 431*917c2899SVille Syrjälä (intel_de_read(dev_priv, intel_dp->output_reg) & 432*917c2899SVille Syrjälä DP_PORT_EN) == 0)) 433*917c2899SVille Syrjälä return; 434*917c2899SVille Syrjälä 435*917c2899SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "\n"); 436*917c2899SVille Syrjälä 437*917c2899SVille Syrjälä if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || 438*917c2899SVille Syrjälä (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { 439*917c2899SVille Syrjälä DP &= ~DP_LINK_TRAIN_MASK_CPT; 440*917c2899SVille Syrjälä DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; 441*917c2899SVille Syrjälä } else { 442*917c2899SVille Syrjälä DP &= ~DP_LINK_TRAIN_MASK; 443*917c2899SVille Syrjälä DP |= DP_LINK_TRAIN_PAT_IDLE; 444*917c2899SVille Syrjälä } 445*917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, DP); 446*917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 447*917c2899SVille Syrjälä 448*917c2899SVille Syrjälä DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 449*917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, DP); 450*917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 451*917c2899SVille Syrjälä 452*917c2899SVille Syrjälä /* 453*917c2899SVille Syrjälä * HW workaround for IBX, we need to move the port 454*917c2899SVille Syrjälä * to transcoder A after disabling it to allow the 455*917c2899SVille Syrjälä * matching HDMI port to be enabled on transcoder A. 456*917c2899SVille Syrjälä */ 457*917c2899SVille Syrjälä if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { 458*917c2899SVille Syrjälä /* 459*917c2899SVille Syrjälä * We get CPU/PCH FIFO underruns on the other pipe when 460*917c2899SVille Syrjälä * doing the workaround. Sweep them under the rug. 461*917c2899SVille Syrjälä */ 462*917c2899SVille Syrjälä intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 463*917c2899SVille Syrjälä intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 464*917c2899SVille Syrjälä 465*917c2899SVille Syrjälä /* always enable with pattern 1 (as per spec) */ 466*917c2899SVille Syrjälä DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK); 467*917c2899SVille Syrjälä DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | 468*917c2899SVille Syrjälä DP_LINK_TRAIN_PAT_1; 469*917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, DP); 470*917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 471*917c2899SVille Syrjälä 472*917c2899SVille Syrjälä DP &= ~DP_PORT_EN; 473*917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, DP); 474*917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 475*917c2899SVille Syrjälä 476*917c2899SVille Syrjälä intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 477*917c2899SVille Syrjälä intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 478*917c2899SVille Syrjälä intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 479*917c2899SVille Syrjälä } 480*917c2899SVille Syrjälä 481*917c2899SVille Syrjälä msleep(intel_dp->pps.panel_power_down_delay); 482*917c2899SVille Syrjälä 483*917c2899SVille Syrjälä intel_dp->DP = DP; 484*917c2899SVille Syrjälä 485*917c2899SVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 486*917c2899SVille Syrjälä intel_wakeref_t wakeref; 487*917c2899SVille Syrjälä 488*917c2899SVille Syrjälä with_intel_pps_lock(intel_dp, wakeref) 489*917c2899SVille Syrjälä intel_dp->pps.active_pipe = INVALID_PIPE; 490*917c2899SVille Syrjälä } 491*917c2899SVille Syrjälä } 492*917c2899SVille Syrjälä 493*917c2899SVille Syrjälä static void intel_disable_dp(struct intel_atomic_state *state, 494*917c2899SVille Syrjälä struct intel_encoder *encoder, 495*917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state, 496*917c2899SVille Syrjälä const struct drm_connector_state *old_conn_state) 497*917c2899SVille Syrjälä { 498*917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 499*917c2899SVille Syrjälä 500*917c2899SVille Syrjälä intel_dp->link_trained = false; 501*917c2899SVille Syrjälä 502*917c2899SVille Syrjälä if (old_crtc_state->has_audio) 503*917c2899SVille Syrjälä intel_audio_codec_disable(encoder, 504*917c2899SVille Syrjälä old_crtc_state, old_conn_state); 505*917c2899SVille Syrjälä 506*917c2899SVille Syrjälä /* 507*917c2899SVille Syrjälä * Make sure the panel is off before trying to change the mode. 508*917c2899SVille Syrjälä * But also ensure that we have vdd while we switch off the panel. 509*917c2899SVille Syrjälä */ 510*917c2899SVille Syrjälä intel_pps_vdd_on(intel_dp); 511*917c2899SVille Syrjälä intel_edp_backlight_off(old_conn_state); 512*917c2899SVille Syrjälä intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 513*917c2899SVille Syrjälä intel_pps_off(intel_dp); 514*917c2899SVille Syrjälä } 515*917c2899SVille Syrjälä 516*917c2899SVille Syrjälä static void g4x_disable_dp(struct intel_atomic_state *state, 517*917c2899SVille Syrjälä struct intel_encoder *encoder, 518*917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state, 519*917c2899SVille Syrjälä const struct drm_connector_state *old_conn_state) 520*917c2899SVille Syrjälä { 521*917c2899SVille Syrjälä intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); 522*917c2899SVille Syrjälä } 523*917c2899SVille Syrjälä 524*917c2899SVille Syrjälä static void vlv_disable_dp(struct intel_atomic_state *state, 525*917c2899SVille Syrjälä struct intel_encoder *encoder, 526*917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state, 527*917c2899SVille Syrjälä const struct drm_connector_state *old_conn_state) 528*917c2899SVille Syrjälä { 529*917c2899SVille Syrjälä intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); 530*917c2899SVille Syrjälä } 531*917c2899SVille Syrjälä 532*917c2899SVille Syrjälä static void g4x_post_disable_dp(struct intel_atomic_state *state, 533*917c2899SVille Syrjälä struct intel_encoder *encoder, 534*917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state, 535*917c2899SVille Syrjälä const struct drm_connector_state *old_conn_state) 536*917c2899SVille Syrjälä { 537*917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 538*917c2899SVille Syrjälä enum port port = encoder->port; 539*917c2899SVille Syrjälä 540*917c2899SVille Syrjälä /* 541*917c2899SVille Syrjälä * Bspec does not list a specific disable sequence for g4x DP. 542*917c2899SVille Syrjälä * Follow the ilk+ sequence (disable pipe before the port) for 543*917c2899SVille Syrjälä * g4x DP as it does not suffer from underruns like the normal 544*917c2899SVille Syrjälä * g4x modeset sequence (disable pipe after the port). 545*917c2899SVille Syrjälä */ 546*917c2899SVille Syrjälä intel_dp_link_down(encoder, old_crtc_state); 547*917c2899SVille Syrjälä 548*917c2899SVille Syrjälä /* Only ilk+ has port A */ 549*917c2899SVille Syrjälä if (port == PORT_A) 550*917c2899SVille Syrjälä ilk_edp_pll_off(intel_dp, old_crtc_state); 551*917c2899SVille Syrjälä } 552*917c2899SVille Syrjälä 553*917c2899SVille Syrjälä static void vlv_post_disable_dp(struct intel_atomic_state *state, 554*917c2899SVille Syrjälä struct intel_encoder *encoder, 555*917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state, 556*917c2899SVille Syrjälä const struct drm_connector_state *old_conn_state) 557*917c2899SVille Syrjälä { 558*917c2899SVille Syrjälä intel_dp_link_down(encoder, old_crtc_state); 559*917c2899SVille Syrjälä } 560*917c2899SVille Syrjälä 561*917c2899SVille Syrjälä static void chv_post_disable_dp(struct intel_atomic_state *state, 562*917c2899SVille Syrjälä struct intel_encoder *encoder, 563*917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state, 564*917c2899SVille Syrjälä const struct drm_connector_state *old_conn_state) 565*917c2899SVille Syrjälä { 566*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 567*917c2899SVille Syrjälä 568*917c2899SVille Syrjälä intel_dp_link_down(encoder, old_crtc_state); 569*917c2899SVille Syrjälä 570*917c2899SVille Syrjälä vlv_dpio_get(dev_priv); 571*917c2899SVille Syrjälä 572*917c2899SVille Syrjälä /* Assert data lane reset */ 573*917c2899SVille Syrjälä chv_data_lane_soft_reset(encoder, old_crtc_state, true); 574*917c2899SVille Syrjälä 575*917c2899SVille Syrjälä vlv_dpio_put(dev_priv); 576*917c2899SVille Syrjälä } 577*917c2899SVille Syrjälä 578*917c2899SVille Syrjälä static void 579*917c2899SVille Syrjälä cpt_set_link_train(struct intel_dp *intel_dp, 580*917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state, 581*917c2899SVille Syrjälä u8 dp_train_pat) 582*917c2899SVille Syrjälä { 583*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 584*917c2899SVille Syrjälä u32 *DP = &intel_dp->DP; 585*917c2899SVille Syrjälä 586*917c2899SVille Syrjälä *DP &= ~DP_LINK_TRAIN_MASK_CPT; 587*917c2899SVille Syrjälä 588*917c2899SVille Syrjälä switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 589*917c2899SVille Syrjälä case DP_TRAINING_PATTERN_DISABLE: 590*917c2899SVille Syrjälä *DP |= DP_LINK_TRAIN_OFF_CPT; 591*917c2899SVille Syrjälä break; 592*917c2899SVille Syrjälä case DP_TRAINING_PATTERN_1: 593*917c2899SVille Syrjälä *DP |= DP_LINK_TRAIN_PAT_1_CPT; 594*917c2899SVille Syrjälä break; 595*917c2899SVille Syrjälä case DP_TRAINING_PATTERN_2: 596*917c2899SVille Syrjälä *DP |= DP_LINK_TRAIN_PAT_2_CPT; 597*917c2899SVille Syrjälä break; 598*917c2899SVille Syrjälä default: 599*917c2899SVille Syrjälä MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat)); 600*917c2899SVille Syrjälä return; 601*917c2899SVille Syrjälä } 602*917c2899SVille Syrjälä 603*917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 604*917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 605*917c2899SVille Syrjälä } 606*917c2899SVille Syrjälä 607*917c2899SVille Syrjälä static void 608*917c2899SVille Syrjälä g4x_set_link_train(struct intel_dp *intel_dp, 609*917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state, 610*917c2899SVille Syrjälä u8 dp_train_pat) 611*917c2899SVille Syrjälä { 612*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 613*917c2899SVille Syrjälä u32 *DP = &intel_dp->DP; 614*917c2899SVille Syrjälä 615*917c2899SVille Syrjälä *DP &= ~DP_LINK_TRAIN_MASK; 616*917c2899SVille Syrjälä 617*917c2899SVille Syrjälä switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 618*917c2899SVille Syrjälä case DP_TRAINING_PATTERN_DISABLE: 619*917c2899SVille Syrjälä *DP |= DP_LINK_TRAIN_OFF; 620*917c2899SVille Syrjälä break; 621*917c2899SVille Syrjälä case DP_TRAINING_PATTERN_1: 622*917c2899SVille Syrjälä *DP |= DP_LINK_TRAIN_PAT_1; 623*917c2899SVille Syrjälä break; 624*917c2899SVille Syrjälä case DP_TRAINING_PATTERN_2: 625*917c2899SVille Syrjälä *DP |= DP_LINK_TRAIN_PAT_2; 626*917c2899SVille Syrjälä break; 627*917c2899SVille Syrjälä default: 628*917c2899SVille Syrjälä MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat)); 629*917c2899SVille Syrjälä return; 630*917c2899SVille Syrjälä } 631*917c2899SVille Syrjälä 632*917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 633*917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 634*917c2899SVille Syrjälä } 635*917c2899SVille Syrjälä 636*917c2899SVille Syrjälä static void intel_dp_enable_port(struct intel_dp *intel_dp, 637*917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state) 638*917c2899SVille Syrjälä { 639*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 640*917c2899SVille Syrjälä 641*917c2899SVille Syrjälä /* enable with pattern 1 (as per spec) */ 642*917c2899SVille Syrjälä 643*917c2899SVille Syrjälä intel_dp_program_link_training_pattern(intel_dp, crtc_state, 644*917c2899SVille Syrjälä DP_TRAINING_PATTERN_1); 645*917c2899SVille Syrjälä 646*917c2899SVille Syrjälä /* 647*917c2899SVille Syrjälä * Magic for VLV/CHV. We _must_ first set up the register 648*917c2899SVille Syrjälä * without actually enabling the port, and then do another 649*917c2899SVille Syrjälä * write to enable the port. Otherwise link training will 650*917c2899SVille Syrjälä * fail when the power sequencer is freshly used for this port. 651*917c2899SVille Syrjälä */ 652*917c2899SVille Syrjälä intel_dp->DP |= DP_PORT_EN; 653*917c2899SVille Syrjälä if (crtc_state->has_audio) 654*917c2899SVille Syrjälä intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 655*917c2899SVille Syrjälä 656*917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 657*917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 658*917c2899SVille Syrjälä } 659*917c2899SVille Syrjälä 660*917c2899SVille Syrjälä static void intel_enable_dp(struct intel_atomic_state *state, 661*917c2899SVille Syrjälä struct intel_encoder *encoder, 662*917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config, 663*917c2899SVille Syrjälä const struct drm_connector_state *conn_state) 664*917c2899SVille Syrjälä { 665*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 666*917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 667*917c2899SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 668*917c2899SVille Syrjälä u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg); 669*917c2899SVille Syrjälä enum pipe pipe = crtc->pipe; 670*917c2899SVille Syrjälä intel_wakeref_t wakeref; 671*917c2899SVille Syrjälä 672*917c2899SVille Syrjälä if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN)) 673*917c2899SVille Syrjälä return; 674*917c2899SVille Syrjälä 675*917c2899SVille Syrjälä with_intel_pps_lock(intel_dp, wakeref) { 676*917c2899SVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 677*917c2899SVille Syrjälä vlv_pps_init(encoder, pipe_config); 678*917c2899SVille Syrjälä 679*917c2899SVille Syrjälä intel_dp_enable_port(intel_dp, pipe_config); 680*917c2899SVille Syrjälä 681*917c2899SVille Syrjälä intel_pps_vdd_on_unlocked(intel_dp); 682*917c2899SVille Syrjälä intel_pps_on_unlocked(intel_dp); 683*917c2899SVille Syrjälä intel_pps_vdd_off_unlocked(intel_dp, true); 684*917c2899SVille Syrjälä } 685*917c2899SVille Syrjälä 686*917c2899SVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 687*917c2899SVille Syrjälä unsigned int lane_mask = 0x0; 688*917c2899SVille Syrjälä 689*917c2899SVille Syrjälä if (IS_CHERRYVIEW(dev_priv)) 690*917c2899SVille Syrjälä lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); 691*917c2899SVille Syrjälä 692*917c2899SVille Syrjälä vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), 693*917c2899SVille Syrjälä lane_mask); 694*917c2899SVille Syrjälä } 695*917c2899SVille Syrjälä 696*917c2899SVille Syrjälä intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 697*917c2899SVille Syrjälä intel_dp_configure_protocol_converter(intel_dp, pipe_config); 698*917c2899SVille Syrjälä intel_dp_check_frl_training(intel_dp); 699*917c2899SVille Syrjälä intel_dp_pcon_dsc_configure(intel_dp, pipe_config); 700*917c2899SVille Syrjälä intel_dp_start_link_train(intel_dp, pipe_config); 701*917c2899SVille Syrjälä intel_dp_stop_link_train(intel_dp, pipe_config); 702*917c2899SVille Syrjälä 703*917c2899SVille Syrjälä if (pipe_config->has_audio) { 704*917c2899SVille Syrjälä drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n", 705*917c2899SVille Syrjälä pipe_name(pipe)); 706*917c2899SVille Syrjälä intel_audio_codec_enable(encoder, pipe_config, conn_state); 707*917c2899SVille Syrjälä } 708*917c2899SVille Syrjälä } 709*917c2899SVille Syrjälä 710*917c2899SVille Syrjälä static void g4x_enable_dp(struct intel_atomic_state *state, 711*917c2899SVille Syrjälä struct intel_encoder *encoder, 712*917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config, 713*917c2899SVille Syrjälä const struct drm_connector_state *conn_state) 714*917c2899SVille Syrjälä { 715*917c2899SVille Syrjälä intel_enable_dp(state, encoder, pipe_config, conn_state); 716*917c2899SVille Syrjälä intel_edp_backlight_on(pipe_config, conn_state); 717*917c2899SVille Syrjälä } 718*917c2899SVille Syrjälä 719*917c2899SVille Syrjälä static void vlv_enable_dp(struct intel_atomic_state *state, 720*917c2899SVille Syrjälä struct intel_encoder *encoder, 721*917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config, 722*917c2899SVille Syrjälä const struct drm_connector_state *conn_state) 723*917c2899SVille Syrjälä { 724*917c2899SVille Syrjälä intel_edp_backlight_on(pipe_config, conn_state); 725*917c2899SVille Syrjälä } 726*917c2899SVille Syrjälä 727*917c2899SVille Syrjälä static void g4x_pre_enable_dp(struct intel_atomic_state *state, 728*917c2899SVille Syrjälä struct intel_encoder *encoder, 729*917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config, 730*917c2899SVille Syrjälä const struct drm_connector_state *conn_state) 731*917c2899SVille Syrjälä { 732*917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 733*917c2899SVille Syrjälä enum port port = encoder->port; 734*917c2899SVille Syrjälä 735*917c2899SVille Syrjälä intel_dp_prepare(encoder, pipe_config); 736*917c2899SVille Syrjälä 737*917c2899SVille Syrjälä /* Only ilk+ has port A */ 738*917c2899SVille Syrjälä if (port == PORT_A) 739*917c2899SVille Syrjälä ilk_edp_pll_on(intel_dp, pipe_config); 740*917c2899SVille Syrjälä } 741*917c2899SVille Syrjälä 742*917c2899SVille Syrjälä static void vlv_pre_enable_dp(struct intel_atomic_state *state, 743*917c2899SVille Syrjälä struct intel_encoder *encoder, 744*917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config, 745*917c2899SVille Syrjälä const struct drm_connector_state *conn_state) 746*917c2899SVille Syrjälä { 747*917c2899SVille Syrjälä vlv_phy_pre_encoder_enable(encoder, pipe_config); 748*917c2899SVille Syrjälä 749*917c2899SVille Syrjälä intel_enable_dp(state, encoder, pipe_config, conn_state); 750*917c2899SVille Syrjälä } 751*917c2899SVille Syrjälä 752*917c2899SVille Syrjälä static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state, 753*917c2899SVille Syrjälä struct intel_encoder *encoder, 754*917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config, 755*917c2899SVille Syrjälä const struct drm_connector_state *conn_state) 756*917c2899SVille Syrjälä { 757*917c2899SVille Syrjälä intel_dp_prepare(encoder, pipe_config); 758*917c2899SVille Syrjälä 759*917c2899SVille Syrjälä vlv_phy_pre_pll_enable(encoder, pipe_config); 760*917c2899SVille Syrjälä } 761*917c2899SVille Syrjälä 762*917c2899SVille Syrjälä static void chv_pre_enable_dp(struct intel_atomic_state *state, 763*917c2899SVille Syrjälä struct intel_encoder *encoder, 764*917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config, 765*917c2899SVille Syrjälä const struct drm_connector_state *conn_state) 766*917c2899SVille Syrjälä { 767*917c2899SVille Syrjälä chv_phy_pre_encoder_enable(encoder, pipe_config); 768*917c2899SVille Syrjälä 769*917c2899SVille Syrjälä intel_enable_dp(state, encoder, pipe_config, conn_state); 770*917c2899SVille Syrjälä 771*917c2899SVille Syrjälä /* Second common lane will stay alive on its own now */ 772*917c2899SVille Syrjälä chv_phy_release_cl2_override(encoder); 773*917c2899SVille Syrjälä } 774*917c2899SVille Syrjälä 775*917c2899SVille Syrjälä static void chv_dp_pre_pll_enable(struct intel_atomic_state *state, 776*917c2899SVille Syrjälä struct intel_encoder *encoder, 777*917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config, 778*917c2899SVille Syrjälä const struct drm_connector_state *conn_state) 779*917c2899SVille Syrjälä { 780*917c2899SVille Syrjälä intel_dp_prepare(encoder, pipe_config); 781*917c2899SVille Syrjälä 782*917c2899SVille Syrjälä chv_phy_pre_pll_enable(encoder, pipe_config); 783*917c2899SVille Syrjälä } 784*917c2899SVille Syrjälä 785*917c2899SVille Syrjälä static void chv_dp_post_pll_disable(struct intel_atomic_state *state, 786*917c2899SVille Syrjälä struct intel_encoder *encoder, 787*917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state, 788*917c2899SVille Syrjälä const struct drm_connector_state *old_conn_state) 789*917c2899SVille Syrjälä { 790*917c2899SVille Syrjälä chv_phy_post_pll_disable(encoder, old_crtc_state); 791*917c2899SVille Syrjälä } 792*917c2899SVille Syrjälä 793*917c2899SVille Syrjälä static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp, 794*917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state) 795*917c2899SVille Syrjälä { 796*917c2899SVille Syrjälä return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 797*917c2899SVille Syrjälä } 798*917c2899SVille Syrjälä 799*917c2899SVille Syrjälä static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp, 800*917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state) 801*917c2899SVille Syrjälä { 802*917c2899SVille Syrjälä return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 803*917c2899SVille Syrjälä } 804*917c2899SVille Syrjälä 805*917c2899SVille Syrjälä static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp) 806*917c2899SVille Syrjälä { 807*917c2899SVille Syrjälä return DP_TRAIN_PRE_EMPH_LEVEL_2; 808*917c2899SVille Syrjälä } 809*917c2899SVille Syrjälä 810*917c2899SVille Syrjälä static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp) 811*917c2899SVille Syrjälä { 812*917c2899SVille Syrjälä return DP_TRAIN_PRE_EMPH_LEVEL_3; 813*917c2899SVille Syrjälä } 814*917c2899SVille Syrjälä 815*917c2899SVille Syrjälä static void vlv_set_signal_levels(struct intel_dp *intel_dp, 816*917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state) 817*917c2899SVille Syrjälä { 818*917c2899SVille Syrjälä struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 819*917c2899SVille Syrjälä unsigned long demph_reg_value, preemph_reg_value, 820*917c2899SVille Syrjälä uniqtranscale_reg_value; 821*917c2899SVille Syrjälä u8 train_set = intel_dp->train_set[0]; 822*917c2899SVille Syrjälä 823*917c2899SVille Syrjälä switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 824*917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_0: 825*917c2899SVille Syrjälä preemph_reg_value = 0x0004000; 826*917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 827*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 828*917c2899SVille Syrjälä demph_reg_value = 0x2B405555; 829*917c2899SVille Syrjälä uniqtranscale_reg_value = 0x552AB83A; 830*917c2899SVille Syrjälä break; 831*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 832*917c2899SVille Syrjälä demph_reg_value = 0x2B404040; 833*917c2899SVille Syrjälä uniqtranscale_reg_value = 0x5548B83A; 834*917c2899SVille Syrjälä break; 835*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 836*917c2899SVille Syrjälä demph_reg_value = 0x2B245555; 837*917c2899SVille Syrjälä uniqtranscale_reg_value = 0x5560B83A; 838*917c2899SVille Syrjälä break; 839*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 840*917c2899SVille Syrjälä demph_reg_value = 0x2B405555; 841*917c2899SVille Syrjälä uniqtranscale_reg_value = 0x5598DA3A; 842*917c2899SVille Syrjälä break; 843*917c2899SVille Syrjälä default: 844*917c2899SVille Syrjälä return; 845*917c2899SVille Syrjälä } 846*917c2899SVille Syrjälä break; 847*917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_1: 848*917c2899SVille Syrjälä preemph_reg_value = 0x0002000; 849*917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 850*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 851*917c2899SVille Syrjälä demph_reg_value = 0x2B404040; 852*917c2899SVille Syrjälä uniqtranscale_reg_value = 0x5552B83A; 853*917c2899SVille Syrjälä break; 854*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 855*917c2899SVille Syrjälä demph_reg_value = 0x2B404848; 856*917c2899SVille Syrjälä uniqtranscale_reg_value = 0x5580B83A; 857*917c2899SVille Syrjälä break; 858*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 859*917c2899SVille Syrjälä demph_reg_value = 0x2B404040; 860*917c2899SVille Syrjälä uniqtranscale_reg_value = 0x55ADDA3A; 861*917c2899SVille Syrjälä break; 862*917c2899SVille Syrjälä default: 863*917c2899SVille Syrjälä return; 864*917c2899SVille Syrjälä } 865*917c2899SVille Syrjälä break; 866*917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_2: 867*917c2899SVille Syrjälä preemph_reg_value = 0x0000000; 868*917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 869*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 870*917c2899SVille Syrjälä demph_reg_value = 0x2B305555; 871*917c2899SVille Syrjälä uniqtranscale_reg_value = 0x5570B83A; 872*917c2899SVille Syrjälä break; 873*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 874*917c2899SVille Syrjälä demph_reg_value = 0x2B2B4040; 875*917c2899SVille Syrjälä uniqtranscale_reg_value = 0x55ADDA3A; 876*917c2899SVille Syrjälä break; 877*917c2899SVille Syrjälä default: 878*917c2899SVille Syrjälä return; 879*917c2899SVille Syrjälä } 880*917c2899SVille Syrjälä break; 881*917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_3: 882*917c2899SVille Syrjälä preemph_reg_value = 0x0006000; 883*917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 884*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 885*917c2899SVille Syrjälä demph_reg_value = 0x1B405555; 886*917c2899SVille Syrjälä uniqtranscale_reg_value = 0x55ADDA3A; 887*917c2899SVille Syrjälä break; 888*917c2899SVille Syrjälä default: 889*917c2899SVille Syrjälä return; 890*917c2899SVille Syrjälä } 891*917c2899SVille Syrjälä break; 892*917c2899SVille Syrjälä default: 893*917c2899SVille Syrjälä return; 894*917c2899SVille Syrjälä } 895*917c2899SVille Syrjälä 896*917c2899SVille Syrjälä vlv_set_phy_signal_level(encoder, crtc_state, 897*917c2899SVille Syrjälä demph_reg_value, preemph_reg_value, 898*917c2899SVille Syrjälä uniqtranscale_reg_value, 0); 899*917c2899SVille Syrjälä } 900*917c2899SVille Syrjälä 901*917c2899SVille Syrjälä static void chv_set_signal_levels(struct intel_dp *intel_dp, 902*917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state) 903*917c2899SVille Syrjälä { 904*917c2899SVille Syrjälä struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 905*917c2899SVille Syrjälä u32 deemph_reg_value, margin_reg_value; 906*917c2899SVille Syrjälä bool uniq_trans_scale = false; 907*917c2899SVille Syrjälä u8 train_set = intel_dp->train_set[0]; 908*917c2899SVille Syrjälä 909*917c2899SVille Syrjälä switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 910*917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_0: 911*917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 912*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 913*917c2899SVille Syrjälä deemph_reg_value = 128; 914*917c2899SVille Syrjälä margin_reg_value = 52; 915*917c2899SVille Syrjälä break; 916*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 917*917c2899SVille Syrjälä deemph_reg_value = 128; 918*917c2899SVille Syrjälä margin_reg_value = 77; 919*917c2899SVille Syrjälä break; 920*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 921*917c2899SVille Syrjälä deemph_reg_value = 128; 922*917c2899SVille Syrjälä margin_reg_value = 102; 923*917c2899SVille Syrjälä break; 924*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 925*917c2899SVille Syrjälä deemph_reg_value = 128; 926*917c2899SVille Syrjälä margin_reg_value = 154; 927*917c2899SVille Syrjälä uniq_trans_scale = true; 928*917c2899SVille Syrjälä break; 929*917c2899SVille Syrjälä default: 930*917c2899SVille Syrjälä return; 931*917c2899SVille Syrjälä } 932*917c2899SVille Syrjälä break; 933*917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_1: 934*917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 935*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 936*917c2899SVille Syrjälä deemph_reg_value = 85; 937*917c2899SVille Syrjälä margin_reg_value = 78; 938*917c2899SVille Syrjälä break; 939*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 940*917c2899SVille Syrjälä deemph_reg_value = 85; 941*917c2899SVille Syrjälä margin_reg_value = 116; 942*917c2899SVille Syrjälä break; 943*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 944*917c2899SVille Syrjälä deemph_reg_value = 85; 945*917c2899SVille Syrjälä margin_reg_value = 154; 946*917c2899SVille Syrjälä break; 947*917c2899SVille Syrjälä default: 948*917c2899SVille Syrjälä return; 949*917c2899SVille Syrjälä } 950*917c2899SVille Syrjälä break; 951*917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_2: 952*917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 953*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 954*917c2899SVille Syrjälä deemph_reg_value = 64; 955*917c2899SVille Syrjälä margin_reg_value = 104; 956*917c2899SVille Syrjälä break; 957*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 958*917c2899SVille Syrjälä deemph_reg_value = 64; 959*917c2899SVille Syrjälä margin_reg_value = 154; 960*917c2899SVille Syrjälä break; 961*917c2899SVille Syrjälä default: 962*917c2899SVille Syrjälä return; 963*917c2899SVille Syrjälä } 964*917c2899SVille Syrjälä break; 965*917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_3: 966*917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 967*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 968*917c2899SVille Syrjälä deemph_reg_value = 43; 969*917c2899SVille Syrjälä margin_reg_value = 154; 970*917c2899SVille Syrjälä break; 971*917c2899SVille Syrjälä default: 972*917c2899SVille Syrjälä return; 973*917c2899SVille Syrjälä } 974*917c2899SVille Syrjälä break; 975*917c2899SVille Syrjälä default: 976*917c2899SVille Syrjälä return; 977*917c2899SVille Syrjälä } 978*917c2899SVille Syrjälä 979*917c2899SVille Syrjälä chv_set_phy_signal_level(encoder, crtc_state, 980*917c2899SVille Syrjälä deemph_reg_value, margin_reg_value, 981*917c2899SVille Syrjälä uniq_trans_scale); 982*917c2899SVille Syrjälä } 983*917c2899SVille Syrjälä 984*917c2899SVille Syrjälä static u32 g4x_signal_levels(u8 train_set) 985*917c2899SVille Syrjälä { 986*917c2899SVille Syrjälä u32 signal_levels = 0; 987*917c2899SVille Syrjälä 988*917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 989*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 990*917c2899SVille Syrjälä default: 991*917c2899SVille Syrjälä signal_levels |= DP_VOLTAGE_0_4; 992*917c2899SVille Syrjälä break; 993*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 994*917c2899SVille Syrjälä signal_levels |= DP_VOLTAGE_0_6; 995*917c2899SVille Syrjälä break; 996*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 997*917c2899SVille Syrjälä signal_levels |= DP_VOLTAGE_0_8; 998*917c2899SVille Syrjälä break; 999*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 1000*917c2899SVille Syrjälä signal_levels |= DP_VOLTAGE_1_2; 1001*917c2899SVille Syrjälä break; 1002*917c2899SVille Syrjälä } 1003*917c2899SVille Syrjälä switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 1004*917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_0: 1005*917c2899SVille Syrjälä default: 1006*917c2899SVille Syrjälä signal_levels |= DP_PRE_EMPHASIS_0; 1007*917c2899SVille Syrjälä break; 1008*917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_1: 1009*917c2899SVille Syrjälä signal_levels |= DP_PRE_EMPHASIS_3_5; 1010*917c2899SVille Syrjälä break; 1011*917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_2: 1012*917c2899SVille Syrjälä signal_levels |= DP_PRE_EMPHASIS_6; 1013*917c2899SVille Syrjälä break; 1014*917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_3: 1015*917c2899SVille Syrjälä signal_levels |= DP_PRE_EMPHASIS_9_5; 1016*917c2899SVille Syrjälä break; 1017*917c2899SVille Syrjälä } 1018*917c2899SVille Syrjälä return signal_levels; 1019*917c2899SVille Syrjälä } 1020*917c2899SVille Syrjälä 1021*917c2899SVille Syrjälä static void 1022*917c2899SVille Syrjälä g4x_set_signal_levels(struct intel_dp *intel_dp, 1023*917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state) 1024*917c2899SVille Syrjälä { 1025*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1026*917c2899SVille Syrjälä u8 train_set = intel_dp->train_set[0]; 1027*917c2899SVille Syrjälä u32 signal_levels; 1028*917c2899SVille Syrjälä 1029*917c2899SVille Syrjälä signal_levels = g4x_signal_levels(train_set); 1030*917c2899SVille Syrjälä 1031*917c2899SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1032*917c2899SVille Syrjälä signal_levels); 1033*917c2899SVille Syrjälä 1034*917c2899SVille Syrjälä intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK); 1035*917c2899SVille Syrjälä intel_dp->DP |= signal_levels; 1036*917c2899SVille Syrjälä 1037*917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 1038*917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 1039*917c2899SVille Syrjälä } 1040*917c2899SVille Syrjälä 1041*917c2899SVille Syrjälä /* SNB CPU eDP voltage swing and pre-emphasis control */ 1042*917c2899SVille Syrjälä static u32 snb_cpu_edp_signal_levels(u8 train_set) 1043*917c2899SVille Syrjälä { 1044*917c2899SVille Syrjälä u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1045*917c2899SVille Syrjälä DP_TRAIN_PRE_EMPHASIS_MASK); 1046*917c2899SVille Syrjälä 1047*917c2899SVille Syrjälä switch (signal_levels) { 1048*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1049*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1050*917c2899SVille Syrjälä return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1051*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1052*917c2899SVille Syrjälä return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 1053*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1054*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1055*917c2899SVille Syrjälä return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 1056*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1057*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1058*917c2899SVille Syrjälä return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 1059*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1060*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1061*917c2899SVille Syrjälä return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 1062*917c2899SVille Syrjälä default: 1063*917c2899SVille Syrjälä MISSING_CASE(signal_levels); 1064*917c2899SVille Syrjälä return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1065*917c2899SVille Syrjälä } 1066*917c2899SVille Syrjälä } 1067*917c2899SVille Syrjälä 1068*917c2899SVille Syrjälä static void 1069*917c2899SVille Syrjälä snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp, 1070*917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state) 1071*917c2899SVille Syrjälä { 1072*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1073*917c2899SVille Syrjälä u8 train_set = intel_dp->train_set[0]; 1074*917c2899SVille Syrjälä u32 signal_levels; 1075*917c2899SVille Syrjälä 1076*917c2899SVille Syrjälä signal_levels = snb_cpu_edp_signal_levels(train_set); 1077*917c2899SVille Syrjälä 1078*917c2899SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1079*917c2899SVille Syrjälä signal_levels); 1080*917c2899SVille Syrjälä 1081*917c2899SVille Syrjälä intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 1082*917c2899SVille Syrjälä intel_dp->DP |= signal_levels; 1083*917c2899SVille Syrjälä 1084*917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 1085*917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 1086*917c2899SVille Syrjälä } 1087*917c2899SVille Syrjälä 1088*917c2899SVille Syrjälä /* IVB CPU eDP voltage swing and pre-emphasis control */ 1089*917c2899SVille Syrjälä static u32 ivb_cpu_edp_signal_levels(u8 train_set) 1090*917c2899SVille Syrjälä { 1091*917c2899SVille Syrjälä u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1092*917c2899SVille Syrjälä DP_TRAIN_PRE_EMPHASIS_MASK); 1093*917c2899SVille Syrjälä 1094*917c2899SVille Syrjälä switch (signal_levels) { 1095*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1096*917c2899SVille Syrjälä return EDP_LINK_TRAIN_400MV_0DB_IVB; 1097*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1098*917c2899SVille Syrjälä return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 1099*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1100*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1101*917c2899SVille Syrjälä return EDP_LINK_TRAIN_400MV_6DB_IVB; 1102*917c2899SVille Syrjälä 1103*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1104*917c2899SVille Syrjälä return EDP_LINK_TRAIN_600MV_0DB_IVB; 1105*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1106*917c2899SVille Syrjälä return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 1107*917c2899SVille Syrjälä 1108*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1109*917c2899SVille Syrjälä return EDP_LINK_TRAIN_800MV_0DB_IVB; 1110*917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1111*917c2899SVille Syrjälä return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 1112*917c2899SVille Syrjälä 1113*917c2899SVille Syrjälä default: 1114*917c2899SVille Syrjälä MISSING_CASE(signal_levels); 1115*917c2899SVille Syrjälä return EDP_LINK_TRAIN_500MV_0DB_IVB; 1116*917c2899SVille Syrjälä } 1117*917c2899SVille Syrjälä } 1118*917c2899SVille Syrjälä 1119*917c2899SVille Syrjälä static void 1120*917c2899SVille Syrjälä ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp, 1121*917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state) 1122*917c2899SVille Syrjälä { 1123*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1124*917c2899SVille Syrjälä u8 train_set = intel_dp->train_set[0]; 1125*917c2899SVille Syrjälä u32 signal_levels; 1126*917c2899SVille Syrjälä 1127*917c2899SVille Syrjälä signal_levels = ivb_cpu_edp_signal_levels(train_set); 1128*917c2899SVille Syrjälä 1129*917c2899SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1130*917c2899SVille Syrjälä signal_levels); 1131*917c2899SVille Syrjälä 1132*917c2899SVille Syrjälä intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 1133*917c2899SVille Syrjälä intel_dp->DP |= signal_levels; 1134*917c2899SVille Syrjälä 1135*917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 1136*917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 1137*917c2899SVille Syrjälä } 1138*917c2899SVille Syrjälä 1139*917c2899SVille Syrjälä /* 1140*917c2899SVille Syrjälä * If display is now connected check links status, 1141*917c2899SVille Syrjälä * there has been known issues of link loss triggering 1142*917c2899SVille Syrjälä * long pulse. 1143*917c2899SVille Syrjälä * 1144*917c2899SVille Syrjälä * Some sinks (eg. ASUS PB287Q) seem to perform some 1145*917c2899SVille Syrjälä * weird HPD ping pong during modesets. So we can apparently 1146*917c2899SVille Syrjälä * end up with HPD going low during a modeset, and then 1147*917c2899SVille Syrjälä * going back up soon after. And once that happens we must 1148*917c2899SVille Syrjälä * retrain the link to get a picture. That's in case no 1149*917c2899SVille Syrjälä * userspace component reacted to intermittent HPD dip. 1150*917c2899SVille Syrjälä */ 1151*917c2899SVille Syrjälä static enum intel_hotplug_state 1152*917c2899SVille Syrjälä intel_dp_hotplug(struct intel_encoder *encoder, 1153*917c2899SVille Syrjälä struct intel_connector *connector) 1154*917c2899SVille Syrjälä { 1155*917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1156*917c2899SVille Syrjälä struct drm_modeset_acquire_ctx ctx; 1157*917c2899SVille Syrjälä enum intel_hotplug_state state; 1158*917c2899SVille Syrjälä int ret; 1159*917c2899SVille Syrjälä 1160*917c2899SVille Syrjälä if (intel_dp->compliance.test_active && 1161*917c2899SVille Syrjälä intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 1162*917c2899SVille Syrjälä intel_dp_phy_test(encoder); 1163*917c2899SVille Syrjälä /* just do the PHY test and nothing else */ 1164*917c2899SVille Syrjälä return INTEL_HOTPLUG_UNCHANGED; 1165*917c2899SVille Syrjälä } 1166*917c2899SVille Syrjälä 1167*917c2899SVille Syrjälä state = intel_encoder_hotplug(encoder, connector); 1168*917c2899SVille Syrjälä 1169*917c2899SVille Syrjälä drm_modeset_acquire_init(&ctx, 0); 1170*917c2899SVille Syrjälä 1171*917c2899SVille Syrjälä for (;;) { 1172*917c2899SVille Syrjälä ret = intel_dp_retrain_link(encoder, &ctx); 1173*917c2899SVille Syrjälä 1174*917c2899SVille Syrjälä if (ret == -EDEADLK) { 1175*917c2899SVille Syrjälä drm_modeset_backoff(&ctx); 1176*917c2899SVille Syrjälä continue; 1177*917c2899SVille Syrjälä } 1178*917c2899SVille Syrjälä 1179*917c2899SVille Syrjälä break; 1180*917c2899SVille Syrjälä } 1181*917c2899SVille Syrjälä 1182*917c2899SVille Syrjälä drm_modeset_drop_locks(&ctx); 1183*917c2899SVille Syrjälä drm_modeset_acquire_fini(&ctx); 1184*917c2899SVille Syrjälä drm_WARN(encoder->base.dev, ret, 1185*917c2899SVille Syrjälä "Acquiring modeset locks failed with %i\n", ret); 1186*917c2899SVille Syrjälä 1187*917c2899SVille Syrjälä /* 1188*917c2899SVille Syrjälä * Keeping it consistent with intel_ddi_hotplug() and 1189*917c2899SVille Syrjälä * intel_hdmi_hotplug(). 1190*917c2899SVille Syrjälä */ 1191*917c2899SVille Syrjälä if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 1192*917c2899SVille Syrjälä state = INTEL_HOTPLUG_RETRY; 1193*917c2899SVille Syrjälä 1194*917c2899SVille Syrjälä return state; 1195*917c2899SVille Syrjälä } 1196*917c2899SVille Syrjälä 1197*917c2899SVille Syrjälä static bool ibx_digital_port_connected(struct intel_encoder *encoder) 1198*917c2899SVille Syrjälä { 1199*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1200*917c2899SVille Syrjälä u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 1201*917c2899SVille Syrjälä 1202*917c2899SVille Syrjälä return intel_de_read(dev_priv, SDEISR) & bit; 1203*917c2899SVille Syrjälä } 1204*917c2899SVille Syrjälä 1205*917c2899SVille Syrjälä static bool g4x_digital_port_connected(struct intel_encoder *encoder) 1206*917c2899SVille Syrjälä { 1207*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1208*917c2899SVille Syrjälä u32 bit; 1209*917c2899SVille Syrjälä 1210*917c2899SVille Syrjälä switch (encoder->hpd_pin) { 1211*917c2899SVille Syrjälä case HPD_PORT_B: 1212*917c2899SVille Syrjälä bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 1213*917c2899SVille Syrjälä break; 1214*917c2899SVille Syrjälä case HPD_PORT_C: 1215*917c2899SVille Syrjälä bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 1216*917c2899SVille Syrjälä break; 1217*917c2899SVille Syrjälä case HPD_PORT_D: 1218*917c2899SVille Syrjälä bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 1219*917c2899SVille Syrjälä break; 1220*917c2899SVille Syrjälä default: 1221*917c2899SVille Syrjälä MISSING_CASE(encoder->hpd_pin); 1222*917c2899SVille Syrjälä return false; 1223*917c2899SVille Syrjälä } 1224*917c2899SVille Syrjälä 1225*917c2899SVille Syrjälä return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; 1226*917c2899SVille Syrjälä } 1227*917c2899SVille Syrjälä 1228*917c2899SVille Syrjälä static bool gm45_digital_port_connected(struct intel_encoder *encoder) 1229*917c2899SVille Syrjälä { 1230*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1231*917c2899SVille Syrjälä u32 bit; 1232*917c2899SVille Syrjälä 1233*917c2899SVille Syrjälä switch (encoder->hpd_pin) { 1234*917c2899SVille Syrjälä case HPD_PORT_B: 1235*917c2899SVille Syrjälä bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; 1236*917c2899SVille Syrjälä break; 1237*917c2899SVille Syrjälä case HPD_PORT_C: 1238*917c2899SVille Syrjälä bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; 1239*917c2899SVille Syrjälä break; 1240*917c2899SVille Syrjälä case HPD_PORT_D: 1241*917c2899SVille Syrjälä bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; 1242*917c2899SVille Syrjälä break; 1243*917c2899SVille Syrjälä default: 1244*917c2899SVille Syrjälä MISSING_CASE(encoder->hpd_pin); 1245*917c2899SVille Syrjälä return false; 1246*917c2899SVille Syrjälä } 1247*917c2899SVille Syrjälä 1248*917c2899SVille Syrjälä return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; 1249*917c2899SVille Syrjälä } 1250*917c2899SVille Syrjälä 1251*917c2899SVille Syrjälä static bool ilk_digital_port_connected(struct intel_encoder *encoder) 1252*917c2899SVille Syrjälä { 1253*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1254*917c2899SVille Syrjälä u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 1255*917c2899SVille Syrjälä 1256*917c2899SVille Syrjälä return intel_de_read(dev_priv, DEISR) & bit; 1257*917c2899SVille Syrjälä } 1258*917c2899SVille Syrjälä 1259*917c2899SVille Syrjälä static void intel_dp_encoder_destroy(struct drm_encoder *encoder) 1260*917c2899SVille Syrjälä { 1261*917c2899SVille Syrjälä intel_dp_encoder_flush_work(encoder); 1262*917c2899SVille Syrjälä 1263*917c2899SVille Syrjälä drm_encoder_cleanup(encoder); 1264*917c2899SVille Syrjälä kfree(enc_to_dig_port(to_intel_encoder(encoder))); 1265*917c2899SVille Syrjälä } 1266*917c2899SVille Syrjälä 1267*917c2899SVille Syrjälä enum pipe vlv_active_pipe(struct intel_dp *intel_dp) 1268*917c2899SVille Syrjälä { 1269*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1270*917c2899SVille Syrjälä struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1271*917c2899SVille Syrjälä enum pipe pipe; 1272*917c2899SVille Syrjälä 1273*917c2899SVille Syrjälä if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg, 1274*917c2899SVille Syrjälä encoder->port, &pipe)) 1275*917c2899SVille Syrjälä return pipe; 1276*917c2899SVille Syrjälä 1277*917c2899SVille Syrjälä return INVALID_PIPE; 1278*917c2899SVille Syrjälä } 1279*917c2899SVille Syrjälä 1280*917c2899SVille Syrjälä static void intel_dp_encoder_reset(struct drm_encoder *encoder) 1281*917c2899SVille Syrjälä { 1282*917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->dev); 1283*917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 1284*917c2899SVille Syrjälä 1285*917c2899SVille Syrjälä intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); 1286*917c2899SVille Syrjälä 1287*917c2899SVille Syrjälä intel_dp->reset_link_params = true; 1288*917c2899SVille Syrjälä 1289*917c2899SVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1290*917c2899SVille Syrjälä intel_wakeref_t wakeref; 1291*917c2899SVille Syrjälä 1292*917c2899SVille Syrjälä with_intel_pps_lock(intel_dp, wakeref) 1293*917c2899SVille Syrjälä intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp); 1294*917c2899SVille Syrjälä } 1295*917c2899SVille Syrjälä 1296*917c2899SVille Syrjälä intel_pps_encoder_reset(intel_dp); 1297*917c2899SVille Syrjälä } 1298*917c2899SVille Syrjälä 1299*917c2899SVille Syrjälä static const struct drm_encoder_funcs intel_dp_enc_funcs = { 1300*917c2899SVille Syrjälä .reset = intel_dp_encoder_reset, 1301*917c2899SVille Syrjälä .destroy = intel_dp_encoder_destroy, 1302*917c2899SVille Syrjälä }; 1303*917c2899SVille Syrjälä 1304*917c2899SVille Syrjälä bool intel_dp_init(struct drm_i915_private *dev_priv, 1305*917c2899SVille Syrjälä i915_reg_t output_reg, 1306*917c2899SVille Syrjälä enum port port) 1307*917c2899SVille Syrjälä { 1308*917c2899SVille Syrjälä struct intel_digital_port *dig_port; 1309*917c2899SVille Syrjälä struct intel_encoder *intel_encoder; 1310*917c2899SVille Syrjälä struct drm_encoder *encoder; 1311*917c2899SVille Syrjälä struct intel_connector *intel_connector; 1312*917c2899SVille Syrjälä 1313*917c2899SVille Syrjälä dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 1314*917c2899SVille Syrjälä if (!dig_port) 1315*917c2899SVille Syrjälä return false; 1316*917c2899SVille Syrjälä 1317*917c2899SVille Syrjälä intel_connector = intel_connector_alloc(); 1318*917c2899SVille Syrjälä if (!intel_connector) 1319*917c2899SVille Syrjälä goto err_connector_alloc; 1320*917c2899SVille Syrjälä 1321*917c2899SVille Syrjälä intel_encoder = &dig_port->base; 1322*917c2899SVille Syrjälä encoder = &intel_encoder->base; 1323*917c2899SVille Syrjälä 1324*917c2899SVille Syrjälä mutex_init(&dig_port->hdcp_mutex); 1325*917c2899SVille Syrjälä 1326*917c2899SVille Syrjälä if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 1327*917c2899SVille Syrjälä &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, 1328*917c2899SVille Syrjälä "DP %c", port_name(port))) 1329*917c2899SVille Syrjälä goto err_encoder_init; 1330*917c2899SVille Syrjälä 1331*917c2899SVille Syrjälä intel_encoder->hotplug = intel_dp_hotplug; 1332*917c2899SVille Syrjälä intel_encoder->compute_config = intel_dp_compute_config; 1333*917c2899SVille Syrjälä intel_encoder->get_hw_state = intel_dp_get_hw_state; 1334*917c2899SVille Syrjälä intel_encoder->get_config = intel_dp_get_config; 1335*917c2899SVille Syrjälä intel_encoder->sync_state = intel_dp_sync_state; 1336*917c2899SVille Syrjälä intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check; 1337*917c2899SVille Syrjälä intel_encoder->update_pipe = intel_panel_update_backlight; 1338*917c2899SVille Syrjälä intel_encoder->suspend = intel_dp_encoder_suspend; 1339*917c2899SVille Syrjälä intel_encoder->shutdown = intel_dp_encoder_shutdown; 1340*917c2899SVille Syrjälä if (IS_CHERRYVIEW(dev_priv)) { 1341*917c2899SVille Syrjälä intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; 1342*917c2899SVille Syrjälä intel_encoder->pre_enable = chv_pre_enable_dp; 1343*917c2899SVille Syrjälä intel_encoder->enable = vlv_enable_dp; 1344*917c2899SVille Syrjälä intel_encoder->disable = vlv_disable_dp; 1345*917c2899SVille Syrjälä intel_encoder->post_disable = chv_post_disable_dp; 1346*917c2899SVille Syrjälä intel_encoder->post_pll_disable = chv_dp_post_pll_disable; 1347*917c2899SVille Syrjälä } else if (IS_VALLEYVIEW(dev_priv)) { 1348*917c2899SVille Syrjälä intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 1349*917c2899SVille Syrjälä intel_encoder->pre_enable = vlv_pre_enable_dp; 1350*917c2899SVille Syrjälä intel_encoder->enable = vlv_enable_dp; 1351*917c2899SVille Syrjälä intel_encoder->disable = vlv_disable_dp; 1352*917c2899SVille Syrjälä intel_encoder->post_disable = vlv_post_disable_dp; 1353*917c2899SVille Syrjälä } else { 1354*917c2899SVille Syrjälä intel_encoder->pre_enable = g4x_pre_enable_dp; 1355*917c2899SVille Syrjälä intel_encoder->enable = g4x_enable_dp; 1356*917c2899SVille Syrjälä intel_encoder->disable = g4x_disable_dp; 1357*917c2899SVille Syrjälä intel_encoder->post_disable = g4x_post_disable_dp; 1358*917c2899SVille Syrjälä } 1359*917c2899SVille Syrjälä 1360*917c2899SVille Syrjälä if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || 1361*917c2899SVille Syrjälä (HAS_PCH_CPT(dev_priv) && port != PORT_A)) 1362*917c2899SVille Syrjälä dig_port->dp.set_link_train = cpt_set_link_train; 1363*917c2899SVille Syrjälä else 1364*917c2899SVille Syrjälä dig_port->dp.set_link_train = g4x_set_link_train; 1365*917c2899SVille Syrjälä 1366*917c2899SVille Syrjälä if (IS_CHERRYVIEW(dev_priv)) 1367*917c2899SVille Syrjälä dig_port->dp.set_signal_levels = chv_set_signal_levels; 1368*917c2899SVille Syrjälä else if (IS_VALLEYVIEW(dev_priv)) 1369*917c2899SVille Syrjälä dig_port->dp.set_signal_levels = vlv_set_signal_levels; 1370*917c2899SVille Syrjälä else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) 1371*917c2899SVille Syrjälä dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels; 1372*917c2899SVille Syrjälä else if (IS_GEN(dev_priv, 6) && port == PORT_A) 1373*917c2899SVille Syrjälä dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels; 1374*917c2899SVille Syrjälä else 1375*917c2899SVille Syrjälä dig_port->dp.set_signal_levels = g4x_set_signal_levels; 1376*917c2899SVille Syrjälä 1377*917c2899SVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || 1378*917c2899SVille Syrjälä (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) { 1379*917c2899SVille Syrjälä dig_port->dp.preemph_max = intel_dp_preemph_max_3; 1380*917c2899SVille Syrjälä dig_port->dp.voltage_max = intel_dp_voltage_max_3; 1381*917c2899SVille Syrjälä } else { 1382*917c2899SVille Syrjälä dig_port->dp.preemph_max = intel_dp_preemph_max_2; 1383*917c2899SVille Syrjälä dig_port->dp.voltage_max = intel_dp_voltage_max_2; 1384*917c2899SVille Syrjälä } 1385*917c2899SVille Syrjälä 1386*917c2899SVille Syrjälä dig_port->dp.output_reg = output_reg; 1387*917c2899SVille Syrjälä dig_port->max_lanes = 4; 1388*917c2899SVille Syrjälä 1389*917c2899SVille Syrjälä intel_encoder->type = INTEL_OUTPUT_DP; 1390*917c2899SVille Syrjälä intel_encoder->power_domain = intel_port_to_power_domain(port); 1391*917c2899SVille Syrjälä if (IS_CHERRYVIEW(dev_priv)) { 1392*917c2899SVille Syrjälä if (port == PORT_D) 1393*917c2899SVille Syrjälä intel_encoder->pipe_mask = BIT(PIPE_C); 1394*917c2899SVille Syrjälä else 1395*917c2899SVille Syrjälä intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 1396*917c2899SVille Syrjälä } else { 1397*917c2899SVille Syrjälä intel_encoder->pipe_mask = ~0; 1398*917c2899SVille Syrjälä } 1399*917c2899SVille Syrjälä intel_encoder->cloneable = 0; 1400*917c2899SVille Syrjälä intel_encoder->port = port; 1401*917c2899SVille Syrjälä intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 1402*917c2899SVille Syrjälä 1403*917c2899SVille Syrjälä dig_port->hpd_pulse = intel_dp_hpd_pulse; 1404*917c2899SVille Syrjälä 1405*917c2899SVille Syrjälä if (HAS_GMCH(dev_priv)) { 1406*917c2899SVille Syrjälä if (IS_GM45(dev_priv)) 1407*917c2899SVille Syrjälä dig_port->connected = gm45_digital_port_connected; 1408*917c2899SVille Syrjälä else 1409*917c2899SVille Syrjälä dig_port->connected = g4x_digital_port_connected; 1410*917c2899SVille Syrjälä } else { 1411*917c2899SVille Syrjälä if (port == PORT_A) 1412*917c2899SVille Syrjälä dig_port->connected = ilk_digital_port_connected; 1413*917c2899SVille Syrjälä else 1414*917c2899SVille Syrjälä dig_port->connected = ibx_digital_port_connected; 1415*917c2899SVille Syrjälä } 1416*917c2899SVille Syrjälä 1417*917c2899SVille Syrjälä if (port != PORT_A) 1418*917c2899SVille Syrjälä intel_infoframe_init(dig_port); 1419*917c2899SVille Syrjälä 1420*917c2899SVille Syrjälä dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 1421*917c2899SVille Syrjälä if (!intel_dp_init_connector(dig_port, intel_connector)) 1422*917c2899SVille Syrjälä goto err_init_connector; 1423*917c2899SVille Syrjälä 1424*917c2899SVille Syrjälä return true; 1425*917c2899SVille Syrjälä 1426*917c2899SVille Syrjälä err_init_connector: 1427*917c2899SVille Syrjälä drm_encoder_cleanup(encoder); 1428*917c2899SVille Syrjälä err_encoder_init: 1429*917c2899SVille Syrjälä kfree(intel_connector); 1430*917c2899SVille Syrjälä err_connector_alloc: 1431*917c2899SVille Syrjälä kfree(dig_port); 1432*917c2899SVille Syrjälä return false; 1433*917c2899SVille Syrjälä } 1434