1917c2899SVille Syrjälä // SPDX-License-Identifier: MIT 2917c2899SVille Syrjälä /* 3917c2899SVille Syrjälä * Copyright © 2020 Intel Corporation 4917c2899SVille Syrjälä * 5917c2899SVille Syrjälä * DisplayPort support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code). 6917c2899SVille Syrjälä */ 7917c2899SVille Syrjälä 8917c2899SVille Syrjälä #include "g4x_dp.h" 9917c2899SVille Syrjälä #include "intel_audio.h" 10*6cc42fbeSJani Nikula #include "intel_backlight.h" 11917c2899SVille Syrjälä #include "intel_connector.h" 127785ae0bSVille Syrjälä #include "intel_de.h" 13917c2899SVille Syrjälä #include "intel_display_types.h" 14917c2899SVille Syrjälä #include "intel_dp.h" 15917c2899SVille Syrjälä #include "intel_dp_link_training.h" 16917c2899SVille Syrjälä #include "intel_dpio_phy.h" 17917c2899SVille Syrjälä #include "intel_fifo_underrun.h" 18917c2899SVille Syrjälä #include "intel_hdmi.h" 19917c2899SVille Syrjälä #include "intel_hotplug.h" 20917c2899SVille Syrjälä #include "intel_pps.h" 21917c2899SVille Syrjälä #include "intel_sideband.h" 22917c2899SVille Syrjälä 23917c2899SVille Syrjälä struct dp_link_dpll { 24917c2899SVille Syrjälä int clock; 25917c2899SVille Syrjälä struct dpll dpll; 26917c2899SVille Syrjälä }; 27917c2899SVille Syrjälä 28917c2899SVille Syrjälä static const struct dp_link_dpll g4x_dpll[] = { 29917c2899SVille Syrjälä { 162000, 30917c2899SVille Syrjälä { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 31917c2899SVille Syrjälä { 270000, 32917c2899SVille Syrjälä { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 33917c2899SVille Syrjälä }; 34917c2899SVille Syrjälä 35917c2899SVille Syrjälä static const struct dp_link_dpll pch_dpll[] = { 36917c2899SVille Syrjälä { 162000, 37917c2899SVille Syrjälä { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 38917c2899SVille Syrjälä { 270000, 39917c2899SVille Syrjälä { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 40917c2899SVille Syrjälä }; 41917c2899SVille Syrjälä 42917c2899SVille Syrjälä static const struct dp_link_dpll vlv_dpll[] = { 43917c2899SVille Syrjälä { 162000, 44917c2899SVille Syrjälä { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 45917c2899SVille Syrjälä { 270000, 46917c2899SVille Syrjälä { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 47917c2899SVille Syrjälä }; 48917c2899SVille Syrjälä 49917c2899SVille Syrjälä /* 50917c2899SVille Syrjälä * CHV supports eDP 1.4 that have more link rates. 51917c2899SVille Syrjälä * Below only provides the fixed rate but exclude variable rate. 52917c2899SVille Syrjälä */ 53917c2899SVille Syrjälä static const struct dp_link_dpll chv_dpll[] = { 54917c2899SVille Syrjälä /* 55917c2899SVille Syrjälä * CHV requires to program fractional division for m2. 56917c2899SVille Syrjälä * m2 is stored in fixed point format using formula below 57917c2899SVille Syrjälä * (m2_int << 22) | m2_fraction 58917c2899SVille Syrjälä */ 59917c2899SVille Syrjälä { 162000, /* m2_int = 32, m2_fraction = 1677722 */ 60917c2899SVille Syrjälä { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, 61917c2899SVille Syrjälä { 270000, /* m2_int = 27, m2_fraction = 0 */ 62917c2899SVille Syrjälä { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, 63917c2899SVille Syrjälä }; 64917c2899SVille Syrjälä 65917c2899SVille Syrjälä const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) 66917c2899SVille Syrjälä { 67917c2899SVille Syrjälä return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll; 68917c2899SVille Syrjälä } 69917c2899SVille Syrjälä 70053ffdd1SVille Syrjälä void g4x_dp_set_clock(struct intel_encoder *encoder, 71917c2899SVille Syrjälä struct intel_crtc_state *pipe_config) 72917c2899SVille Syrjälä { 73917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 74917c2899SVille Syrjälä const struct dp_link_dpll *divisor = NULL; 75917c2899SVille Syrjälä int i, count = 0; 76917c2899SVille Syrjälä 77917c2899SVille Syrjälä if (IS_G4X(dev_priv)) { 78917c2899SVille Syrjälä divisor = g4x_dpll; 79917c2899SVille Syrjälä count = ARRAY_SIZE(g4x_dpll); 80917c2899SVille Syrjälä } else if (HAS_PCH_SPLIT(dev_priv)) { 81917c2899SVille Syrjälä divisor = pch_dpll; 82917c2899SVille Syrjälä count = ARRAY_SIZE(pch_dpll); 83917c2899SVille Syrjälä } else if (IS_CHERRYVIEW(dev_priv)) { 84917c2899SVille Syrjälä divisor = chv_dpll; 85917c2899SVille Syrjälä count = ARRAY_SIZE(chv_dpll); 86917c2899SVille Syrjälä } else if (IS_VALLEYVIEW(dev_priv)) { 87917c2899SVille Syrjälä divisor = vlv_dpll; 88917c2899SVille Syrjälä count = ARRAY_SIZE(vlv_dpll); 89917c2899SVille Syrjälä } 90917c2899SVille Syrjälä 91917c2899SVille Syrjälä if (divisor && count) { 92917c2899SVille Syrjälä for (i = 0; i < count; i++) { 93917c2899SVille Syrjälä if (pipe_config->port_clock == divisor[i].clock) { 94917c2899SVille Syrjälä pipe_config->dpll = divisor[i].dpll; 95917c2899SVille Syrjälä pipe_config->clock_set = true; 96917c2899SVille Syrjälä break; 97917c2899SVille Syrjälä } 98917c2899SVille Syrjälä } 99917c2899SVille Syrjälä } 100917c2899SVille Syrjälä } 101917c2899SVille Syrjälä 102917c2899SVille Syrjälä static void intel_dp_prepare(struct intel_encoder *encoder, 103917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config) 104917c2899SVille Syrjälä { 105917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 106917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 107917c2899SVille Syrjälä enum port port = encoder->port; 108917c2899SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 109917c2899SVille Syrjälä const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 110917c2899SVille Syrjälä 111917c2899SVille Syrjälä intel_dp_set_link_params(intel_dp, 112917c2899SVille Syrjälä pipe_config->port_clock, 113917c2899SVille Syrjälä pipe_config->lane_count); 114917c2899SVille Syrjälä 115917c2899SVille Syrjälä /* 116917c2899SVille Syrjälä * There are four kinds of DP registers: 117917c2899SVille Syrjälä * IBX PCH 118917c2899SVille Syrjälä * SNB CPU 119917c2899SVille Syrjälä * IVB CPU 120917c2899SVille Syrjälä * CPT PCH 121917c2899SVille Syrjälä * 122917c2899SVille Syrjälä * IBX PCH and CPU are the same for almost everything, 123917c2899SVille Syrjälä * except that the CPU DP PLL is configured in this 124917c2899SVille Syrjälä * register 125917c2899SVille Syrjälä * 126917c2899SVille Syrjälä * CPT PCH is quite different, having many bits moved 127917c2899SVille Syrjälä * to the TRANS_DP_CTL register instead. That 128917c2899SVille Syrjälä * configuration happens (oddly) in ilk_pch_enable 129917c2899SVille Syrjälä */ 130917c2899SVille Syrjälä 131917c2899SVille Syrjälä /* Preserve the BIOS-computed detected bit. This is 132917c2899SVille Syrjälä * supposed to be read-only. 133917c2899SVille Syrjälä */ 134917c2899SVille Syrjälä intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; 135917c2899SVille Syrjälä 136917c2899SVille Syrjälä /* Handle DP bits in common between all three register formats */ 137917c2899SVille Syrjälä intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 138917c2899SVille Syrjälä intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); 139917c2899SVille Syrjälä 140917c2899SVille Syrjälä /* Split out the IBX/CPU vs CPT settings */ 141917c2899SVille Syrjälä 142917c2899SVille Syrjälä if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { 143917c2899SVille Syrjälä if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 144917c2899SVille Syrjälä intel_dp->DP |= DP_SYNC_HS_HIGH; 145917c2899SVille Syrjälä if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 146917c2899SVille Syrjälä intel_dp->DP |= DP_SYNC_VS_HIGH; 147917c2899SVille Syrjälä intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 148917c2899SVille Syrjälä 149917c2899SVille Syrjälä if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 150917c2899SVille Syrjälä intel_dp->DP |= DP_ENHANCED_FRAMING; 151917c2899SVille Syrjälä 152917c2899SVille Syrjälä intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe); 153917c2899SVille Syrjälä } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { 154917c2899SVille Syrjälä u32 trans_dp; 155917c2899SVille Syrjälä 156917c2899SVille Syrjälä intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 157917c2899SVille Syrjälä 158917c2899SVille Syrjälä trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe)); 159917c2899SVille Syrjälä if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 160917c2899SVille Syrjälä trans_dp |= TRANS_DP_ENH_FRAMING; 161917c2899SVille Syrjälä else 162917c2899SVille Syrjälä trans_dp &= ~TRANS_DP_ENH_FRAMING; 163917c2899SVille Syrjälä intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp); 164917c2899SVille Syrjälä } else { 165917c2899SVille Syrjälä if (IS_G4X(dev_priv) && pipe_config->limited_color_range) 166917c2899SVille Syrjälä intel_dp->DP |= DP_COLOR_RANGE_16_235; 167917c2899SVille Syrjälä 168917c2899SVille Syrjälä if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 169917c2899SVille Syrjälä intel_dp->DP |= DP_SYNC_HS_HIGH; 170917c2899SVille Syrjälä if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 171917c2899SVille Syrjälä intel_dp->DP |= DP_SYNC_VS_HIGH; 172917c2899SVille Syrjälä intel_dp->DP |= DP_LINK_TRAIN_OFF; 173917c2899SVille Syrjälä 174917c2899SVille Syrjälä if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 175917c2899SVille Syrjälä intel_dp->DP |= DP_ENHANCED_FRAMING; 176917c2899SVille Syrjälä 177917c2899SVille Syrjälä if (IS_CHERRYVIEW(dev_priv)) 178917c2899SVille Syrjälä intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe); 179917c2899SVille Syrjälä else 180917c2899SVille Syrjälä intel_dp->DP |= DP_PIPE_SEL(crtc->pipe); 181917c2899SVille Syrjälä } 182917c2899SVille Syrjälä } 183917c2899SVille Syrjälä 184917c2899SVille Syrjälä static void assert_dp_port(struct intel_dp *intel_dp, bool state) 185917c2899SVille Syrjälä { 186917c2899SVille Syrjälä struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 187917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 188917c2899SVille Syrjälä bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN; 189917c2899SVille Syrjälä 190917c2899SVille Syrjälä I915_STATE_WARN(cur_state != state, 191917c2899SVille Syrjälä "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n", 192917c2899SVille Syrjälä dig_port->base.base.base.id, dig_port->base.base.name, 193917c2899SVille Syrjälä onoff(state), onoff(cur_state)); 194917c2899SVille Syrjälä } 195917c2899SVille Syrjälä #define assert_dp_port_disabled(d) assert_dp_port((d), false) 196917c2899SVille Syrjälä 197917c2899SVille Syrjälä static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) 198917c2899SVille Syrjälä { 199917c2899SVille Syrjälä bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE; 200917c2899SVille Syrjälä 201917c2899SVille Syrjälä I915_STATE_WARN(cur_state != state, 202917c2899SVille Syrjälä "eDP PLL state assertion failure (expected %s, current %s)\n", 203917c2899SVille Syrjälä onoff(state), onoff(cur_state)); 204917c2899SVille Syrjälä } 205917c2899SVille Syrjälä #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) 206917c2899SVille Syrjälä #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) 207917c2899SVille Syrjälä 208917c2899SVille Syrjälä static void ilk_edp_pll_on(struct intel_dp *intel_dp, 209917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config) 210917c2899SVille Syrjälä { 211917c2899SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 212917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 213917c2899SVille Syrjälä 214917c2899SVille Syrjälä assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); 215917c2899SVille Syrjälä assert_dp_port_disabled(intel_dp); 216917c2899SVille Syrjälä assert_edp_pll_disabled(dev_priv); 217917c2899SVille Syrjälä 218917c2899SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n", 219917c2899SVille Syrjälä pipe_config->port_clock); 220917c2899SVille Syrjälä 221917c2899SVille Syrjälä intel_dp->DP &= ~DP_PLL_FREQ_MASK; 222917c2899SVille Syrjälä 223917c2899SVille Syrjälä if (pipe_config->port_clock == 162000) 224917c2899SVille Syrjälä intel_dp->DP |= DP_PLL_FREQ_162MHZ; 225917c2899SVille Syrjälä else 226917c2899SVille Syrjälä intel_dp->DP |= DP_PLL_FREQ_270MHZ; 227917c2899SVille Syrjälä 228917c2899SVille Syrjälä intel_de_write(dev_priv, DP_A, intel_dp->DP); 229917c2899SVille Syrjälä intel_de_posting_read(dev_priv, DP_A); 230917c2899SVille Syrjälä udelay(500); 231917c2899SVille Syrjälä 232917c2899SVille Syrjälä /* 233917c2899SVille Syrjälä * [DevILK] Work around required when enabling DP PLL 234917c2899SVille Syrjälä * while a pipe is enabled going to FDI: 235917c2899SVille Syrjälä * 1. Wait for the start of vertical blank on the enabled pipe going to FDI 236917c2899SVille Syrjälä * 2. Program DP PLL enable 237917c2899SVille Syrjälä */ 238d47d29a6SMatt Roper if (IS_IRONLAKE(dev_priv)) 239917c2899SVille Syrjälä intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); 240917c2899SVille Syrjälä 241917c2899SVille Syrjälä intel_dp->DP |= DP_PLL_ENABLE; 242917c2899SVille Syrjälä 243917c2899SVille Syrjälä intel_de_write(dev_priv, DP_A, intel_dp->DP); 244917c2899SVille Syrjälä intel_de_posting_read(dev_priv, DP_A); 245917c2899SVille Syrjälä udelay(200); 246917c2899SVille Syrjälä } 247917c2899SVille Syrjälä 248917c2899SVille Syrjälä static void ilk_edp_pll_off(struct intel_dp *intel_dp, 249917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state) 250917c2899SVille Syrjälä { 251917c2899SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 252917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 253917c2899SVille Syrjälä 254917c2899SVille Syrjälä assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder); 255917c2899SVille Syrjälä assert_dp_port_disabled(intel_dp); 256917c2899SVille Syrjälä assert_edp_pll_enabled(dev_priv); 257917c2899SVille Syrjälä 258917c2899SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n"); 259917c2899SVille Syrjälä 260917c2899SVille Syrjälä intel_dp->DP &= ~DP_PLL_ENABLE; 261917c2899SVille Syrjälä 262917c2899SVille Syrjälä intel_de_write(dev_priv, DP_A, intel_dp->DP); 263917c2899SVille Syrjälä intel_de_posting_read(dev_priv, DP_A); 264917c2899SVille Syrjälä udelay(200); 265917c2899SVille Syrjälä } 266917c2899SVille Syrjälä 267917c2899SVille Syrjälä static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv, 268917c2899SVille Syrjälä enum port port, enum pipe *pipe) 269917c2899SVille Syrjälä { 270917c2899SVille Syrjälä enum pipe p; 271917c2899SVille Syrjälä 272917c2899SVille Syrjälä for_each_pipe(dev_priv, p) { 273917c2899SVille Syrjälä u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p)); 274917c2899SVille Syrjälä 275917c2899SVille Syrjälä if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) { 276917c2899SVille Syrjälä *pipe = p; 277917c2899SVille Syrjälä return true; 278917c2899SVille Syrjälä } 279917c2899SVille Syrjälä } 280917c2899SVille Syrjälä 281917c2899SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n", 282917c2899SVille Syrjälä port_name(port)); 283917c2899SVille Syrjälä 284917c2899SVille Syrjälä /* must initialize pipe to something for the asserts */ 285917c2899SVille Syrjälä *pipe = PIPE_A; 286917c2899SVille Syrjälä 287917c2899SVille Syrjälä return false; 288917c2899SVille Syrjälä } 289917c2899SVille Syrjälä 290053ffdd1SVille Syrjälä bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv, 291917c2899SVille Syrjälä i915_reg_t dp_reg, enum port port, 292917c2899SVille Syrjälä enum pipe *pipe) 293917c2899SVille Syrjälä { 294917c2899SVille Syrjälä bool ret; 295917c2899SVille Syrjälä u32 val; 296917c2899SVille Syrjälä 297917c2899SVille Syrjälä val = intel_de_read(dev_priv, dp_reg); 298917c2899SVille Syrjälä 299917c2899SVille Syrjälä ret = val & DP_PORT_EN; 300917c2899SVille Syrjälä 301917c2899SVille Syrjälä /* asserts want to know the pipe even if the port is disabled */ 302917c2899SVille Syrjälä if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) 303917c2899SVille Syrjälä *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB; 304917c2899SVille Syrjälä else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) 305917c2899SVille Syrjälä ret &= cpt_dp_port_selected(dev_priv, port, pipe); 306917c2899SVille Syrjälä else if (IS_CHERRYVIEW(dev_priv)) 307917c2899SVille Syrjälä *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV; 308917c2899SVille Syrjälä else 309917c2899SVille Syrjälä *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT; 310917c2899SVille Syrjälä 311917c2899SVille Syrjälä return ret; 312917c2899SVille Syrjälä } 313917c2899SVille Syrjälä 314917c2899SVille Syrjälä static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 315917c2899SVille Syrjälä enum pipe *pipe) 316917c2899SVille Syrjälä { 317917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 318917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 319917c2899SVille Syrjälä intel_wakeref_t wakeref; 320917c2899SVille Syrjälä bool ret; 321917c2899SVille Syrjälä 322917c2899SVille Syrjälä wakeref = intel_display_power_get_if_enabled(dev_priv, 323917c2899SVille Syrjälä encoder->power_domain); 324917c2899SVille Syrjälä if (!wakeref) 325917c2899SVille Syrjälä return false; 326917c2899SVille Syrjälä 327053ffdd1SVille Syrjälä ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg, 328917c2899SVille Syrjälä encoder->port, pipe); 329917c2899SVille Syrjälä 330917c2899SVille Syrjälä intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 331917c2899SVille Syrjälä 332917c2899SVille Syrjälä return ret; 333917c2899SVille Syrjälä } 334917c2899SVille Syrjälä 335917c2899SVille Syrjälä static void intel_dp_get_config(struct intel_encoder *encoder, 336917c2899SVille Syrjälä struct intel_crtc_state *pipe_config) 337917c2899SVille Syrjälä { 338917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 339917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 340917c2899SVille Syrjälä u32 tmp, flags = 0; 341917c2899SVille Syrjälä enum port port = encoder->port; 342917c2899SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 343917c2899SVille Syrjälä 344917c2899SVille Syrjälä if (encoder->type == INTEL_OUTPUT_EDP) 345917c2899SVille Syrjälä pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 346917c2899SVille Syrjälä else 347917c2899SVille Syrjälä pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 348917c2899SVille Syrjälä 349917c2899SVille Syrjälä tmp = intel_de_read(dev_priv, intel_dp->output_reg); 350917c2899SVille Syrjälä 351917c2899SVille Syrjälä pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; 352917c2899SVille Syrjälä 353917c2899SVille Syrjälä if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { 354917c2899SVille Syrjälä u32 trans_dp = intel_de_read(dev_priv, 355917c2899SVille Syrjälä TRANS_DP_CTL(crtc->pipe)); 356917c2899SVille Syrjälä 357917c2899SVille Syrjälä if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) 358917c2899SVille Syrjälä flags |= DRM_MODE_FLAG_PHSYNC; 359917c2899SVille Syrjälä else 360917c2899SVille Syrjälä flags |= DRM_MODE_FLAG_NHSYNC; 361917c2899SVille Syrjälä 362917c2899SVille Syrjälä if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) 363917c2899SVille Syrjälä flags |= DRM_MODE_FLAG_PVSYNC; 364917c2899SVille Syrjälä else 365917c2899SVille Syrjälä flags |= DRM_MODE_FLAG_NVSYNC; 366917c2899SVille Syrjälä } else { 367917c2899SVille Syrjälä if (tmp & DP_SYNC_HS_HIGH) 368917c2899SVille Syrjälä flags |= DRM_MODE_FLAG_PHSYNC; 369917c2899SVille Syrjälä else 370917c2899SVille Syrjälä flags |= DRM_MODE_FLAG_NHSYNC; 371917c2899SVille Syrjälä 372917c2899SVille Syrjälä if (tmp & DP_SYNC_VS_HIGH) 373917c2899SVille Syrjälä flags |= DRM_MODE_FLAG_PVSYNC; 374917c2899SVille Syrjälä else 375917c2899SVille Syrjälä flags |= DRM_MODE_FLAG_NVSYNC; 376917c2899SVille Syrjälä } 377917c2899SVille Syrjälä 378917c2899SVille Syrjälä pipe_config->hw.adjusted_mode.flags |= flags; 379917c2899SVille Syrjälä 380917c2899SVille Syrjälä if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) 381917c2899SVille Syrjälä pipe_config->limited_color_range = true; 382917c2899SVille Syrjälä 383917c2899SVille Syrjälä pipe_config->lane_count = 384917c2899SVille Syrjälä ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; 385917c2899SVille Syrjälä 386917c2899SVille Syrjälä intel_dp_get_m_n(crtc, pipe_config); 387917c2899SVille Syrjälä 388917c2899SVille Syrjälä if (port == PORT_A) { 389917c2899SVille Syrjälä if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) 390917c2899SVille Syrjälä pipe_config->port_clock = 162000; 391917c2899SVille Syrjälä else 392917c2899SVille Syrjälä pipe_config->port_clock = 270000; 393917c2899SVille Syrjälä } 394917c2899SVille Syrjälä 395917c2899SVille Syrjälä pipe_config->hw.adjusted_mode.crtc_clock = 396917c2899SVille Syrjälä intel_dotclock_calculate(pipe_config->port_clock, 397917c2899SVille Syrjälä &pipe_config->dp_m_n); 398917c2899SVille Syrjälä 399917c2899SVille Syrjälä if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp && 400917c2899SVille Syrjälä pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 401917c2899SVille Syrjälä /* 402917c2899SVille Syrjälä * This is a big fat ugly hack. 403917c2899SVille Syrjälä * 404917c2899SVille Syrjälä * Some machines in UEFI boot mode provide us a VBT that has 18 405917c2899SVille Syrjälä * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 406917c2899SVille Syrjälä * unknown we fail to light up. Yet the same BIOS boots up with 407917c2899SVille Syrjälä * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 408917c2899SVille Syrjälä * max, not what it tells us to use. 409917c2899SVille Syrjälä * 410917c2899SVille Syrjälä * Note: This will still be broken if the eDP panel is not lit 411917c2899SVille Syrjälä * up by the BIOS, and thus we can't get the mode at module 412917c2899SVille Syrjälä * load. 413917c2899SVille Syrjälä */ 414917c2899SVille Syrjälä drm_dbg_kms(&dev_priv->drm, 415917c2899SVille Syrjälä "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 416917c2899SVille Syrjälä pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 417917c2899SVille Syrjälä dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 418917c2899SVille Syrjälä } 419917c2899SVille Syrjälä } 420917c2899SVille Syrjälä 421917c2899SVille Syrjälä static void 422917c2899SVille Syrjälä intel_dp_link_down(struct intel_encoder *encoder, 423917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state) 424917c2899SVille Syrjälä { 425917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 426917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 427917c2899SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 428917c2899SVille Syrjälä enum port port = encoder->port; 429917c2899SVille Syrjälä u32 DP = intel_dp->DP; 430917c2899SVille Syrjälä 431917c2899SVille Syrjälä if (drm_WARN_ON(&dev_priv->drm, 432917c2899SVille Syrjälä (intel_de_read(dev_priv, intel_dp->output_reg) & 433917c2899SVille Syrjälä DP_PORT_EN) == 0)) 434917c2899SVille Syrjälä return; 435917c2899SVille Syrjälä 436917c2899SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "\n"); 437917c2899SVille Syrjälä 438917c2899SVille Syrjälä if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || 439917c2899SVille Syrjälä (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { 440917c2899SVille Syrjälä DP &= ~DP_LINK_TRAIN_MASK_CPT; 441917c2899SVille Syrjälä DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; 442917c2899SVille Syrjälä } else { 443917c2899SVille Syrjälä DP &= ~DP_LINK_TRAIN_MASK; 444917c2899SVille Syrjälä DP |= DP_LINK_TRAIN_PAT_IDLE; 445917c2899SVille Syrjälä } 446917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, DP); 447917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 448917c2899SVille Syrjälä 449917c2899SVille Syrjälä DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 450917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, DP); 451917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 452917c2899SVille Syrjälä 453917c2899SVille Syrjälä /* 454917c2899SVille Syrjälä * HW workaround for IBX, we need to move the port 455917c2899SVille Syrjälä * to transcoder A after disabling it to allow the 456917c2899SVille Syrjälä * matching HDMI port to be enabled on transcoder A. 457917c2899SVille Syrjälä */ 458917c2899SVille Syrjälä if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { 459917c2899SVille Syrjälä /* 460917c2899SVille Syrjälä * We get CPU/PCH FIFO underruns on the other pipe when 461917c2899SVille Syrjälä * doing the workaround. Sweep them under the rug. 462917c2899SVille Syrjälä */ 463917c2899SVille Syrjälä intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 464917c2899SVille Syrjälä intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 465917c2899SVille Syrjälä 466917c2899SVille Syrjälä /* always enable with pattern 1 (as per spec) */ 467917c2899SVille Syrjälä DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK); 468917c2899SVille Syrjälä DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | 469917c2899SVille Syrjälä DP_LINK_TRAIN_PAT_1; 470917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, DP); 471917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 472917c2899SVille Syrjälä 473917c2899SVille Syrjälä DP &= ~DP_PORT_EN; 474917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, DP); 475917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 476917c2899SVille Syrjälä 477917c2899SVille Syrjälä intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 478917c2899SVille Syrjälä intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 479917c2899SVille Syrjälä intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 480917c2899SVille Syrjälä } 481917c2899SVille Syrjälä 482917c2899SVille Syrjälä msleep(intel_dp->pps.panel_power_down_delay); 483917c2899SVille Syrjälä 484917c2899SVille Syrjälä intel_dp->DP = DP; 485917c2899SVille Syrjälä 486917c2899SVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 487917c2899SVille Syrjälä intel_wakeref_t wakeref; 488917c2899SVille Syrjälä 489917c2899SVille Syrjälä with_intel_pps_lock(intel_dp, wakeref) 490917c2899SVille Syrjälä intel_dp->pps.active_pipe = INVALID_PIPE; 491917c2899SVille Syrjälä } 492917c2899SVille Syrjälä } 493917c2899SVille Syrjälä 494917c2899SVille Syrjälä static void intel_disable_dp(struct intel_atomic_state *state, 495917c2899SVille Syrjälä struct intel_encoder *encoder, 496917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state, 497917c2899SVille Syrjälä const struct drm_connector_state *old_conn_state) 498917c2899SVille Syrjälä { 499917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 500917c2899SVille Syrjälä 501917c2899SVille Syrjälä intel_dp->link_trained = false; 502917c2899SVille Syrjälä 503917c2899SVille Syrjälä if (old_crtc_state->has_audio) 504917c2899SVille Syrjälä intel_audio_codec_disable(encoder, 505917c2899SVille Syrjälä old_crtc_state, old_conn_state); 506917c2899SVille Syrjälä 507917c2899SVille Syrjälä /* 508917c2899SVille Syrjälä * Make sure the panel is off before trying to change the mode. 509917c2899SVille Syrjälä * But also ensure that we have vdd while we switch off the panel. 510917c2899SVille Syrjälä */ 511917c2899SVille Syrjälä intel_pps_vdd_on(intel_dp); 512917c2899SVille Syrjälä intel_edp_backlight_off(old_conn_state); 513917c2899SVille Syrjälä intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 514917c2899SVille Syrjälä intel_pps_off(intel_dp); 515917c2899SVille Syrjälä } 516917c2899SVille Syrjälä 517917c2899SVille Syrjälä static void g4x_disable_dp(struct intel_atomic_state *state, 518917c2899SVille Syrjälä struct intel_encoder *encoder, 519917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state, 520917c2899SVille Syrjälä const struct drm_connector_state *old_conn_state) 521917c2899SVille Syrjälä { 522917c2899SVille Syrjälä intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); 523917c2899SVille Syrjälä } 524917c2899SVille Syrjälä 525917c2899SVille Syrjälä static void vlv_disable_dp(struct intel_atomic_state *state, 526917c2899SVille Syrjälä struct intel_encoder *encoder, 527917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state, 528917c2899SVille Syrjälä const struct drm_connector_state *old_conn_state) 529917c2899SVille Syrjälä { 530917c2899SVille Syrjälä intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); 531917c2899SVille Syrjälä } 532917c2899SVille Syrjälä 533917c2899SVille Syrjälä static void g4x_post_disable_dp(struct intel_atomic_state *state, 534917c2899SVille Syrjälä struct intel_encoder *encoder, 535917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state, 536917c2899SVille Syrjälä const struct drm_connector_state *old_conn_state) 537917c2899SVille Syrjälä { 538917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 539917c2899SVille Syrjälä enum port port = encoder->port; 540917c2899SVille Syrjälä 541917c2899SVille Syrjälä /* 542917c2899SVille Syrjälä * Bspec does not list a specific disable sequence for g4x DP. 543917c2899SVille Syrjälä * Follow the ilk+ sequence (disable pipe before the port) for 544917c2899SVille Syrjälä * g4x DP as it does not suffer from underruns like the normal 545917c2899SVille Syrjälä * g4x modeset sequence (disable pipe after the port). 546917c2899SVille Syrjälä */ 547917c2899SVille Syrjälä intel_dp_link_down(encoder, old_crtc_state); 548917c2899SVille Syrjälä 549917c2899SVille Syrjälä /* Only ilk+ has port A */ 550917c2899SVille Syrjälä if (port == PORT_A) 551917c2899SVille Syrjälä ilk_edp_pll_off(intel_dp, old_crtc_state); 552917c2899SVille Syrjälä } 553917c2899SVille Syrjälä 554917c2899SVille Syrjälä static void vlv_post_disable_dp(struct intel_atomic_state *state, 555917c2899SVille Syrjälä struct intel_encoder *encoder, 556917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state, 557917c2899SVille Syrjälä const struct drm_connector_state *old_conn_state) 558917c2899SVille Syrjälä { 559917c2899SVille Syrjälä intel_dp_link_down(encoder, old_crtc_state); 560917c2899SVille Syrjälä } 561917c2899SVille Syrjälä 562917c2899SVille Syrjälä static void chv_post_disable_dp(struct intel_atomic_state *state, 563917c2899SVille Syrjälä struct intel_encoder *encoder, 564917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state, 565917c2899SVille Syrjälä const struct drm_connector_state *old_conn_state) 566917c2899SVille Syrjälä { 567917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 568917c2899SVille Syrjälä 569917c2899SVille Syrjälä intel_dp_link_down(encoder, old_crtc_state); 570917c2899SVille Syrjälä 571917c2899SVille Syrjälä vlv_dpio_get(dev_priv); 572917c2899SVille Syrjälä 573917c2899SVille Syrjälä /* Assert data lane reset */ 574917c2899SVille Syrjälä chv_data_lane_soft_reset(encoder, old_crtc_state, true); 575917c2899SVille Syrjälä 576917c2899SVille Syrjälä vlv_dpio_put(dev_priv); 577917c2899SVille Syrjälä } 578917c2899SVille Syrjälä 579917c2899SVille Syrjälä static void 580917c2899SVille Syrjälä cpt_set_link_train(struct intel_dp *intel_dp, 581917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state, 582917c2899SVille Syrjälä u8 dp_train_pat) 583917c2899SVille Syrjälä { 584917c2899SVille Syrjälä struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 585917c2899SVille Syrjälä u32 *DP = &intel_dp->DP; 586917c2899SVille Syrjälä 587917c2899SVille Syrjälä *DP &= ~DP_LINK_TRAIN_MASK_CPT; 588917c2899SVille Syrjälä 589917c2899SVille Syrjälä switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 590917c2899SVille Syrjälä case DP_TRAINING_PATTERN_DISABLE: 591917c2899SVille Syrjälä *DP |= DP_LINK_TRAIN_OFF_CPT; 592917c2899SVille Syrjälä break; 593917c2899SVille Syrjälä case DP_TRAINING_PATTERN_1: 594917c2899SVille Syrjälä *DP |= DP_LINK_TRAIN_PAT_1_CPT; 595917c2899SVille Syrjälä break; 596917c2899SVille Syrjälä case DP_TRAINING_PATTERN_2: 597917c2899SVille Syrjälä *DP |= DP_LINK_TRAIN_PAT_2_CPT; 598917c2899SVille Syrjälä break; 599917c2899SVille Syrjälä default: 600917c2899SVille Syrjälä MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat)); 601917c2899SVille Syrjälä return; 602917c2899SVille Syrjälä } 603917c2899SVille Syrjälä 604917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 605917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 606917c2899SVille Syrjälä } 607917c2899SVille Syrjälä 608917c2899SVille Syrjälä static void 609917c2899SVille Syrjälä g4x_set_link_train(struct intel_dp *intel_dp, 610917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state, 611917c2899SVille Syrjälä u8 dp_train_pat) 612917c2899SVille Syrjälä { 613917c2899SVille Syrjälä struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 614917c2899SVille Syrjälä u32 *DP = &intel_dp->DP; 615917c2899SVille Syrjälä 616917c2899SVille Syrjälä *DP &= ~DP_LINK_TRAIN_MASK; 617917c2899SVille Syrjälä 618917c2899SVille Syrjälä switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 619917c2899SVille Syrjälä case DP_TRAINING_PATTERN_DISABLE: 620917c2899SVille Syrjälä *DP |= DP_LINK_TRAIN_OFF; 621917c2899SVille Syrjälä break; 622917c2899SVille Syrjälä case DP_TRAINING_PATTERN_1: 623917c2899SVille Syrjälä *DP |= DP_LINK_TRAIN_PAT_1; 624917c2899SVille Syrjälä break; 625917c2899SVille Syrjälä case DP_TRAINING_PATTERN_2: 626917c2899SVille Syrjälä *DP |= DP_LINK_TRAIN_PAT_2; 627917c2899SVille Syrjälä break; 628917c2899SVille Syrjälä default: 629917c2899SVille Syrjälä MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat)); 630917c2899SVille Syrjälä return; 631917c2899SVille Syrjälä } 632917c2899SVille Syrjälä 633917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 634917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 635917c2899SVille Syrjälä } 636917c2899SVille Syrjälä 637917c2899SVille Syrjälä static void intel_dp_enable_port(struct intel_dp *intel_dp, 638917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state) 639917c2899SVille Syrjälä { 640917c2899SVille Syrjälä struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 641917c2899SVille Syrjälä 642917c2899SVille Syrjälä /* enable with pattern 1 (as per spec) */ 643917c2899SVille Syrjälä 644917c2899SVille Syrjälä intel_dp_program_link_training_pattern(intel_dp, crtc_state, 645917c2899SVille Syrjälä DP_TRAINING_PATTERN_1); 646917c2899SVille Syrjälä 647917c2899SVille Syrjälä /* 648917c2899SVille Syrjälä * Magic for VLV/CHV. We _must_ first set up the register 649917c2899SVille Syrjälä * without actually enabling the port, and then do another 650917c2899SVille Syrjälä * write to enable the port. Otherwise link training will 651917c2899SVille Syrjälä * fail when the power sequencer is freshly used for this port. 652917c2899SVille Syrjälä */ 653917c2899SVille Syrjälä intel_dp->DP |= DP_PORT_EN; 654917c2899SVille Syrjälä if (crtc_state->has_audio) 655917c2899SVille Syrjälä intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 656917c2899SVille Syrjälä 657917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 658917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 659917c2899SVille Syrjälä } 660917c2899SVille Syrjälä 661917c2899SVille Syrjälä static void intel_enable_dp(struct intel_atomic_state *state, 662917c2899SVille Syrjälä struct intel_encoder *encoder, 663917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config, 664917c2899SVille Syrjälä const struct drm_connector_state *conn_state) 665917c2899SVille Syrjälä { 666917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 667917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 668917c2899SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 669917c2899SVille Syrjälä u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg); 670917c2899SVille Syrjälä enum pipe pipe = crtc->pipe; 671917c2899SVille Syrjälä intel_wakeref_t wakeref; 672917c2899SVille Syrjälä 673917c2899SVille Syrjälä if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN)) 674917c2899SVille Syrjälä return; 675917c2899SVille Syrjälä 676917c2899SVille Syrjälä with_intel_pps_lock(intel_dp, wakeref) { 677917c2899SVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 678917c2899SVille Syrjälä vlv_pps_init(encoder, pipe_config); 679917c2899SVille Syrjälä 680917c2899SVille Syrjälä intel_dp_enable_port(intel_dp, pipe_config); 681917c2899SVille Syrjälä 682917c2899SVille Syrjälä intel_pps_vdd_on_unlocked(intel_dp); 683917c2899SVille Syrjälä intel_pps_on_unlocked(intel_dp); 684917c2899SVille Syrjälä intel_pps_vdd_off_unlocked(intel_dp, true); 685917c2899SVille Syrjälä } 686917c2899SVille Syrjälä 687917c2899SVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 688917c2899SVille Syrjälä unsigned int lane_mask = 0x0; 689917c2899SVille Syrjälä 690917c2899SVille Syrjälä if (IS_CHERRYVIEW(dev_priv)) 691917c2899SVille Syrjälä lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); 692917c2899SVille Syrjälä 693917c2899SVille Syrjälä vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), 694917c2899SVille Syrjälä lane_mask); 695917c2899SVille Syrjälä } 696917c2899SVille Syrjälä 697917c2899SVille Syrjälä intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 698917c2899SVille Syrjälä intel_dp_configure_protocol_converter(intel_dp, pipe_config); 699917c2899SVille Syrjälä intel_dp_check_frl_training(intel_dp); 700917c2899SVille Syrjälä intel_dp_pcon_dsc_configure(intel_dp, pipe_config); 701917c2899SVille Syrjälä intel_dp_start_link_train(intel_dp, pipe_config); 702917c2899SVille Syrjälä intel_dp_stop_link_train(intel_dp, pipe_config); 703917c2899SVille Syrjälä 704917c2899SVille Syrjälä if (pipe_config->has_audio) { 705917c2899SVille Syrjälä drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n", 706917c2899SVille Syrjälä pipe_name(pipe)); 707917c2899SVille Syrjälä intel_audio_codec_enable(encoder, pipe_config, conn_state); 708917c2899SVille Syrjälä } 709917c2899SVille Syrjälä } 710917c2899SVille Syrjälä 711917c2899SVille Syrjälä static void g4x_enable_dp(struct intel_atomic_state *state, 712917c2899SVille Syrjälä struct intel_encoder *encoder, 713917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config, 714917c2899SVille Syrjälä const struct drm_connector_state *conn_state) 715917c2899SVille Syrjälä { 716917c2899SVille Syrjälä intel_enable_dp(state, encoder, pipe_config, conn_state); 717917c2899SVille Syrjälä intel_edp_backlight_on(pipe_config, conn_state); 718917c2899SVille Syrjälä } 719917c2899SVille Syrjälä 720917c2899SVille Syrjälä static void vlv_enable_dp(struct intel_atomic_state *state, 721917c2899SVille Syrjälä struct intel_encoder *encoder, 722917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config, 723917c2899SVille Syrjälä const struct drm_connector_state *conn_state) 724917c2899SVille Syrjälä { 725917c2899SVille Syrjälä intel_edp_backlight_on(pipe_config, conn_state); 726917c2899SVille Syrjälä } 727917c2899SVille Syrjälä 728917c2899SVille Syrjälä static void g4x_pre_enable_dp(struct intel_atomic_state *state, 729917c2899SVille Syrjälä struct intel_encoder *encoder, 730917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config, 731917c2899SVille Syrjälä const struct drm_connector_state *conn_state) 732917c2899SVille Syrjälä { 733917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 734917c2899SVille Syrjälä enum port port = encoder->port; 735917c2899SVille Syrjälä 736917c2899SVille Syrjälä intel_dp_prepare(encoder, pipe_config); 737917c2899SVille Syrjälä 738917c2899SVille Syrjälä /* Only ilk+ has port A */ 739917c2899SVille Syrjälä if (port == PORT_A) 740917c2899SVille Syrjälä ilk_edp_pll_on(intel_dp, pipe_config); 741917c2899SVille Syrjälä } 742917c2899SVille Syrjälä 743917c2899SVille Syrjälä static void vlv_pre_enable_dp(struct intel_atomic_state *state, 744917c2899SVille Syrjälä struct intel_encoder *encoder, 745917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config, 746917c2899SVille Syrjälä const struct drm_connector_state *conn_state) 747917c2899SVille Syrjälä { 748917c2899SVille Syrjälä vlv_phy_pre_encoder_enable(encoder, pipe_config); 749917c2899SVille Syrjälä 750917c2899SVille Syrjälä intel_enable_dp(state, encoder, pipe_config, conn_state); 751917c2899SVille Syrjälä } 752917c2899SVille Syrjälä 753917c2899SVille Syrjälä static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state, 754917c2899SVille Syrjälä struct intel_encoder *encoder, 755917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config, 756917c2899SVille Syrjälä const struct drm_connector_state *conn_state) 757917c2899SVille Syrjälä { 758917c2899SVille Syrjälä intel_dp_prepare(encoder, pipe_config); 759917c2899SVille Syrjälä 760917c2899SVille Syrjälä vlv_phy_pre_pll_enable(encoder, pipe_config); 761917c2899SVille Syrjälä } 762917c2899SVille Syrjälä 763917c2899SVille Syrjälä static void chv_pre_enable_dp(struct intel_atomic_state *state, 764917c2899SVille Syrjälä struct intel_encoder *encoder, 765917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config, 766917c2899SVille Syrjälä const struct drm_connector_state *conn_state) 767917c2899SVille Syrjälä { 768917c2899SVille Syrjälä chv_phy_pre_encoder_enable(encoder, pipe_config); 769917c2899SVille Syrjälä 770917c2899SVille Syrjälä intel_enable_dp(state, encoder, pipe_config, conn_state); 771917c2899SVille Syrjälä 772917c2899SVille Syrjälä /* Second common lane will stay alive on its own now */ 773917c2899SVille Syrjälä chv_phy_release_cl2_override(encoder); 774917c2899SVille Syrjälä } 775917c2899SVille Syrjälä 776917c2899SVille Syrjälä static void chv_dp_pre_pll_enable(struct intel_atomic_state *state, 777917c2899SVille Syrjälä struct intel_encoder *encoder, 778917c2899SVille Syrjälä const struct intel_crtc_state *pipe_config, 779917c2899SVille Syrjälä const struct drm_connector_state *conn_state) 780917c2899SVille Syrjälä { 781917c2899SVille Syrjälä intel_dp_prepare(encoder, pipe_config); 782917c2899SVille Syrjälä 783917c2899SVille Syrjälä chv_phy_pre_pll_enable(encoder, pipe_config); 784917c2899SVille Syrjälä } 785917c2899SVille Syrjälä 786917c2899SVille Syrjälä static void chv_dp_post_pll_disable(struct intel_atomic_state *state, 787917c2899SVille Syrjälä struct intel_encoder *encoder, 788917c2899SVille Syrjälä const struct intel_crtc_state *old_crtc_state, 789917c2899SVille Syrjälä const struct drm_connector_state *old_conn_state) 790917c2899SVille Syrjälä { 791917c2899SVille Syrjälä chv_phy_post_pll_disable(encoder, old_crtc_state); 792917c2899SVille Syrjälä } 793917c2899SVille Syrjälä 794917c2899SVille Syrjälä static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp, 795917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state) 796917c2899SVille Syrjälä { 797917c2899SVille Syrjälä return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 798917c2899SVille Syrjälä } 799917c2899SVille Syrjälä 800917c2899SVille Syrjälä static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp, 801917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state) 802917c2899SVille Syrjälä { 803917c2899SVille Syrjälä return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 804917c2899SVille Syrjälä } 805917c2899SVille Syrjälä 806917c2899SVille Syrjälä static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp) 807917c2899SVille Syrjälä { 808917c2899SVille Syrjälä return DP_TRAIN_PRE_EMPH_LEVEL_2; 809917c2899SVille Syrjälä } 810917c2899SVille Syrjälä 811917c2899SVille Syrjälä static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp) 812917c2899SVille Syrjälä { 813917c2899SVille Syrjälä return DP_TRAIN_PRE_EMPH_LEVEL_3; 814917c2899SVille Syrjälä } 815917c2899SVille Syrjälä 816917c2899SVille Syrjälä static void vlv_set_signal_levels(struct intel_dp *intel_dp, 817917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state) 818917c2899SVille Syrjälä { 819917c2899SVille Syrjälä struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 820917c2899SVille Syrjälä unsigned long demph_reg_value, preemph_reg_value, 821917c2899SVille Syrjälä uniqtranscale_reg_value; 822917c2899SVille Syrjälä u8 train_set = intel_dp->train_set[0]; 823917c2899SVille Syrjälä 824917c2899SVille Syrjälä switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 825917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_0: 826917c2899SVille Syrjälä preemph_reg_value = 0x0004000; 827917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 828917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 829917c2899SVille Syrjälä demph_reg_value = 0x2B405555; 830917c2899SVille Syrjälä uniqtranscale_reg_value = 0x552AB83A; 831917c2899SVille Syrjälä break; 832917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 833917c2899SVille Syrjälä demph_reg_value = 0x2B404040; 834917c2899SVille Syrjälä uniqtranscale_reg_value = 0x5548B83A; 835917c2899SVille Syrjälä break; 836917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 837917c2899SVille Syrjälä demph_reg_value = 0x2B245555; 838917c2899SVille Syrjälä uniqtranscale_reg_value = 0x5560B83A; 839917c2899SVille Syrjälä break; 840917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 841917c2899SVille Syrjälä demph_reg_value = 0x2B405555; 842917c2899SVille Syrjälä uniqtranscale_reg_value = 0x5598DA3A; 843917c2899SVille Syrjälä break; 844917c2899SVille Syrjälä default: 845917c2899SVille Syrjälä return; 846917c2899SVille Syrjälä } 847917c2899SVille Syrjälä break; 848917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_1: 849917c2899SVille Syrjälä preemph_reg_value = 0x0002000; 850917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 851917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 852917c2899SVille Syrjälä demph_reg_value = 0x2B404040; 853917c2899SVille Syrjälä uniqtranscale_reg_value = 0x5552B83A; 854917c2899SVille Syrjälä break; 855917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 856917c2899SVille Syrjälä demph_reg_value = 0x2B404848; 857917c2899SVille Syrjälä uniqtranscale_reg_value = 0x5580B83A; 858917c2899SVille Syrjälä break; 859917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 860917c2899SVille Syrjälä demph_reg_value = 0x2B404040; 861917c2899SVille Syrjälä uniqtranscale_reg_value = 0x55ADDA3A; 862917c2899SVille Syrjälä break; 863917c2899SVille Syrjälä default: 864917c2899SVille Syrjälä return; 865917c2899SVille Syrjälä } 866917c2899SVille Syrjälä break; 867917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_2: 868917c2899SVille Syrjälä preemph_reg_value = 0x0000000; 869917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 870917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 871917c2899SVille Syrjälä demph_reg_value = 0x2B305555; 872917c2899SVille Syrjälä uniqtranscale_reg_value = 0x5570B83A; 873917c2899SVille Syrjälä break; 874917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 875917c2899SVille Syrjälä demph_reg_value = 0x2B2B4040; 876917c2899SVille Syrjälä uniqtranscale_reg_value = 0x55ADDA3A; 877917c2899SVille Syrjälä break; 878917c2899SVille Syrjälä default: 879917c2899SVille Syrjälä return; 880917c2899SVille Syrjälä } 881917c2899SVille Syrjälä break; 882917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_3: 883917c2899SVille Syrjälä preemph_reg_value = 0x0006000; 884917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 885917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 886917c2899SVille Syrjälä demph_reg_value = 0x1B405555; 887917c2899SVille Syrjälä uniqtranscale_reg_value = 0x55ADDA3A; 888917c2899SVille Syrjälä break; 889917c2899SVille Syrjälä default: 890917c2899SVille Syrjälä return; 891917c2899SVille Syrjälä } 892917c2899SVille Syrjälä break; 893917c2899SVille Syrjälä default: 894917c2899SVille Syrjälä return; 895917c2899SVille Syrjälä } 896917c2899SVille Syrjälä 897917c2899SVille Syrjälä vlv_set_phy_signal_level(encoder, crtc_state, 898917c2899SVille Syrjälä demph_reg_value, preemph_reg_value, 899917c2899SVille Syrjälä uniqtranscale_reg_value, 0); 900917c2899SVille Syrjälä } 901917c2899SVille Syrjälä 902917c2899SVille Syrjälä static void chv_set_signal_levels(struct intel_dp *intel_dp, 903917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state) 904917c2899SVille Syrjälä { 905917c2899SVille Syrjälä struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 906917c2899SVille Syrjälä u32 deemph_reg_value, margin_reg_value; 907917c2899SVille Syrjälä bool uniq_trans_scale = false; 908917c2899SVille Syrjälä u8 train_set = intel_dp->train_set[0]; 909917c2899SVille Syrjälä 910917c2899SVille Syrjälä switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 911917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_0: 912917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 913917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 914917c2899SVille Syrjälä deemph_reg_value = 128; 915917c2899SVille Syrjälä margin_reg_value = 52; 916917c2899SVille Syrjälä break; 917917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 918917c2899SVille Syrjälä deemph_reg_value = 128; 919917c2899SVille Syrjälä margin_reg_value = 77; 920917c2899SVille Syrjälä break; 921917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 922917c2899SVille Syrjälä deemph_reg_value = 128; 923917c2899SVille Syrjälä margin_reg_value = 102; 924917c2899SVille Syrjälä break; 925917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 926917c2899SVille Syrjälä deemph_reg_value = 128; 927917c2899SVille Syrjälä margin_reg_value = 154; 928917c2899SVille Syrjälä uniq_trans_scale = true; 929917c2899SVille Syrjälä break; 930917c2899SVille Syrjälä default: 931917c2899SVille Syrjälä return; 932917c2899SVille Syrjälä } 933917c2899SVille Syrjälä break; 934917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_1: 935917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 936917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 937917c2899SVille Syrjälä deemph_reg_value = 85; 938917c2899SVille Syrjälä margin_reg_value = 78; 939917c2899SVille Syrjälä break; 940917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 941917c2899SVille Syrjälä deemph_reg_value = 85; 942917c2899SVille Syrjälä margin_reg_value = 116; 943917c2899SVille Syrjälä break; 944917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 945917c2899SVille Syrjälä deemph_reg_value = 85; 946917c2899SVille Syrjälä margin_reg_value = 154; 947917c2899SVille Syrjälä break; 948917c2899SVille Syrjälä default: 949917c2899SVille Syrjälä return; 950917c2899SVille Syrjälä } 951917c2899SVille Syrjälä break; 952917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_2: 953917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 954917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 955917c2899SVille Syrjälä deemph_reg_value = 64; 956917c2899SVille Syrjälä margin_reg_value = 104; 957917c2899SVille Syrjälä break; 958917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 959917c2899SVille Syrjälä deemph_reg_value = 64; 960917c2899SVille Syrjälä margin_reg_value = 154; 961917c2899SVille Syrjälä break; 962917c2899SVille Syrjälä default: 963917c2899SVille Syrjälä return; 964917c2899SVille Syrjälä } 965917c2899SVille Syrjälä break; 966917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_3: 967917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 968917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 969917c2899SVille Syrjälä deemph_reg_value = 43; 970917c2899SVille Syrjälä margin_reg_value = 154; 971917c2899SVille Syrjälä break; 972917c2899SVille Syrjälä default: 973917c2899SVille Syrjälä return; 974917c2899SVille Syrjälä } 975917c2899SVille Syrjälä break; 976917c2899SVille Syrjälä default: 977917c2899SVille Syrjälä return; 978917c2899SVille Syrjälä } 979917c2899SVille Syrjälä 980917c2899SVille Syrjälä chv_set_phy_signal_level(encoder, crtc_state, 981917c2899SVille Syrjälä deemph_reg_value, margin_reg_value, 982917c2899SVille Syrjälä uniq_trans_scale); 983917c2899SVille Syrjälä } 984917c2899SVille Syrjälä 985917c2899SVille Syrjälä static u32 g4x_signal_levels(u8 train_set) 986917c2899SVille Syrjälä { 987917c2899SVille Syrjälä u32 signal_levels = 0; 988917c2899SVille Syrjälä 989917c2899SVille Syrjälä switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 990917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 991917c2899SVille Syrjälä default: 992917c2899SVille Syrjälä signal_levels |= DP_VOLTAGE_0_4; 993917c2899SVille Syrjälä break; 994917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 995917c2899SVille Syrjälä signal_levels |= DP_VOLTAGE_0_6; 996917c2899SVille Syrjälä break; 997917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 998917c2899SVille Syrjälä signal_levels |= DP_VOLTAGE_0_8; 999917c2899SVille Syrjälä break; 1000917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 1001917c2899SVille Syrjälä signal_levels |= DP_VOLTAGE_1_2; 1002917c2899SVille Syrjälä break; 1003917c2899SVille Syrjälä } 1004917c2899SVille Syrjälä switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 1005917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_0: 1006917c2899SVille Syrjälä default: 1007917c2899SVille Syrjälä signal_levels |= DP_PRE_EMPHASIS_0; 1008917c2899SVille Syrjälä break; 1009917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_1: 1010917c2899SVille Syrjälä signal_levels |= DP_PRE_EMPHASIS_3_5; 1011917c2899SVille Syrjälä break; 1012917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_2: 1013917c2899SVille Syrjälä signal_levels |= DP_PRE_EMPHASIS_6; 1014917c2899SVille Syrjälä break; 1015917c2899SVille Syrjälä case DP_TRAIN_PRE_EMPH_LEVEL_3: 1016917c2899SVille Syrjälä signal_levels |= DP_PRE_EMPHASIS_9_5; 1017917c2899SVille Syrjälä break; 1018917c2899SVille Syrjälä } 1019917c2899SVille Syrjälä return signal_levels; 1020917c2899SVille Syrjälä } 1021917c2899SVille Syrjälä 1022917c2899SVille Syrjälä static void 1023917c2899SVille Syrjälä g4x_set_signal_levels(struct intel_dp *intel_dp, 1024917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state) 1025917c2899SVille Syrjälä { 1026917c2899SVille Syrjälä struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1027917c2899SVille Syrjälä u8 train_set = intel_dp->train_set[0]; 1028917c2899SVille Syrjälä u32 signal_levels; 1029917c2899SVille Syrjälä 1030917c2899SVille Syrjälä signal_levels = g4x_signal_levels(train_set); 1031917c2899SVille Syrjälä 1032917c2899SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1033917c2899SVille Syrjälä signal_levels); 1034917c2899SVille Syrjälä 1035917c2899SVille Syrjälä intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK); 1036917c2899SVille Syrjälä intel_dp->DP |= signal_levels; 1037917c2899SVille Syrjälä 1038917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 1039917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 1040917c2899SVille Syrjälä } 1041917c2899SVille Syrjälä 1042917c2899SVille Syrjälä /* SNB CPU eDP voltage swing and pre-emphasis control */ 1043917c2899SVille Syrjälä static u32 snb_cpu_edp_signal_levels(u8 train_set) 1044917c2899SVille Syrjälä { 1045917c2899SVille Syrjälä u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1046917c2899SVille Syrjälä DP_TRAIN_PRE_EMPHASIS_MASK); 1047917c2899SVille Syrjälä 1048917c2899SVille Syrjälä switch (signal_levels) { 1049917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1050917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1051917c2899SVille Syrjälä return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1052917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1053917c2899SVille Syrjälä return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 1054917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1055917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1056917c2899SVille Syrjälä return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 1057917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1058917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1059917c2899SVille Syrjälä return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 1060917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1061917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1062917c2899SVille Syrjälä return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 1063917c2899SVille Syrjälä default: 1064917c2899SVille Syrjälä MISSING_CASE(signal_levels); 1065917c2899SVille Syrjälä return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1066917c2899SVille Syrjälä } 1067917c2899SVille Syrjälä } 1068917c2899SVille Syrjälä 1069917c2899SVille Syrjälä static void 1070917c2899SVille Syrjälä snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp, 1071917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state) 1072917c2899SVille Syrjälä { 1073917c2899SVille Syrjälä struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1074917c2899SVille Syrjälä u8 train_set = intel_dp->train_set[0]; 1075917c2899SVille Syrjälä u32 signal_levels; 1076917c2899SVille Syrjälä 1077917c2899SVille Syrjälä signal_levels = snb_cpu_edp_signal_levels(train_set); 1078917c2899SVille Syrjälä 1079917c2899SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1080917c2899SVille Syrjälä signal_levels); 1081917c2899SVille Syrjälä 1082917c2899SVille Syrjälä intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 1083917c2899SVille Syrjälä intel_dp->DP |= signal_levels; 1084917c2899SVille Syrjälä 1085917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 1086917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 1087917c2899SVille Syrjälä } 1088917c2899SVille Syrjälä 1089917c2899SVille Syrjälä /* IVB CPU eDP voltage swing and pre-emphasis control */ 1090917c2899SVille Syrjälä static u32 ivb_cpu_edp_signal_levels(u8 train_set) 1091917c2899SVille Syrjälä { 1092917c2899SVille Syrjälä u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1093917c2899SVille Syrjälä DP_TRAIN_PRE_EMPHASIS_MASK); 1094917c2899SVille Syrjälä 1095917c2899SVille Syrjälä switch (signal_levels) { 1096917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1097917c2899SVille Syrjälä return EDP_LINK_TRAIN_400MV_0DB_IVB; 1098917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1099917c2899SVille Syrjälä return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 1100917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1101917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1102917c2899SVille Syrjälä return EDP_LINK_TRAIN_400MV_6DB_IVB; 1103917c2899SVille Syrjälä 1104917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1105917c2899SVille Syrjälä return EDP_LINK_TRAIN_600MV_0DB_IVB; 1106917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1107917c2899SVille Syrjälä return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 1108917c2899SVille Syrjälä 1109917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1110917c2899SVille Syrjälä return EDP_LINK_TRAIN_800MV_0DB_IVB; 1111917c2899SVille Syrjälä case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1112917c2899SVille Syrjälä return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 1113917c2899SVille Syrjälä 1114917c2899SVille Syrjälä default: 1115917c2899SVille Syrjälä MISSING_CASE(signal_levels); 1116917c2899SVille Syrjälä return EDP_LINK_TRAIN_500MV_0DB_IVB; 1117917c2899SVille Syrjälä } 1118917c2899SVille Syrjälä } 1119917c2899SVille Syrjälä 1120917c2899SVille Syrjälä static void 1121917c2899SVille Syrjälä ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp, 1122917c2899SVille Syrjälä const struct intel_crtc_state *crtc_state) 1123917c2899SVille Syrjälä { 1124917c2899SVille Syrjälä struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1125917c2899SVille Syrjälä u8 train_set = intel_dp->train_set[0]; 1126917c2899SVille Syrjälä u32 signal_levels; 1127917c2899SVille Syrjälä 1128917c2899SVille Syrjälä signal_levels = ivb_cpu_edp_signal_levels(train_set); 1129917c2899SVille Syrjälä 1130917c2899SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1131917c2899SVille Syrjälä signal_levels); 1132917c2899SVille Syrjälä 1133917c2899SVille Syrjälä intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 1134917c2899SVille Syrjälä intel_dp->DP |= signal_levels; 1135917c2899SVille Syrjälä 1136917c2899SVille Syrjälä intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 1137917c2899SVille Syrjälä intel_de_posting_read(dev_priv, intel_dp->output_reg); 1138917c2899SVille Syrjälä } 1139917c2899SVille Syrjälä 1140917c2899SVille Syrjälä /* 1141917c2899SVille Syrjälä * If display is now connected check links status, 1142917c2899SVille Syrjälä * there has been known issues of link loss triggering 1143917c2899SVille Syrjälä * long pulse. 1144917c2899SVille Syrjälä * 1145917c2899SVille Syrjälä * Some sinks (eg. ASUS PB287Q) seem to perform some 1146917c2899SVille Syrjälä * weird HPD ping pong during modesets. So we can apparently 1147917c2899SVille Syrjälä * end up with HPD going low during a modeset, and then 1148917c2899SVille Syrjälä * going back up soon after. And once that happens we must 1149917c2899SVille Syrjälä * retrain the link to get a picture. That's in case no 1150917c2899SVille Syrjälä * userspace component reacted to intermittent HPD dip. 1151917c2899SVille Syrjälä */ 1152917c2899SVille Syrjälä static enum intel_hotplug_state 1153917c2899SVille Syrjälä intel_dp_hotplug(struct intel_encoder *encoder, 1154917c2899SVille Syrjälä struct intel_connector *connector) 1155917c2899SVille Syrjälä { 1156917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1157917c2899SVille Syrjälä struct drm_modeset_acquire_ctx ctx; 1158917c2899SVille Syrjälä enum intel_hotplug_state state; 1159917c2899SVille Syrjälä int ret; 1160917c2899SVille Syrjälä 1161917c2899SVille Syrjälä if (intel_dp->compliance.test_active && 1162917c2899SVille Syrjälä intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 1163917c2899SVille Syrjälä intel_dp_phy_test(encoder); 1164917c2899SVille Syrjälä /* just do the PHY test and nothing else */ 1165917c2899SVille Syrjälä return INTEL_HOTPLUG_UNCHANGED; 1166917c2899SVille Syrjälä } 1167917c2899SVille Syrjälä 1168917c2899SVille Syrjälä state = intel_encoder_hotplug(encoder, connector); 1169917c2899SVille Syrjälä 1170917c2899SVille Syrjälä drm_modeset_acquire_init(&ctx, 0); 1171917c2899SVille Syrjälä 1172917c2899SVille Syrjälä for (;;) { 1173917c2899SVille Syrjälä ret = intel_dp_retrain_link(encoder, &ctx); 1174917c2899SVille Syrjälä 1175917c2899SVille Syrjälä if (ret == -EDEADLK) { 1176917c2899SVille Syrjälä drm_modeset_backoff(&ctx); 1177917c2899SVille Syrjälä continue; 1178917c2899SVille Syrjälä } 1179917c2899SVille Syrjälä 1180917c2899SVille Syrjälä break; 1181917c2899SVille Syrjälä } 1182917c2899SVille Syrjälä 1183917c2899SVille Syrjälä drm_modeset_drop_locks(&ctx); 1184917c2899SVille Syrjälä drm_modeset_acquire_fini(&ctx); 1185917c2899SVille Syrjälä drm_WARN(encoder->base.dev, ret, 1186917c2899SVille Syrjälä "Acquiring modeset locks failed with %i\n", ret); 1187917c2899SVille Syrjälä 1188917c2899SVille Syrjälä /* 1189917c2899SVille Syrjälä * Keeping it consistent with intel_ddi_hotplug() and 1190917c2899SVille Syrjälä * intel_hdmi_hotplug(). 1191917c2899SVille Syrjälä */ 1192917c2899SVille Syrjälä if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 1193917c2899SVille Syrjälä state = INTEL_HOTPLUG_RETRY; 1194917c2899SVille Syrjälä 1195917c2899SVille Syrjälä return state; 1196917c2899SVille Syrjälä } 1197917c2899SVille Syrjälä 1198917c2899SVille Syrjälä static bool ibx_digital_port_connected(struct intel_encoder *encoder) 1199917c2899SVille Syrjälä { 1200917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1201917c2899SVille Syrjälä u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 1202917c2899SVille Syrjälä 1203917c2899SVille Syrjälä return intel_de_read(dev_priv, SDEISR) & bit; 1204917c2899SVille Syrjälä } 1205917c2899SVille Syrjälä 1206917c2899SVille Syrjälä static bool g4x_digital_port_connected(struct intel_encoder *encoder) 1207917c2899SVille Syrjälä { 1208917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1209917c2899SVille Syrjälä u32 bit; 1210917c2899SVille Syrjälä 1211917c2899SVille Syrjälä switch (encoder->hpd_pin) { 1212917c2899SVille Syrjälä case HPD_PORT_B: 1213917c2899SVille Syrjälä bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 1214917c2899SVille Syrjälä break; 1215917c2899SVille Syrjälä case HPD_PORT_C: 1216917c2899SVille Syrjälä bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 1217917c2899SVille Syrjälä break; 1218917c2899SVille Syrjälä case HPD_PORT_D: 1219917c2899SVille Syrjälä bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 1220917c2899SVille Syrjälä break; 1221917c2899SVille Syrjälä default: 1222917c2899SVille Syrjälä MISSING_CASE(encoder->hpd_pin); 1223917c2899SVille Syrjälä return false; 1224917c2899SVille Syrjälä } 1225917c2899SVille Syrjälä 1226917c2899SVille Syrjälä return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; 1227917c2899SVille Syrjälä } 1228917c2899SVille Syrjälä 1229917c2899SVille Syrjälä static bool gm45_digital_port_connected(struct intel_encoder *encoder) 1230917c2899SVille Syrjälä { 1231917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1232917c2899SVille Syrjälä u32 bit; 1233917c2899SVille Syrjälä 1234917c2899SVille Syrjälä switch (encoder->hpd_pin) { 1235917c2899SVille Syrjälä case HPD_PORT_B: 1236917c2899SVille Syrjälä bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; 1237917c2899SVille Syrjälä break; 1238917c2899SVille Syrjälä case HPD_PORT_C: 1239917c2899SVille Syrjälä bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; 1240917c2899SVille Syrjälä break; 1241917c2899SVille Syrjälä case HPD_PORT_D: 1242917c2899SVille Syrjälä bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; 1243917c2899SVille Syrjälä break; 1244917c2899SVille Syrjälä default: 1245917c2899SVille Syrjälä MISSING_CASE(encoder->hpd_pin); 1246917c2899SVille Syrjälä return false; 1247917c2899SVille Syrjälä } 1248917c2899SVille Syrjälä 1249917c2899SVille Syrjälä return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; 1250917c2899SVille Syrjälä } 1251917c2899SVille Syrjälä 1252917c2899SVille Syrjälä static bool ilk_digital_port_connected(struct intel_encoder *encoder) 1253917c2899SVille Syrjälä { 1254917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1255917c2899SVille Syrjälä u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 1256917c2899SVille Syrjälä 1257917c2899SVille Syrjälä return intel_de_read(dev_priv, DEISR) & bit; 1258917c2899SVille Syrjälä } 1259917c2899SVille Syrjälä 1260917c2899SVille Syrjälä static void intel_dp_encoder_destroy(struct drm_encoder *encoder) 1261917c2899SVille Syrjälä { 1262917c2899SVille Syrjälä intel_dp_encoder_flush_work(encoder); 1263917c2899SVille Syrjälä 1264917c2899SVille Syrjälä drm_encoder_cleanup(encoder); 1265917c2899SVille Syrjälä kfree(enc_to_dig_port(to_intel_encoder(encoder))); 1266917c2899SVille Syrjälä } 1267917c2899SVille Syrjälä 1268917c2899SVille Syrjälä enum pipe vlv_active_pipe(struct intel_dp *intel_dp) 1269917c2899SVille Syrjälä { 1270917c2899SVille Syrjälä struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1271917c2899SVille Syrjälä struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1272917c2899SVille Syrjälä enum pipe pipe; 1273917c2899SVille Syrjälä 1274053ffdd1SVille Syrjälä if (g4x_dp_port_enabled(dev_priv, intel_dp->output_reg, 1275917c2899SVille Syrjälä encoder->port, &pipe)) 1276917c2899SVille Syrjälä return pipe; 1277917c2899SVille Syrjälä 1278917c2899SVille Syrjälä return INVALID_PIPE; 1279917c2899SVille Syrjälä } 1280917c2899SVille Syrjälä 1281917c2899SVille Syrjälä static void intel_dp_encoder_reset(struct drm_encoder *encoder) 1282917c2899SVille Syrjälä { 1283917c2899SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(encoder->dev); 1284917c2899SVille Syrjälä struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 1285917c2899SVille Syrjälä 1286917c2899SVille Syrjälä intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); 1287917c2899SVille Syrjälä 1288917c2899SVille Syrjälä intel_dp->reset_link_params = true; 1289917c2899SVille Syrjälä 1290917c2899SVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1291917c2899SVille Syrjälä intel_wakeref_t wakeref; 1292917c2899SVille Syrjälä 1293917c2899SVille Syrjälä with_intel_pps_lock(intel_dp, wakeref) 1294917c2899SVille Syrjälä intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp); 1295917c2899SVille Syrjälä } 1296917c2899SVille Syrjälä 1297917c2899SVille Syrjälä intel_pps_encoder_reset(intel_dp); 1298917c2899SVille Syrjälä } 1299917c2899SVille Syrjälä 1300917c2899SVille Syrjälä static const struct drm_encoder_funcs intel_dp_enc_funcs = { 1301917c2899SVille Syrjälä .reset = intel_dp_encoder_reset, 1302917c2899SVille Syrjälä .destroy = intel_dp_encoder_destroy, 1303917c2899SVille Syrjälä }; 1304917c2899SVille Syrjälä 1305053ffdd1SVille Syrjälä bool g4x_dp_init(struct drm_i915_private *dev_priv, 1306053ffdd1SVille Syrjälä i915_reg_t output_reg, enum port port) 1307917c2899SVille Syrjälä { 1308917c2899SVille Syrjälä struct intel_digital_port *dig_port; 1309917c2899SVille Syrjälä struct intel_encoder *intel_encoder; 1310917c2899SVille Syrjälä struct drm_encoder *encoder; 1311917c2899SVille Syrjälä struct intel_connector *intel_connector; 1312917c2899SVille Syrjälä 1313917c2899SVille Syrjälä dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 1314917c2899SVille Syrjälä if (!dig_port) 1315917c2899SVille Syrjälä return false; 1316917c2899SVille Syrjälä 1317917c2899SVille Syrjälä intel_connector = intel_connector_alloc(); 1318917c2899SVille Syrjälä if (!intel_connector) 1319917c2899SVille Syrjälä goto err_connector_alloc; 1320917c2899SVille Syrjälä 1321917c2899SVille Syrjälä intel_encoder = &dig_port->base; 1322917c2899SVille Syrjälä encoder = &intel_encoder->base; 1323917c2899SVille Syrjälä 1324917c2899SVille Syrjälä mutex_init(&dig_port->hdcp_mutex); 1325917c2899SVille Syrjälä 1326917c2899SVille Syrjälä if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 1327917c2899SVille Syrjälä &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, 1328917c2899SVille Syrjälä "DP %c", port_name(port))) 1329917c2899SVille Syrjälä goto err_encoder_init; 1330917c2899SVille Syrjälä 1331917c2899SVille Syrjälä intel_encoder->hotplug = intel_dp_hotplug; 1332917c2899SVille Syrjälä intel_encoder->compute_config = intel_dp_compute_config; 1333917c2899SVille Syrjälä intel_encoder->get_hw_state = intel_dp_get_hw_state; 1334917c2899SVille Syrjälä intel_encoder->get_config = intel_dp_get_config; 1335917c2899SVille Syrjälä intel_encoder->sync_state = intel_dp_sync_state; 1336917c2899SVille Syrjälä intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check; 1337917c2899SVille Syrjälä intel_encoder->update_pipe = intel_panel_update_backlight; 1338917c2899SVille Syrjälä intel_encoder->suspend = intel_dp_encoder_suspend; 1339917c2899SVille Syrjälä intel_encoder->shutdown = intel_dp_encoder_shutdown; 1340917c2899SVille Syrjälä if (IS_CHERRYVIEW(dev_priv)) { 1341917c2899SVille Syrjälä intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; 1342917c2899SVille Syrjälä intel_encoder->pre_enable = chv_pre_enable_dp; 1343917c2899SVille Syrjälä intel_encoder->enable = vlv_enable_dp; 1344917c2899SVille Syrjälä intel_encoder->disable = vlv_disable_dp; 1345917c2899SVille Syrjälä intel_encoder->post_disable = chv_post_disable_dp; 1346917c2899SVille Syrjälä intel_encoder->post_pll_disable = chv_dp_post_pll_disable; 1347917c2899SVille Syrjälä } else if (IS_VALLEYVIEW(dev_priv)) { 1348917c2899SVille Syrjälä intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 1349917c2899SVille Syrjälä intel_encoder->pre_enable = vlv_pre_enable_dp; 1350917c2899SVille Syrjälä intel_encoder->enable = vlv_enable_dp; 1351917c2899SVille Syrjälä intel_encoder->disable = vlv_disable_dp; 1352917c2899SVille Syrjälä intel_encoder->post_disable = vlv_post_disable_dp; 1353917c2899SVille Syrjälä } else { 1354917c2899SVille Syrjälä intel_encoder->pre_enable = g4x_pre_enable_dp; 1355917c2899SVille Syrjälä intel_encoder->enable = g4x_enable_dp; 1356917c2899SVille Syrjälä intel_encoder->disable = g4x_disable_dp; 1357917c2899SVille Syrjälä intel_encoder->post_disable = g4x_post_disable_dp; 1358917c2899SVille Syrjälä } 1359917c2899SVille Syrjälä 1360917c2899SVille Syrjälä if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || 1361917c2899SVille Syrjälä (HAS_PCH_CPT(dev_priv) && port != PORT_A)) 1362917c2899SVille Syrjälä dig_port->dp.set_link_train = cpt_set_link_train; 1363917c2899SVille Syrjälä else 1364917c2899SVille Syrjälä dig_port->dp.set_link_train = g4x_set_link_train; 1365917c2899SVille Syrjälä 1366917c2899SVille Syrjälä if (IS_CHERRYVIEW(dev_priv)) 1367917c2899SVille Syrjälä dig_port->dp.set_signal_levels = chv_set_signal_levels; 1368917c2899SVille Syrjälä else if (IS_VALLEYVIEW(dev_priv)) 1369917c2899SVille Syrjälä dig_port->dp.set_signal_levels = vlv_set_signal_levels; 1370917c2899SVille Syrjälä else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) 1371917c2899SVille Syrjälä dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels; 1372d47d29a6SMatt Roper else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A) 1373917c2899SVille Syrjälä dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels; 1374917c2899SVille Syrjälä else 1375917c2899SVille Syrjälä dig_port->dp.set_signal_levels = g4x_set_signal_levels; 1376917c2899SVille Syrjälä 1377917c2899SVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || 1378917c2899SVille Syrjälä (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) { 1379917c2899SVille Syrjälä dig_port->dp.preemph_max = intel_dp_preemph_max_3; 1380917c2899SVille Syrjälä dig_port->dp.voltage_max = intel_dp_voltage_max_3; 1381917c2899SVille Syrjälä } else { 1382917c2899SVille Syrjälä dig_port->dp.preemph_max = intel_dp_preemph_max_2; 1383917c2899SVille Syrjälä dig_port->dp.voltage_max = intel_dp_voltage_max_2; 1384917c2899SVille Syrjälä } 1385917c2899SVille Syrjälä 1386917c2899SVille Syrjälä dig_port->dp.output_reg = output_reg; 1387917c2899SVille Syrjälä dig_port->max_lanes = 4; 1388917c2899SVille Syrjälä 1389917c2899SVille Syrjälä intel_encoder->type = INTEL_OUTPUT_DP; 1390917c2899SVille Syrjälä intel_encoder->power_domain = intel_port_to_power_domain(port); 1391917c2899SVille Syrjälä if (IS_CHERRYVIEW(dev_priv)) { 1392917c2899SVille Syrjälä if (port == PORT_D) 1393917c2899SVille Syrjälä intel_encoder->pipe_mask = BIT(PIPE_C); 1394917c2899SVille Syrjälä else 1395917c2899SVille Syrjälä intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 1396917c2899SVille Syrjälä } else { 1397917c2899SVille Syrjälä intel_encoder->pipe_mask = ~0; 1398917c2899SVille Syrjälä } 1399917c2899SVille Syrjälä intel_encoder->cloneable = 0; 1400917c2899SVille Syrjälä intel_encoder->port = port; 1401917c2899SVille Syrjälä intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 1402917c2899SVille Syrjälä 1403917c2899SVille Syrjälä dig_port->hpd_pulse = intel_dp_hpd_pulse; 1404917c2899SVille Syrjälä 1405917c2899SVille Syrjälä if (HAS_GMCH(dev_priv)) { 1406917c2899SVille Syrjälä if (IS_GM45(dev_priv)) 1407917c2899SVille Syrjälä dig_port->connected = gm45_digital_port_connected; 1408917c2899SVille Syrjälä else 1409917c2899SVille Syrjälä dig_port->connected = g4x_digital_port_connected; 1410917c2899SVille Syrjälä } else { 1411917c2899SVille Syrjälä if (port == PORT_A) 1412917c2899SVille Syrjälä dig_port->connected = ilk_digital_port_connected; 1413917c2899SVille Syrjälä else 1414917c2899SVille Syrjälä dig_port->connected = ibx_digital_port_connected; 1415917c2899SVille Syrjälä } 1416917c2899SVille Syrjälä 1417917c2899SVille Syrjälä if (port != PORT_A) 1418917c2899SVille Syrjälä intel_infoframe_init(dig_port); 1419917c2899SVille Syrjälä 1420917c2899SVille Syrjälä dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 1421917c2899SVille Syrjälä if (!intel_dp_init_connector(dig_port, intel_connector)) 1422917c2899SVille Syrjälä goto err_init_connector; 1423917c2899SVille Syrjälä 1424917c2899SVille Syrjälä return true; 1425917c2899SVille Syrjälä 1426917c2899SVille Syrjälä err_init_connector: 1427917c2899SVille Syrjälä drm_encoder_cleanup(encoder); 1428917c2899SVille Syrjälä err_encoder_init: 1429917c2899SVille Syrjälä kfree(intel_connector); 1430917c2899SVille Syrjälä err_connector_alloc: 1431917c2899SVille Syrjälä kfree(dig_port); 1432917c2899SVille Syrjälä return false; 1433917c2899SVille Syrjälä } 1434