1 /* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 19 20 #include <linux/hdmi.h> 21 #include <linux/module.h> 22 23 #include <drm/drmP.h> 24 #include <drm/drm_crtc_helper.h> 25 #include <drm/drm_encoder_slave.h> 26 #include <drm/drm_edid.h> 27 #include <drm/i2c/tda998x.h> 28 29 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 30 31 struct tda998x_priv { 32 struct i2c_client *cec; 33 uint16_t rev; 34 uint8_t current_page; 35 int dpms; 36 bool is_hdmi_sink; 37 u8 vip_cntrl_0; 38 u8 vip_cntrl_1; 39 u8 vip_cntrl_2; 40 struct tda998x_encoder_params params; 41 }; 42 43 #define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv) 44 45 /* The TDA9988 series of devices use a paged register scheme.. to simplify 46 * things we encode the page # in upper bits of the register #. To read/ 47 * write a given register, we need to make sure CURPAGE register is set 48 * appropriately. Which implies reads/writes are not atomic. Fun! 49 */ 50 51 #define REG(page, addr) (((page) << 8) | (addr)) 52 #define REG2ADDR(reg) ((reg) & 0xff) 53 #define REG2PAGE(reg) (((reg) >> 8) & 0xff) 54 55 #define REG_CURPAGE 0xff /* write */ 56 57 58 /* Page 00h: General Control */ 59 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */ 60 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ 61 # define MAIN_CNTRL0_SR (1 << 0) 62 # define MAIN_CNTRL0_DECS (1 << 1) 63 # define MAIN_CNTRL0_DEHS (1 << 2) 64 # define MAIN_CNTRL0_CECS (1 << 3) 65 # define MAIN_CNTRL0_CEHS (1 << 4) 66 # define MAIN_CNTRL0_SCALER (1 << 7) 67 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */ 68 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ 69 # define SOFTRESET_AUDIO (1 << 0) 70 # define SOFTRESET_I2C_MASTER (1 << 1) 71 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ 72 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ 73 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ 74 # define I2C_MASTER_DIS_MM (1 << 0) 75 # define I2C_MASTER_DIS_FILT (1 << 1) 76 # define I2C_MASTER_APP_STRT_LAT (1 << 2) 77 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ 78 # define FEAT_POWERDOWN_SPDIF (1 << 3) 79 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ 80 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ 81 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ 82 # define INT_FLAGS_2_EDID_BLK_RD (1 << 1) 83 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ 84 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ 85 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ 86 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ 87 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ 88 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ 89 # define VIP_CNTRL_0_MIRR_A (1 << 7) 90 # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) 91 # define VIP_CNTRL_0_MIRR_B (1 << 3) 92 # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) 93 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ 94 # define VIP_CNTRL_1_MIRR_C (1 << 7) 95 # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) 96 # define VIP_CNTRL_1_MIRR_D (1 << 3) 97 # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) 98 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ 99 # define VIP_CNTRL_2_MIRR_E (1 << 7) 100 # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) 101 # define VIP_CNTRL_2_MIRR_F (1 << 3) 102 # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) 103 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ 104 # define VIP_CNTRL_3_X_TGL (1 << 0) 105 # define VIP_CNTRL_3_H_TGL (1 << 1) 106 # define VIP_CNTRL_3_V_TGL (1 << 2) 107 # define VIP_CNTRL_3_EMB (1 << 3) 108 # define VIP_CNTRL_3_SYNC_DE (1 << 4) 109 # define VIP_CNTRL_3_SYNC_HS (1 << 5) 110 # define VIP_CNTRL_3_DE_INT (1 << 6) 111 # define VIP_CNTRL_3_EDGE (1 << 7) 112 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ 113 # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) 114 # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) 115 # define VIP_CNTRL_4_CCIR656 (1 << 4) 116 # define VIP_CNTRL_4_656_ALT (1 << 5) 117 # define VIP_CNTRL_4_TST_656 (1 << 6) 118 # define VIP_CNTRL_4_TST_PAT (1 << 7) 119 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ 120 # define VIP_CNTRL_5_CKCASE (1 << 0) 121 # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) 122 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */ 123 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ 124 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ 125 # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) 126 # define MAT_CONTRL_MAT_BP (1 << 2) 127 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ 128 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ 129 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ 130 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ 131 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ 132 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ 133 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ 134 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ 135 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ 136 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ 137 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ 138 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ 139 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ 140 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ 141 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ 142 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ 143 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ 144 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ 145 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ 146 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ 147 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ 148 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ 149 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ 150 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ 151 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ 152 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ 153 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ 154 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ 155 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ 156 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ 157 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ 158 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ 159 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ 160 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ 161 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ 162 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ 163 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ 164 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ 165 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ 166 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ 167 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ 168 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ 169 # define TBG_CNTRL_0_TOP_TGL (1 << 0) 170 # define TBG_CNTRL_0_TOP_SEL (1 << 1) 171 # define TBG_CNTRL_0_DE_EXT (1 << 2) 172 # define TBG_CNTRL_0_TOP_EXT (1 << 3) 173 # define TBG_CNTRL_0_FRAME_DIS (1 << 5) 174 # define TBG_CNTRL_0_SYNC_MTHD (1 << 6) 175 # define TBG_CNTRL_0_SYNC_ONCE (1 << 7) 176 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ 177 # define TBG_CNTRL_1_H_TGL (1 << 0) 178 # define TBG_CNTRL_1_V_TGL (1 << 1) 179 # define TBG_CNTRL_1_TGL_EN (1 << 2) 180 # define TBG_CNTRL_1_X_EXT (1 << 3) 181 # define TBG_CNTRL_1_H_EXT (1 << 4) 182 # define TBG_CNTRL_1_V_EXT (1 << 5) 183 # define TBG_CNTRL_1_DWIN_DIS (1 << 6) 184 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ 185 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ 186 # define HVF_CNTRL_0_SM (1 << 7) 187 # define HVF_CNTRL_0_RWB (1 << 6) 188 # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) 189 # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) 190 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ 191 # define HVF_CNTRL_1_FOR (1 << 0) 192 # define HVF_CNTRL_1_YUVBLK (1 << 1) 193 # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) 194 # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) 195 # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) 196 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ 197 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ 198 # define I2S_FORMAT(x) (((x) & 3) << 0) 199 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ 200 # define AIP_CLKSEL_FS(x) (((x) & 3) << 0) 201 # define AIP_CLKSEL_CLK_POL(x) (((x) & 1) << 2) 202 # define AIP_CLKSEL_AIP(x) (((x) & 7) << 3) 203 204 205 /* Page 02h: PLL settings */ 206 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ 207 # define PLL_SERIAL_1_SRL_FDN (1 << 0) 208 # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) 209 # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) 210 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ 211 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0) 212 # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) 213 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ 214 # define PLL_SERIAL_3_SRL_CCIR (1 << 0) 215 # define PLL_SERIAL_3_SRL_DE (1 << 2) 216 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) 217 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ 218 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ 219 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ 220 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ 221 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ 222 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ 223 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ 224 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ 225 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ 226 # define AUDIO_DIV_SERCLK_1 0 227 # define AUDIO_DIV_SERCLK_2 1 228 # define AUDIO_DIV_SERCLK_4 2 229 # define AUDIO_DIV_SERCLK_8 3 230 # define AUDIO_DIV_SERCLK_16 4 231 # define AUDIO_DIV_SERCLK_32 5 232 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ 233 # define SEL_CLK_SEL_CLK1 (1 << 0) 234 # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) 235 # define SEL_CLK_ENA_SC_CLK (1 << 3) 236 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ 237 238 239 /* Page 09h: EDID Control */ 240 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ 241 /* next 127 successive registers are the EDID block */ 242 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ 243 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ 244 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ 245 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ 246 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ 247 248 249 /* Page 10h: information frames and packets */ 250 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ 251 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ 252 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ 253 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ 254 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ 255 256 257 /* Page 11h: audio settings and content info packets */ 258 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ 259 # define AIP_CNTRL_0_RST_FIFO (1 << 0) 260 # define AIP_CNTRL_0_SWAP (1 << 1) 261 # define AIP_CNTRL_0_LAYOUT (1 << 2) 262 # define AIP_CNTRL_0_ACR_MAN (1 << 5) 263 # define AIP_CNTRL_0_RST_CTS (1 << 6) 264 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */ 265 # define CA_I2S_CA_I2S(x) (((x) & 31) << 0) 266 # define CA_I2S_HBR_CHSTAT (1 << 6) 267 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ 268 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ 269 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ 270 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ 271 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ 272 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ 273 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ 274 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */ 275 # define CTS_N_K(x) (((x) & 7) << 0) 276 # define CTS_N_M(x) (((x) & 3) << 4) 277 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ 278 # define ENC_CNTRL_RST_ENC (1 << 0) 279 # define ENC_CNTRL_RST_SEL (1 << 1) 280 # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) 281 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ 282 # define DIP_FLAGS_ACR (1 << 0) 283 # define DIP_FLAGS_GC (1 << 1) 284 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ 285 # define DIP_IF_FLAGS_IF1 (1 << 1) 286 # define DIP_IF_FLAGS_IF2 (1 << 2) 287 # define DIP_IF_FLAGS_IF3 (1 << 3) 288 # define DIP_IF_FLAGS_IF4 (1 << 4) 289 # define DIP_IF_FLAGS_IF5 (1 << 5) 290 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ 291 292 293 /* Page 12h: HDCP and OTP */ 294 #define REG_TX3 REG(0x12, 0x9a) /* read/write */ 295 #define REG_TX4 REG(0x12, 0x9b) /* read/write */ 296 # define TX4_PD_RAM (1 << 1) 297 #define REG_TX33 REG(0x12, 0xb8) /* read/write */ 298 # define TX33_HDMI (1 << 1) 299 300 301 /* Page 13h: Gamut related metadata packets */ 302 303 304 305 /* CEC registers: (not paged) 306 */ 307 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ 308 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) 309 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) 310 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) 311 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) 312 #define REG_CEC_RXSHPDLEV 0xfe /* read */ 313 # define CEC_RXSHPDLEV_RXSENS (1 << 0) 314 # define CEC_RXSHPDLEV_HPD (1 << 1) 315 316 #define REG_CEC_ENAMODS 0xff /* read/write */ 317 # define CEC_ENAMODS_DIS_FRO (1 << 6) 318 # define CEC_ENAMODS_DIS_CCLK (1 << 5) 319 # define CEC_ENAMODS_EN_RXSENS (1 << 2) 320 # define CEC_ENAMODS_EN_HDMI (1 << 1) 321 # define CEC_ENAMODS_EN_CEC (1 << 0) 322 323 324 /* Device versions: */ 325 #define TDA9989N2 0x0101 326 #define TDA19989 0x0201 327 #define TDA19989N2 0x0202 328 #define TDA19988 0x0301 329 330 static void 331 cec_write(struct drm_encoder *encoder, uint16_t addr, uint8_t val) 332 { 333 struct i2c_client *client = to_tda998x_priv(encoder)->cec; 334 uint8_t buf[] = {addr, val}; 335 int ret; 336 337 ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 338 if (ret < 0) 339 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr); 340 } 341 342 static uint8_t 343 cec_read(struct drm_encoder *encoder, uint8_t addr) 344 { 345 struct i2c_client *client = to_tda998x_priv(encoder)->cec; 346 uint8_t val; 347 int ret; 348 349 ret = i2c_master_send(client, &addr, sizeof(addr)); 350 if (ret < 0) 351 goto fail; 352 353 ret = i2c_master_recv(client, &val, sizeof(val)); 354 if (ret < 0) 355 goto fail; 356 357 return val; 358 359 fail: 360 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr); 361 return 0; 362 } 363 364 static void 365 set_page(struct drm_encoder *encoder, uint16_t reg) 366 { 367 struct tda998x_priv *priv = to_tda998x_priv(encoder); 368 369 if (REG2PAGE(reg) != priv->current_page) { 370 struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 371 uint8_t buf[] = { 372 REG_CURPAGE, REG2PAGE(reg) 373 }; 374 int ret = i2c_master_send(client, buf, sizeof(buf)); 375 if (ret < 0) 376 dev_err(&client->dev, "Error %d writing to REG_CURPAGE\n", ret); 377 378 priv->current_page = REG2PAGE(reg); 379 } 380 } 381 382 static int 383 reg_read_range(struct drm_encoder *encoder, uint16_t reg, char *buf, int cnt) 384 { 385 struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 386 uint8_t addr = REG2ADDR(reg); 387 int ret; 388 389 set_page(encoder, reg); 390 391 ret = i2c_master_send(client, &addr, sizeof(addr)); 392 if (ret < 0) 393 goto fail; 394 395 ret = i2c_master_recv(client, buf, cnt); 396 if (ret < 0) 397 goto fail; 398 399 return ret; 400 401 fail: 402 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); 403 return ret; 404 } 405 406 static void 407 reg_write_range(struct drm_encoder *encoder, uint16_t reg, uint8_t *p, int cnt) 408 { 409 struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 410 uint8_t buf[cnt+1]; 411 int ret; 412 413 buf[0] = REG2ADDR(reg); 414 memcpy(&buf[1], p, cnt); 415 416 set_page(encoder, reg); 417 418 ret = i2c_master_send(client, buf, cnt + 1); 419 if (ret < 0) 420 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 421 } 422 423 static uint8_t 424 reg_read(struct drm_encoder *encoder, uint16_t reg) 425 { 426 uint8_t val = 0; 427 reg_read_range(encoder, reg, &val, sizeof(val)); 428 return val; 429 } 430 431 static void 432 reg_write(struct drm_encoder *encoder, uint16_t reg, uint8_t val) 433 { 434 struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 435 uint8_t buf[] = {REG2ADDR(reg), val}; 436 int ret; 437 438 set_page(encoder, reg); 439 440 ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 441 if (ret < 0) 442 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 443 } 444 445 static void 446 reg_write16(struct drm_encoder *encoder, uint16_t reg, uint16_t val) 447 { 448 struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 449 uint8_t buf[] = {REG2ADDR(reg), val >> 8, val}; 450 int ret; 451 452 set_page(encoder, reg); 453 454 ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 455 if (ret < 0) 456 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 457 } 458 459 static void 460 reg_set(struct drm_encoder *encoder, uint16_t reg, uint8_t val) 461 { 462 reg_write(encoder, reg, reg_read(encoder, reg) | val); 463 } 464 465 static void 466 reg_clear(struct drm_encoder *encoder, uint16_t reg, uint8_t val) 467 { 468 reg_write(encoder, reg, reg_read(encoder, reg) & ~val); 469 } 470 471 static void 472 tda998x_reset(struct drm_encoder *encoder) 473 { 474 /* reset audio and i2c master: */ 475 reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 476 msleep(50); 477 reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 478 msleep(50); 479 480 /* reset transmitter: */ 481 reg_set(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 482 reg_clear(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 483 484 /* PLL registers common configuration */ 485 reg_write(encoder, REG_PLL_SERIAL_1, 0x00); 486 reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); 487 reg_write(encoder, REG_PLL_SERIAL_3, 0x00); 488 reg_write(encoder, REG_SERIALIZER, 0x00); 489 reg_write(encoder, REG_BUFFER_OUT, 0x00); 490 reg_write(encoder, REG_PLL_SCG1, 0x00); 491 reg_write(encoder, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); 492 reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 493 reg_write(encoder, REG_PLL_SCGN1, 0xfa); 494 reg_write(encoder, REG_PLL_SCGN2, 0x00); 495 reg_write(encoder, REG_PLL_SCGR1, 0x5b); 496 reg_write(encoder, REG_PLL_SCGR2, 0x00); 497 reg_write(encoder, REG_PLL_SCG2, 0x10); 498 499 /* Write the default value MUX register */ 500 reg_write(encoder, REG_MUX_VP_VIP_OUT, 0x24); 501 } 502 503 static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes) 504 { 505 uint8_t sum = 0; 506 507 while (bytes--) 508 sum += *buf++; 509 return (255 - sum) + 1; 510 } 511 512 #define HB(x) (x) 513 #define PB(x) (HB(2) + 1 + (x)) 514 515 static void 516 tda998x_write_if(struct drm_encoder *encoder, uint8_t bit, uint16_t addr, 517 uint8_t *buf, size_t size) 518 { 519 buf[PB(0)] = tda998x_cksum(buf, size); 520 521 reg_clear(encoder, REG_DIP_IF_FLAGS, bit); 522 reg_write_range(encoder, addr, buf, size); 523 reg_set(encoder, REG_DIP_IF_FLAGS, bit); 524 } 525 526 static void 527 tda998x_write_aif(struct drm_encoder *encoder, struct tda998x_encoder_params *p) 528 { 529 uint8_t buf[PB(5) + 1]; 530 531 memset(buf, 0, sizeof(buf)); 532 buf[HB(0)] = 0x84; 533 buf[HB(1)] = 0x01; 534 buf[HB(2)] = 10; 535 buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */ 536 buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */ 537 buf[PB(4)] = p->audio_frame[4]; 538 buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */ 539 540 tda998x_write_if(encoder, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf, 541 sizeof(buf)); 542 } 543 544 static void 545 tda998x_write_avi(struct drm_encoder *encoder, struct drm_display_mode *mode) 546 { 547 uint8_t buf[PB(13) + 1]; 548 549 memset(buf, 0, sizeof(buf)); 550 buf[HB(0)] = 0x82; 551 buf[HB(1)] = 0x02; 552 buf[HB(2)] = 13; 553 buf[PB(1)] = HDMI_SCAN_MODE_UNDERSCAN; 554 buf[PB(3)] = HDMI_QUANTIZATION_RANGE_FULL << 2; 555 buf[PB(4)] = drm_match_cea_mode(mode); 556 557 tda998x_write_if(encoder, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, 558 sizeof(buf)); 559 } 560 561 static void tda998x_audio_mute(struct drm_encoder *encoder, bool on) 562 { 563 if (on) { 564 reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO); 565 reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO); 566 reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 567 } else { 568 reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 569 } 570 } 571 572 static void 573 tda998x_configure_audio(struct drm_encoder *encoder, 574 struct drm_display_mode *mode, struct tda998x_encoder_params *p) 575 { 576 uint8_t buf[6], clksel_aip, clksel_fs, ca_i2s, cts_n, adiv; 577 uint32_t n; 578 579 /* Enable audio ports */ 580 reg_write(encoder, REG_ENA_AP, p->audio_cfg); 581 reg_write(encoder, REG_ENA_ACLK, p->audio_clk_cfg); 582 583 /* Set audio input source */ 584 switch (p->audio_format) { 585 case AFMT_SPDIF: 586 reg_write(encoder, REG_MUX_AP, 0x40); 587 clksel_aip = AIP_CLKSEL_AIP(0); 588 /* FS64SPDIF */ 589 clksel_fs = AIP_CLKSEL_FS(2); 590 cts_n = CTS_N_M(3) | CTS_N_K(3); 591 ca_i2s = 0; 592 break; 593 594 case AFMT_I2S: 595 reg_write(encoder, REG_MUX_AP, 0x64); 596 clksel_aip = AIP_CLKSEL_AIP(1); 597 /* ACLK */ 598 clksel_fs = AIP_CLKSEL_FS(0); 599 cts_n = CTS_N_M(3) | CTS_N_K(3); 600 ca_i2s = CA_I2S_CA_I2S(0); 601 break; 602 603 default: 604 BUG(); 605 return; 606 } 607 608 reg_write(encoder, REG_AIP_CLKSEL, clksel_aip); 609 reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT); 610 611 /* Enable automatic CTS generation */ 612 reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_ACR_MAN); 613 reg_write(encoder, REG_CTS_N, cts_n); 614 615 /* 616 * Audio input somehow depends on HDMI line rate which is 617 * related to pixclk. Testing showed that modes with pixclk 618 * >100MHz need a larger divider while <40MHz need the default. 619 * There is no detailed info in the datasheet, so we just 620 * assume 100MHz requires larger divider. 621 */ 622 if (mode->clock > 100000) 623 adiv = AUDIO_DIV_SERCLK_16; 624 else 625 adiv = AUDIO_DIV_SERCLK_8; 626 reg_write(encoder, REG_AUDIO_DIV, adiv); 627 628 /* 629 * This is the approximate value of N, which happens to be 630 * the recommended values for non-coherent clocks. 631 */ 632 n = 128 * p->audio_sample_rate / 1000; 633 634 /* Write the CTS and N values */ 635 buf[0] = 0x44; 636 buf[1] = 0x42; 637 buf[2] = 0x01; 638 buf[3] = n; 639 buf[4] = n >> 8; 640 buf[5] = n >> 16; 641 reg_write_range(encoder, REG_ACR_CTS_0, buf, 6); 642 643 /* Set CTS clock reference */ 644 reg_write(encoder, REG_AIP_CLKSEL, clksel_aip | clksel_fs); 645 646 /* Reset CTS generator */ 647 reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 648 reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 649 650 /* Write the channel status */ 651 buf[0] = 0x04; 652 buf[1] = 0x00; 653 buf[2] = 0x00; 654 buf[3] = 0xf1; 655 reg_write_range(encoder, REG_CH_STAT_B(0), buf, 4); 656 657 tda998x_audio_mute(encoder, true); 658 mdelay(20); 659 tda998x_audio_mute(encoder, false); 660 661 /* Write the audio information packet */ 662 tda998x_write_aif(encoder, p); 663 } 664 665 /* DRM encoder functions */ 666 667 static void 668 tda998x_encoder_set_config(struct drm_encoder *encoder, void *params) 669 { 670 struct tda998x_priv *priv = to_tda998x_priv(encoder); 671 struct tda998x_encoder_params *p = params; 672 673 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | 674 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | 675 VIP_CNTRL_0_SWAP_B(p->swap_b) | 676 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); 677 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | 678 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | 679 VIP_CNTRL_1_SWAP_D(p->swap_d) | 680 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); 681 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | 682 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | 683 VIP_CNTRL_2_SWAP_F(p->swap_f) | 684 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); 685 686 priv->params = *p; 687 } 688 689 static void 690 tda998x_encoder_dpms(struct drm_encoder *encoder, int mode) 691 { 692 struct tda998x_priv *priv = to_tda998x_priv(encoder); 693 694 /* we only care about on or off: */ 695 if (mode != DRM_MODE_DPMS_ON) 696 mode = DRM_MODE_DPMS_OFF; 697 698 if (mode == priv->dpms) 699 return; 700 701 switch (mode) { 702 case DRM_MODE_DPMS_ON: 703 /* enable video ports, audio will be enabled later */ 704 reg_write(encoder, REG_ENA_VP_0, 0xff); 705 reg_write(encoder, REG_ENA_VP_1, 0xff); 706 reg_write(encoder, REG_ENA_VP_2, 0xff); 707 /* set muxing after enabling ports: */ 708 reg_write(encoder, REG_VIP_CNTRL_0, priv->vip_cntrl_0); 709 reg_write(encoder, REG_VIP_CNTRL_1, priv->vip_cntrl_1); 710 reg_write(encoder, REG_VIP_CNTRL_2, priv->vip_cntrl_2); 711 break; 712 case DRM_MODE_DPMS_OFF: 713 /* disable video ports */ 714 reg_write(encoder, REG_ENA_VP_0, 0x00); 715 reg_write(encoder, REG_ENA_VP_1, 0x00); 716 reg_write(encoder, REG_ENA_VP_2, 0x00); 717 break; 718 } 719 720 priv->dpms = mode; 721 } 722 723 static void 724 tda998x_encoder_save(struct drm_encoder *encoder) 725 { 726 DBG(""); 727 } 728 729 static void 730 tda998x_encoder_restore(struct drm_encoder *encoder) 731 { 732 DBG(""); 733 } 734 735 static bool 736 tda998x_encoder_mode_fixup(struct drm_encoder *encoder, 737 const struct drm_display_mode *mode, 738 struct drm_display_mode *adjusted_mode) 739 { 740 return true; 741 } 742 743 static int 744 tda998x_encoder_mode_valid(struct drm_encoder *encoder, 745 struct drm_display_mode *mode) 746 { 747 return MODE_OK; 748 } 749 750 static void 751 tda998x_encoder_mode_set(struct drm_encoder *encoder, 752 struct drm_display_mode *mode, 753 struct drm_display_mode *adjusted_mode) 754 { 755 struct tda998x_priv *priv = to_tda998x_priv(encoder); 756 uint16_t ref_pix, ref_line, n_pix, n_line; 757 uint16_t hs_pix_s, hs_pix_e; 758 uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e; 759 uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e; 760 uint16_t vwin1_line_s, vwin1_line_e; 761 uint16_t vwin2_line_s, vwin2_line_e; 762 uint16_t de_pix_s, de_pix_e; 763 uint8_t reg, div, rep; 764 765 /* 766 * Internally TDA998x is using ITU-R BT.656 style sync but 767 * we get VESA style sync. TDA998x is using a reference pixel 768 * relative to ITU to sync to the input frame and for output 769 * sync generation. Currently, we are using reference detection 770 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point 771 * which is position of rising VS with coincident rising HS. 772 * 773 * Now there is some issues to take care of: 774 * - HDMI data islands require sync-before-active 775 * - TDA998x register values must be > 0 to be enabled 776 * - REFLINE needs an additional offset of +1 777 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB 778 * 779 * So we add +1 to all horizontal and vertical register values, 780 * plus an additional +3 for REFPIX as we are using RGB input only. 781 */ 782 n_pix = mode->htotal; 783 n_line = mode->vtotal; 784 785 hs_pix_e = mode->hsync_end - mode->hdisplay; 786 hs_pix_s = mode->hsync_start - mode->hdisplay; 787 de_pix_e = mode->htotal; 788 de_pix_s = mode->htotal - mode->hdisplay; 789 ref_pix = 3 + hs_pix_s; 790 791 /* 792 * Attached LCD controllers may generate broken sync. Allow 793 * those to adjust the position of the rising VS edge by adding 794 * HSKEW to ref_pix. 795 */ 796 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) 797 ref_pix += adjusted_mode->hskew; 798 799 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { 800 ref_line = 1 + mode->vsync_start - mode->vdisplay; 801 vwin1_line_s = mode->vtotal - mode->vdisplay - 1; 802 vwin1_line_e = vwin1_line_s + mode->vdisplay; 803 vs1_pix_s = vs1_pix_e = hs_pix_s; 804 vs1_line_s = mode->vsync_start - mode->vdisplay; 805 vs1_line_e = vs1_line_s + 806 mode->vsync_end - mode->vsync_start; 807 vwin2_line_s = vwin2_line_e = 0; 808 vs2_pix_s = vs2_pix_e = 0; 809 vs2_line_s = vs2_line_e = 0; 810 } else { 811 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; 812 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; 813 vwin1_line_e = vwin1_line_s + mode->vdisplay/2; 814 vs1_pix_s = vs1_pix_e = hs_pix_s; 815 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; 816 vs1_line_e = vs1_line_s + 817 (mode->vsync_end - mode->vsync_start)/2; 818 vwin2_line_s = vwin1_line_s + mode->vtotal/2; 819 vwin2_line_e = vwin2_line_s + mode->vdisplay/2; 820 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; 821 vs2_line_s = vs1_line_s + mode->vtotal/2 ; 822 vs2_line_e = vs2_line_s + 823 (mode->vsync_end - mode->vsync_start)/2; 824 } 825 826 div = 148500 / mode->clock; 827 if (div != 0) { 828 div--; 829 if (div > 3) 830 div = 3; 831 } 832 833 /* mute the audio FIFO: */ 834 reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 835 836 /* set HDMI HDCP mode off: */ 837 reg_set(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 838 reg_clear(encoder, REG_TX33, TX33_HDMI); 839 840 reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); 841 /* no pre-filter or interpolator: */ 842 reg_write(encoder, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | 843 HVF_CNTRL_0_INTPOL(0)); 844 reg_write(encoder, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); 845 reg_write(encoder, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | 846 VIP_CNTRL_4_BLC(0)); 847 reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR); 848 849 reg_clear(encoder, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); 850 reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); 851 reg_write(encoder, REG_SERIALIZER, 0); 852 reg_write(encoder, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); 853 854 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */ 855 rep = 0; 856 reg_write(encoder, REG_RPT_CNTRL, 0); 857 reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | 858 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 859 860 reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | 861 PLL_SERIAL_2_SRL_PR(rep)); 862 863 /* set color matrix bypass flag: */ 864 reg_set(encoder, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP); 865 866 /* set BIAS tmds value: */ 867 reg_write(encoder, REG_ANA_GENERAL, 0x09); 868 869 reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); 870 871 /* 872 * Sync on rising HSYNC/VSYNC 873 */ 874 reg_write(encoder, REG_VIP_CNTRL_3, 0); 875 reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS); 876 877 /* 878 * TDA19988 requires high-active sync at input stage, 879 * so invert low-active sync provided by master encoder here 880 */ 881 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 882 reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL); 883 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 884 reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL); 885 886 /* 887 * Always generate sync polarity relative to input sync and 888 * revert input stage toggled sync at output stage 889 */ 890 reg = TBG_CNTRL_1_TGL_EN; 891 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 892 reg |= TBG_CNTRL_1_H_TGL; 893 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 894 reg |= TBG_CNTRL_1_V_TGL; 895 reg_write(encoder, REG_TBG_CNTRL_1, reg); 896 897 reg_write(encoder, REG_VIDFORMAT, 0x00); 898 reg_write16(encoder, REG_REFPIX_MSB, ref_pix); 899 reg_write16(encoder, REG_REFLINE_MSB, ref_line); 900 reg_write16(encoder, REG_NPIX_MSB, n_pix); 901 reg_write16(encoder, REG_NLINE_MSB, n_line); 902 reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, vs1_line_s); 903 reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, vs1_pix_s); 904 reg_write16(encoder, REG_VS_LINE_END_1_MSB, vs1_line_e); 905 reg_write16(encoder, REG_VS_PIX_END_1_MSB, vs1_pix_e); 906 reg_write16(encoder, REG_VS_LINE_STRT_2_MSB, vs2_line_s); 907 reg_write16(encoder, REG_VS_PIX_STRT_2_MSB, vs2_pix_s); 908 reg_write16(encoder, REG_VS_LINE_END_2_MSB, vs2_line_e); 909 reg_write16(encoder, REG_VS_PIX_END_2_MSB, vs2_pix_e); 910 reg_write16(encoder, REG_HS_PIX_START_MSB, hs_pix_s); 911 reg_write16(encoder, REG_HS_PIX_STOP_MSB, hs_pix_e); 912 reg_write16(encoder, REG_VWIN_START_1_MSB, vwin1_line_s); 913 reg_write16(encoder, REG_VWIN_END_1_MSB, vwin1_line_e); 914 reg_write16(encoder, REG_VWIN_START_2_MSB, vwin2_line_s); 915 reg_write16(encoder, REG_VWIN_END_2_MSB, vwin2_line_e); 916 reg_write16(encoder, REG_DE_START_MSB, de_pix_s); 917 reg_write16(encoder, REG_DE_STOP_MSB, de_pix_e); 918 919 if (priv->rev == TDA19988) { 920 /* let incoming pixels fill the active space (if any) */ 921 reg_write(encoder, REG_ENABLE_SPACE, 0x00); 922 } 923 924 /* must be last register set: */ 925 reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); 926 927 /* Only setup the info frames if the sink is HDMI */ 928 if (priv->is_hdmi_sink) { 929 /* We need to turn HDMI HDCP stuff on to get audio through */ 930 reg_clear(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 931 reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); 932 reg_set(encoder, REG_TX33, TX33_HDMI); 933 934 tda998x_write_avi(encoder, adjusted_mode); 935 936 if (priv->params.audio_cfg) 937 tda998x_configure_audio(encoder, adjusted_mode, 938 &priv->params); 939 } 940 } 941 942 static enum drm_connector_status 943 tda998x_encoder_detect(struct drm_encoder *encoder, 944 struct drm_connector *connector) 945 { 946 uint8_t val = cec_read(encoder, REG_CEC_RXSHPDLEV); 947 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : 948 connector_status_disconnected; 949 } 950 951 static int 952 read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk) 953 { 954 uint8_t offset, segptr; 955 int ret, i; 956 957 /* enable EDID read irq: */ 958 reg_set(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 959 960 offset = (blk & 1) ? 128 : 0; 961 segptr = blk / 2; 962 963 reg_write(encoder, REG_DDC_ADDR, 0xa0); 964 reg_write(encoder, REG_DDC_OFFS, offset); 965 reg_write(encoder, REG_DDC_SEGM_ADDR, 0x60); 966 reg_write(encoder, REG_DDC_SEGM, segptr); 967 968 /* enable reading EDID: */ 969 reg_write(encoder, REG_EDID_CTRL, 0x1); 970 971 /* flag must be cleared by sw: */ 972 reg_write(encoder, REG_EDID_CTRL, 0x0); 973 974 /* wait for block read to complete: */ 975 for (i = 100; i > 0; i--) { 976 uint8_t val = reg_read(encoder, REG_INT_FLAGS_2); 977 if (val & INT_FLAGS_2_EDID_BLK_RD) 978 break; 979 msleep(1); 980 } 981 982 if (i == 0) 983 return -ETIMEDOUT; 984 985 ret = reg_read_range(encoder, REG_EDID_DATA_0, buf, EDID_LENGTH); 986 if (ret != EDID_LENGTH) { 987 dev_err(encoder->dev->dev, "failed to read edid block %d: %d", 988 blk, ret); 989 return ret; 990 } 991 992 reg_clear(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 993 994 return 0; 995 } 996 997 static uint8_t * 998 do_get_edid(struct drm_encoder *encoder) 999 { 1000 struct tda998x_priv *priv = to_tda998x_priv(encoder); 1001 int j = 0, valid_extensions = 0; 1002 uint8_t *block, *new; 1003 bool print_bad_edid = drm_debug & DRM_UT_KMS; 1004 1005 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1006 return NULL; 1007 1008 if (priv->rev == TDA19988) 1009 reg_clear(encoder, REG_TX4, TX4_PD_RAM); 1010 1011 /* base block fetch */ 1012 if (read_edid_block(encoder, block, 0)) 1013 goto fail; 1014 1015 if (!drm_edid_block_valid(block, 0, print_bad_edid)) 1016 goto fail; 1017 1018 /* if there's no extensions, we're done */ 1019 if (block[0x7e] == 0) 1020 goto done; 1021 1022 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 1023 if (!new) 1024 goto fail; 1025 block = new; 1026 1027 for (j = 1; j <= block[0x7e]; j++) { 1028 uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH; 1029 if (read_edid_block(encoder, ext_block, j)) 1030 goto fail; 1031 1032 if (!drm_edid_block_valid(ext_block, j, print_bad_edid)) 1033 goto fail; 1034 1035 valid_extensions++; 1036 } 1037 1038 if (valid_extensions != block[0x7e]) { 1039 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1040 block[0x7e] = valid_extensions; 1041 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1042 if (!new) 1043 goto fail; 1044 block = new; 1045 } 1046 1047 done: 1048 if (priv->rev == TDA19988) 1049 reg_set(encoder, REG_TX4, TX4_PD_RAM); 1050 1051 return block; 1052 1053 fail: 1054 if (priv->rev == TDA19988) 1055 reg_set(encoder, REG_TX4, TX4_PD_RAM); 1056 dev_warn(encoder->dev->dev, "failed to read EDID\n"); 1057 kfree(block); 1058 return NULL; 1059 } 1060 1061 static int 1062 tda998x_encoder_get_modes(struct drm_encoder *encoder, 1063 struct drm_connector *connector) 1064 { 1065 struct tda998x_priv *priv = to_tda998x_priv(encoder); 1066 struct edid *edid = (struct edid *)do_get_edid(encoder); 1067 int n = 0; 1068 1069 if (edid) { 1070 drm_mode_connector_update_edid_property(connector, edid); 1071 n = drm_add_edid_modes(connector, edid); 1072 priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid); 1073 kfree(edid); 1074 } 1075 1076 return n; 1077 } 1078 1079 static int 1080 tda998x_encoder_create_resources(struct drm_encoder *encoder, 1081 struct drm_connector *connector) 1082 { 1083 DBG(""); 1084 return 0; 1085 } 1086 1087 static int 1088 tda998x_encoder_set_property(struct drm_encoder *encoder, 1089 struct drm_connector *connector, 1090 struct drm_property *property, 1091 uint64_t val) 1092 { 1093 DBG(""); 1094 return 0; 1095 } 1096 1097 static void 1098 tda998x_encoder_destroy(struct drm_encoder *encoder) 1099 { 1100 struct tda998x_priv *priv = to_tda998x_priv(encoder); 1101 drm_i2c_encoder_destroy(encoder); 1102 if (priv->cec) 1103 i2c_unregister_device(priv->cec); 1104 kfree(priv); 1105 } 1106 1107 static struct drm_encoder_slave_funcs tda998x_encoder_funcs = { 1108 .set_config = tda998x_encoder_set_config, 1109 .destroy = tda998x_encoder_destroy, 1110 .dpms = tda998x_encoder_dpms, 1111 .save = tda998x_encoder_save, 1112 .restore = tda998x_encoder_restore, 1113 .mode_fixup = tda998x_encoder_mode_fixup, 1114 .mode_valid = tda998x_encoder_mode_valid, 1115 .mode_set = tda998x_encoder_mode_set, 1116 .detect = tda998x_encoder_detect, 1117 .get_modes = tda998x_encoder_get_modes, 1118 .create_resources = tda998x_encoder_create_resources, 1119 .set_property = tda998x_encoder_set_property, 1120 }; 1121 1122 /* I2C driver functions */ 1123 1124 static int 1125 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) 1126 { 1127 return 0; 1128 } 1129 1130 static int 1131 tda998x_remove(struct i2c_client *client) 1132 { 1133 return 0; 1134 } 1135 1136 static int 1137 tda998x_encoder_init(struct i2c_client *client, 1138 struct drm_device *dev, 1139 struct drm_encoder_slave *encoder_slave) 1140 { 1141 struct drm_encoder *encoder = &encoder_slave->base; 1142 struct tda998x_priv *priv; 1143 1144 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 1145 if (!priv) 1146 return -ENOMEM; 1147 1148 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); 1149 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); 1150 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); 1151 1152 priv->current_page = 0xff; 1153 priv->cec = i2c_new_dummy(client->adapter, 0x34); 1154 if (!priv->cec) 1155 return -ENODEV; 1156 priv->dpms = DRM_MODE_DPMS_OFF; 1157 1158 encoder_slave->slave_priv = priv; 1159 encoder_slave->slave_funcs = &tda998x_encoder_funcs; 1160 1161 /* wake up the device: */ 1162 cec_write(encoder, REG_CEC_ENAMODS, 1163 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); 1164 1165 tda998x_reset(encoder); 1166 1167 /* read version: */ 1168 priv->rev = reg_read(encoder, REG_VERSION_LSB) | 1169 reg_read(encoder, REG_VERSION_MSB) << 8; 1170 1171 /* mask off feature bits: */ 1172 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ 1173 1174 switch (priv->rev) { 1175 case TDA9989N2: dev_info(dev->dev, "found TDA9989 n2"); break; 1176 case TDA19989: dev_info(dev->dev, "found TDA19989"); break; 1177 case TDA19989N2: dev_info(dev->dev, "found TDA19989 n2"); break; 1178 case TDA19988: dev_info(dev->dev, "found TDA19988"); break; 1179 default: 1180 DBG("found unsupported device: %04x", priv->rev); 1181 goto fail; 1182 } 1183 1184 /* after reset, enable DDC: */ 1185 reg_write(encoder, REG_DDC_DISABLE, 0x00); 1186 1187 /* set clock on DDC channel: */ 1188 reg_write(encoder, REG_TX3, 39); 1189 1190 /* if necessary, disable multi-master: */ 1191 if (priv->rev == TDA19989) 1192 reg_set(encoder, REG_I2C_MASTER, I2C_MASTER_DIS_MM); 1193 1194 cec_write(encoder, REG_CEC_FRO_IM_CLK_CTRL, 1195 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); 1196 1197 return 0; 1198 1199 fail: 1200 /* if encoder_init fails, the encoder slave is never registered, 1201 * so cleanup here: 1202 */ 1203 if (priv->cec) 1204 i2c_unregister_device(priv->cec); 1205 kfree(priv); 1206 encoder_slave->slave_priv = NULL; 1207 encoder_slave->slave_funcs = NULL; 1208 return -ENXIO; 1209 } 1210 1211 static struct i2c_device_id tda998x_ids[] = { 1212 { "tda998x", 0 }, 1213 { } 1214 }; 1215 MODULE_DEVICE_TABLE(i2c, tda998x_ids); 1216 1217 static struct drm_i2c_encoder_driver tda998x_driver = { 1218 .i2c_driver = { 1219 .probe = tda998x_probe, 1220 .remove = tda998x_remove, 1221 .driver = { 1222 .name = "tda998x", 1223 }, 1224 .id_table = tda998x_ids, 1225 }, 1226 .encoder_init = tda998x_encoder_init, 1227 }; 1228 1229 /* Module initialization */ 1230 1231 static int __init 1232 tda998x_init(void) 1233 { 1234 DBG(""); 1235 return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver); 1236 } 1237 1238 static void __exit 1239 tda998x_exit(void) 1240 { 1241 DBG(""); 1242 drm_i2c_encoder_unregister(&tda998x_driver); 1243 } 1244 1245 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1246 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); 1247 MODULE_LICENSE("GPL"); 1248 1249 module_init(tda998x_init); 1250 module_exit(tda998x_exit); 1251