1 /* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include <linux/component.h> 19 #include <linux/hdmi.h> 20 #include <linux/module.h> 21 #include <linux/irq.h> 22 #include <sound/asoundef.h> 23 24 #include <drm/drmP.h> 25 #include <drm/drm_crtc_helper.h> 26 #include <drm/drm_edid.h> 27 #include <drm/drm_of.h> 28 #include <drm/i2c/tda998x.h> 29 30 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 31 32 struct tda998x_priv { 33 struct i2c_client *cec; 34 struct i2c_client *hdmi; 35 struct mutex mutex; 36 u16 rev; 37 u8 current_page; 38 int dpms; 39 bool is_hdmi_sink; 40 u8 vip_cntrl_0; 41 u8 vip_cntrl_1; 42 u8 vip_cntrl_2; 43 struct tda998x_encoder_params params; 44 45 wait_queue_head_t wq_edid; 46 volatile int wq_edid_wait; 47 48 struct work_struct detect_work; 49 struct timer_list edid_delay_timer; 50 wait_queue_head_t edid_delay_waitq; 51 bool edid_delay_active; 52 53 struct drm_encoder encoder; 54 struct drm_connector connector; 55 }; 56 57 #define conn_to_tda998x_priv(x) \ 58 container_of(x, struct tda998x_priv, connector) 59 60 #define enc_to_tda998x_priv(x) \ 61 container_of(x, struct tda998x_priv, encoder) 62 63 /* The TDA9988 series of devices use a paged register scheme.. to simplify 64 * things we encode the page # in upper bits of the register #. To read/ 65 * write a given register, we need to make sure CURPAGE register is set 66 * appropriately. Which implies reads/writes are not atomic. Fun! 67 */ 68 69 #define REG(page, addr) (((page) << 8) | (addr)) 70 #define REG2ADDR(reg) ((reg) & 0xff) 71 #define REG2PAGE(reg) (((reg) >> 8) & 0xff) 72 73 #define REG_CURPAGE 0xff /* write */ 74 75 76 /* Page 00h: General Control */ 77 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */ 78 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ 79 # define MAIN_CNTRL0_SR (1 << 0) 80 # define MAIN_CNTRL0_DECS (1 << 1) 81 # define MAIN_CNTRL0_DEHS (1 << 2) 82 # define MAIN_CNTRL0_CECS (1 << 3) 83 # define MAIN_CNTRL0_CEHS (1 << 4) 84 # define MAIN_CNTRL0_SCALER (1 << 7) 85 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */ 86 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ 87 # define SOFTRESET_AUDIO (1 << 0) 88 # define SOFTRESET_I2C_MASTER (1 << 1) 89 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ 90 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ 91 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ 92 # define I2C_MASTER_DIS_MM (1 << 0) 93 # define I2C_MASTER_DIS_FILT (1 << 1) 94 # define I2C_MASTER_APP_STRT_LAT (1 << 2) 95 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ 96 # define FEAT_POWERDOWN_SPDIF (1 << 3) 97 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ 98 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ 99 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ 100 # define INT_FLAGS_2_EDID_BLK_RD (1 << 1) 101 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ 102 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ 103 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ 104 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ 105 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ 106 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ 107 # define VIP_CNTRL_0_MIRR_A (1 << 7) 108 # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) 109 # define VIP_CNTRL_0_MIRR_B (1 << 3) 110 # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) 111 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ 112 # define VIP_CNTRL_1_MIRR_C (1 << 7) 113 # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) 114 # define VIP_CNTRL_1_MIRR_D (1 << 3) 115 # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) 116 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ 117 # define VIP_CNTRL_2_MIRR_E (1 << 7) 118 # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) 119 # define VIP_CNTRL_2_MIRR_F (1 << 3) 120 # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) 121 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ 122 # define VIP_CNTRL_3_X_TGL (1 << 0) 123 # define VIP_CNTRL_3_H_TGL (1 << 1) 124 # define VIP_CNTRL_3_V_TGL (1 << 2) 125 # define VIP_CNTRL_3_EMB (1 << 3) 126 # define VIP_CNTRL_3_SYNC_DE (1 << 4) 127 # define VIP_CNTRL_3_SYNC_HS (1 << 5) 128 # define VIP_CNTRL_3_DE_INT (1 << 6) 129 # define VIP_CNTRL_3_EDGE (1 << 7) 130 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ 131 # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) 132 # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) 133 # define VIP_CNTRL_4_CCIR656 (1 << 4) 134 # define VIP_CNTRL_4_656_ALT (1 << 5) 135 # define VIP_CNTRL_4_TST_656 (1 << 6) 136 # define VIP_CNTRL_4_TST_PAT (1 << 7) 137 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ 138 # define VIP_CNTRL_5_CKCASE (1 << 0) 139 # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) 140 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */ 141 # define MUX_AP_SELECT_I2S 0x64 142 # define MUX_AP_SELECT_SPDIF 0x40 143 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ 144 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ 145 # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) 146 # define MAT_CONTRL_MAT_BP (1 << 2) 147 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ 148 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ 149 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ 150 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ 151 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ 152 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ 153 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ 154 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ 155 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ 156 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ 157 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ 158 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ 159 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ 160 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ 161 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ 162 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ 163 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ 164 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ 165 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ 166 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ 167 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ 168 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ 169 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ 170 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ 171 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ 172 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ 173 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ 174 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ 175 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ 176 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ 177 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ 178 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ 179 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ 180 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ 181 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ 182 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ 183 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ 184 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ 185 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ 186 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ 187 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ 188 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ 189 # define TBG_CNTRL_0_TOP_TGL (1 << 0) 190 # define TBG_CNTRL_0_TOP_SEL (1 << 1) 191 # define TBG_CNTRL_0_DE_EXT (1 << 2) 192 # define TBG_CNTRL_0_TOP_EXT (1 << 3) 193 # define TBG_CNTRL_0_FRAME_DIS (1 << 5) 194 # define TBG_CNTRL_0_SYNC_MTHD (1 << 6) 195 # define TBG_CNTRL_0_SYNC_ONCE (1 << 7) 196 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ 197 # define TBG_CNTRL_1_H_TGL (1 << 0) 198 # define TBG_CNTRL_1_V_TGL (1 << 1) 199 # define TBG_CNTRL_1_TGL_EN (1 << 2) 200 # define TBG_CNTRL_1_X_EXT (1 << 3) 201 # define TBG_CNTRL_1_H_EXT (1 << 4) 202 # define TBG_CNTRL_1_V_EXT (1 << 5) 203 # define TBG_CNTRL_1_DWIN_DIS (1 << 6) 204 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ 205 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ 206 # define HVF_CNTRL_0_SM (1 << 7) 207 # define HVF_CNTRL_0_RWB (1 << 6) 208 # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) 209 # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) 210 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ 211 # define HVF_CNTRL_1_FOR (1 << 0) 212 # define HVF_CNTRL_1_YUVBLK (1 << 1) 213 # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) 214 # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) 215 # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) 216 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ 217 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ 218 # define I2S_FORMAT(x) (((x) & 3) << 0) 219 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ 220 # define AIP_CLKSEL_AIP_SPDIF (0 << 3) 221 # define AIP_CLKSEL_AIP_I2S (1 << 3) 222 # define AIP_CLKSEL_FS_ACLK (0 << 0) 223 # define AIP_CLKSEL_FS_MCLK (1 << 0) 224 # define AIP_CLKSEL_FS_FS64SPDIF (2 << 0) 225 226 /* Page 02h: PLL settings */ 227 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ 228 # define PLL_SERIAL_1_SRL_FDN (1 << 0) 229 # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) 230 # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) 231 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ 232 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0) 233 # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) 234 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ 235 # define PLL_SERIAL_3_SRL_CCIR (1 << 0) 236 # define PLL_SERIAL_3_SRL_DE (1 << 2) 237 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) 238 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ 239 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ 240 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ 241 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ 242 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ 243 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ 244 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ 245 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ 246 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ 247 # define AUDIO_DIV_SERCLK_1 0 248 # define AUDIO_DIV_SERCLK_2 1 249 # define AUDIO_DIV_SERCLK_4 2 250 # define AUDIO_DIV_SERCLK_8 3 251 # define AUDIO_DIV_SERCLK_16 4 252 # define AUDIO_DIV_SERCLK_32 5 253 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ 254 # define SEL_CLK_SEL_CLK1 (1 << 0) 255 # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) 256 # define SEL_CLK_ENA_SC_CLK (1 << 3) 257 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ 258 259 260 /* Page 09h: EDID Control */ 261 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ 262 /* next 127 successive registers are the EDID block */ 263 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ 264 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ 265 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ 266 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ 267 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ 268 269 270 /* Page 10h: information frames and packets */ 271 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ 272 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ 273 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ 274 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ 275 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ 276 277 278 /* Page 11h: audio settings and content info packets */ 279 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ 280 # define AIP_CNTRL_0_RST_FIFO (1 << 0) 281 # define AIP_CNTRL_0_SWAP (1 << 1) 282 # define AIP_CNTRL_0_LAYOUT (1 << 2) 283 # define AIP_CNTRL_0_ACR_MAN (1 << 5) 284 # define AIP_CNTRL_0_RST_CTS (1 << 6) 285 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */ 286 # define CA_I2S_CA_I2S(x) (((x) & 31) << 0) 287 # define CA_I2S_HBR_CHSTAT (1 << 6) 288 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ 289 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ 290 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ 291 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ 292 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ 293 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ 294 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ 295 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */ 296 # define CTS_N_K(x) (((x) & 7) << 0) 297 # define CTS_N_M(x) (((x) & 3) << 4) 298 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ 299 # define ENC_CNTRL_RST_ENC (1 << 0) 300 # define ENC_CNTRL_RST_SEL (1 << 1) 301 # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) 302 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ 303 # define DIP_FLAGS_ACR (1 << 0) 304 # define DIP_FLAGS_GC (1 << 1) 305 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ 306 # define DIP_IF_FLAGS_IF1 (1 << 1) 307 # define DIP_IF_FLAGS_IF2 (1 << 2) 308 # define DIP_IF_FLAGS_IF3 (1 << 3) 309 # define DIP_IF_FLAGS_IF4 (1 << 4) 310 # define DIP_IF_FLAGS_IF5 (1 << 5) 311 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ 312 313 314 /* Page 12h: HDCP and OTP */ 315 #define REG_TX3 REG(0x12, 0x9a) /* read/write */ 316 #define REG_TX4 REG(0x12, 0x9b) /* read/write */ 317 # define TX4_PD_RAM (1 << 1) 318 #define REG_TX33 REG(0x12, 0xb8) /* read/write */ 319 # define TX33_HDMI (1 << 1) 320 321 322 /* Page 13h: Gamut related metadata packets */ 323 324 325 326 /* CEC registers: (not paged) 327 */ 328 #define REG_CEC_INTSTATUS 0xee /* read */ 329 # define CEC_INTSTATUS_CEC (1 << 0) 330 # define CEC_INTSTATUS_HDMI (1 << 1) 331 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ 332 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) 333 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) 334 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) 335 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) 336 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */ 337 #define REG_CEC_RXSHPDINT 0xfd /* read */ 338 # define CEC_RXSHPDINT_RXSENS BIT(0) 339 # define CEC_RXSHPDINT_HPD BIT(1) 340 #define REG_CEC_RXSHPDLEV 0xfe /* read */ 341 # define CEC_RXSHPDLEV_RXSENS (1 << 0) 342 # define CEC_RXSHPDLEV_HPD (1 << 1) 343 344 #define REG_CEC_ENAMODS 0xff /* read/write */ 345 # define CEC_ENAMODS_DIS_FRO (1 << 6) 346 # define CEC_ENAMODS_DIS_CCLK (1 << 5) 347 # define CEC_ENAMODS_EN_RXSENS (1 << 2) 348 # define CEC_ENAMODS_EN_HDMI (1 << 1) 349 # define CEC_ENAMODS_EN_CEC (1 << 0) 350 351 352 /* Device versions: */ 353 #define TDA9989N2 0x0101 354 #define TDA19989 0x0201 355 #define TDA19989N2 0x0202 356 #define TDA19988 0x0301 357 358 static void 359 cec_write(struct tda998x_priv *priv, u16 addr, u8 val) 360 { 361 struct i2c_client *client = priv->cec; 362 u8 buf[] = {addr, val}; 363 int ret; 364 365 ret = i2c_master_send(client, buf, sizeof(buf)); 366 if (ret < 0) 367 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr); 368 } 369 370 static u8 371 cec_read(struct tda998x_priv *priv, u8 addr) 372 { 373 struct i2c_client *client = priv->cec; 374 u8 val; 375 int ret; 376 377 ret = i2c_master_send(client, &addr, sizeof(addr)); 378 if (ret < 0) 379 goto fail; 380 381 ret = i2c_master_recv(client, &val, sizeof(val)); 382 if (ret < 0) 383 goto fail; 384 385 return val; 386 387 fail: 388 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr); 389 return 0; 390 } 391 392 static int 393 set_page(struct tda998x_priv *priv, u16 reg) 394 { 395 if (REG2PAGE(reg) != priv->current_page) { 396 struct i2c_client *client = priv->hdmi; 397 u8 buf[] = { 398 REG_CURPAGE, REG2PAGE(reg) 399 }; 400 int ret = i2c_master_send(client, buf, sizeof(buf)); 401 if (ret < 0) { 402 dev_err(&client->dev, "%s %04x err %d\n", __func__, 403 reg, ret); 404 return ret; 405 } 406 407 priv->current_page = REG2PAGE(reg); 408 } 409 return 0; 410 } 411 412 static int 413 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt) 414 { 415 struct i2c_client *client = priv->hdmi; 416 u8 addr = REG2ADDR(reg); 417 int ret; 418 419 mutex_lock(&priv->mutex); 420 ret = set_page(priv, reg); 421 if (ret < 0) 422 goto out; 423 424 ret = i2c_master_send(client, &addr, sizeof(addr)); 425 if (ret < 0) 426 goto fail; 427 428 ret = i2c_master_recv(client, buf, cnt); 429 if (ret < 0) 430 goto fail; 431 432 goto out; 433 434 fail: 435 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); 436 out: 437 mutex_unlock(&priv->mutex); 438 return ret; 439 } 440 441 static void 442 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt) 443 { 444 struct i2c_client *client = priv->hdmi; 445 u8 buf[cnt+1]; 446 int ret; 447 448 buf[0] = REG2ADDR(reg); 449 memcpy(&buf[1], p, cnt); 450 451 mutex_lock(&priv->mutex); 452 ret = set_page(priv, reg); 453 if (ret < 0) 454 goto out; 455 456 ret = i2c_master_send(client, buf, cnt + 1); 457 if (ret < 0) 458 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 459 out: 460 mutex_unlock(&priv->mutex); 461 } 462 463 static int 464 reg_read(struct tda998x_priv *priv, u16 reg) 465 { 466 u8 val = 0; 467 int ret; 468 469 ret = reg_read_range(priv, reg, &val, sizeof(val)); 470 if (ret < 0) 471 return ret; 472 return val; 473 } 474 475 static void 476 reg_write(struct tda998x_priv *priv, u16 reg, u8 val) 477 { 478 struct i2c_client *client = priv->hdmi; 479 u8 buf[] = {REG2ADDR(reg), val}; 480 int ret; 481 482 mutex_lock(&priv->mutex); 483 ret = set_page(priv, reg); 484 if (ret < 0) 485 goto out; 486 487 ret = i2c_master_send(client, buf, sizeof(buf)); 488 if (ret < 0) 489 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 490 out: 491 mutex_unlock(&priv->mutex); 492 } 493 494 static void 495 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val) 496 { 497 struct i2c_client *client = priv->hdmi; 498 u8 buf[] = {REG2ADDR(reg), val >> 8, val}; 499 int ret; 500 501 mutex_lock(&priv->mutex); 502 ret = set_page(priv, reg); 503 if (ret < 0) 504 goto out; 505 506 ret = i2c_master_send(client, buf, sizeof(buf)); 507 if (ret < 0) 508 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 509 out: 510 mutex_unlock(&priv->mutex); 511 } 512 513 static void 514 reg_set(struct tda998x_priv *priv, u16 reg, u8 val) 515 { 516 int old_val; 517 518 old_val = reg_read(priv, reg); 519 if (old_val >= 0) 520 reg_write(priv, reg, old_val | val); 521 } 522 523 static void 524 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val) 525 { 526 int old_val; 527 528 old_val = reg_read(priv, reg); 529 if (old_val >= 0) 530 reg_write(priv, reg, old_val & ~val); 531 } 532 533 static void 534 tda998x_reset(struct tda998x_priv *priv) 535 { 536 /* reset audio and i2c master: */ 537 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 538 msleep(50); 539 reg_write(priv, REG_SOFTRESET, 0); 540 msleep(50); 541 542 /* reset transmitter: */ 543 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 544 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 545 546 /* PLL registers common configuration */ 547 reg_write(priv, REG_PLL_SERIAL_1, 0x00); 548 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); 549 reg_write(priv, REG_PLL_SERIAL_3, 0x00); 550 reg_write(priv, REG_SERIALIZER, 0x00); 551 reg_write(priv, REG_BUFFER_OUT, 0x00); 552 reg_write(priv, REG_PLL_SCG1, 0x00); 553 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); 554 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 555 reg_write(priv, REG_PLL_SCGN1, 0xfa); 556 reg_write(priv, REG_PLL_SCGN2, 0x00); 557 reg_write(priv, REG_PLL_SCGR1, 0x5b); 558 reg_write(priv, REG_PLL_SCGR2, 0x00); 559 reg_write(priv, REG_PLL_SCG2, 0x10); 560 561 /* Write the default value MUX register */ 562 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24); 563 } 564 565 /* 566 * The TDA998x has a problem when trying to read the EDID close to a 567 * HPD assertion: it needs a delay of 100ms to avoid timing out while 568 * trying to read EDID data. 569 * 570 * However, tda998x_encoder_get_modes() may be called at any moment 571 * after tda998x_connector_detect() indicates that we are connected, so 572 * we need to delay probing modes in tda998x_encoder_get_modes() after 573 * we have seen a HPD inactive->active transition. This code implements 574 * that delay. 575 */ 576 static void tda998x_edid_delay_done(unsigned long data) 577 { 578 struct tda998x_priv *priv = (struct tda998x_priv *)data; 579 580 priv->edid_delay_active = false; 581 wake_up(&priv->edid_delay_waitq); 582 schedule_work(&priv->detect_work); 583 } 584 585 static void tda998x_edid_delay_start(struct tda998x_priv *priv) 586 { 587 priv->edid_delay_active = true; 588 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10); 589 } 590 591 static int tda998x_edid_delay_wait(struct tda998x_priv *priv) 592 { 593 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active); 594 } 595 596 /* 597 * We need to run the KMS hotplug event helper outside of our threaded 598 * interrupt routine as this can call back into our get_modes method, 599 * which will want to make use of interrupts. 600 */ 601 static void tda998x_detect_work(struct work_struct *work) 602 { 603 struct tda998x_priv *priv = 604 container_of(work, struct tda998x_priv, detect_work); 605 struct drm_device *dev = priv->encoder.dev; 606 607 if (dev) 608 drm_kms_helper_hotplug_event(dev); 609 } 610 611 /* 612 * only 2 interrupts may occur: screen plug/unplug and EDID read 613 */ 614 static irqreturn_t tda998x_irq_thread(int irq, void *data) 615 { 616 struct tda998x_priv *priv = data; 617 u8 sta, cec, lvl, flag0, flag1, flag2; 618 bool handled = false; 619 620 sta = cec_read(priv, REG_CEC_INTSTATUS); 621 cec = cec_read(priv, REG_CEC_RXSHPDINT); 622 lvl = cec_read(priv, REG_CEC_RXSHPDLEV); 623 flag0 = reg_read(priv, REG_INT_FLAGS_0); 624 flag1 = reg_read(priv, REG_INT_FLAGS_1); 625 flag2 = reg_read(priv, REG_INT_FLAGS_2); 626 DRM_DEBUG_DRIVER( 627 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n", 628 sta, cec, lvl, flag0, flag1, flag2); 629 630 if (cec & CEC_RXSHPDINT_HPD) { 631 if (lvl & CEC_RXSHPDLEV_HPD) 632 tda998x_edid_delay_start(priv); 633 else 634 schedule_work(&priv->detect_work); 635 636 handled = true; 637 } 638 639 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) { 640 priv->wq_edid_wait = 0; 641 wake_up(&priv->wq_edid); 642 handled = true; 643 } 644 645 return IRQ_RETVAL(handled); 646 } 647 648 static void 649 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr, 650 union hdmi_infoframe *frame) 651 { 652 u8 buf[32]; 653 ssize_t len; 654 655 len = hdmi_infoframe_pack(frame, buf, sizeof(buf)); 656 if (len < 0) { 657 dev_err(&priv->hdmi->dev, 658 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n", 659 frame->any.type, len); 660 return; 661 } 662 663 reg_clear(priv, REG_DIP_IF_FLAGS, bit); 664 reg_write_range(priv, addr, buf, len); 665 reg_set(priv, REG_DIP_IF_FLAGS, bit); 666 } 667 668 static void 669 tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p) 670 { 671 union hdmi_infoframe frame; 672 673 hdmi_audio_infoframe_init(&frame.audio); 674 675 frame.audio.channels = p->audio_frame[1] & 0x07; 676 frame.audio.channel_allocation = p->audio_frame[4]; 677 frame.audio.level_shift_value = (p->audio_frame[5] & 0x78) >> 3; 678 frame.audio.downmix_inhibit = (p->audio_frame[5] & 0x80) >> 7; 679 680 /* 681 * L-PCM and IEC61937 compressed audio shall always set sample 682 * frequency to "refer to stream". For others, see the HDMI 683 * specification. 684 */ 685 frame.audio.sample_frequency = (p->audio_frame[2] & 0x1c) >> 2; 686 687 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame); 688 } 689 690 static void 691 tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode) 692 { 693 union hdmi_infoframe frame; 694 695 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode); 696 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL; 697 698 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame); 699 } 700 701 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on) 702 { 703 if (on) { 704 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO); 705 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO); 706 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 707 } else { 708 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 709 } 710 } 711 712 static void 713 tda998x_configure_audio(struct tda998x_priv *priv, 714 struct drm_display_mode *mode, struct tda998x_encoder_params *p) 715 { 716 u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv; 717 u32 n; 718 719 /* Enable audio ports */ 720 reg_write(priv, REG_ENA_AP, p->audio_cfg); 721 reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg); 722 723 /* Set audio input source */ 724 switch (p->audio_format) { 725 case AFMT_SPDIF: 726 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF); 727 clksel_aip = AIP_CLKSEL_AIP_SPDIF; 728 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF; 729 cts_n = CTS_N_M(3) | CTS_N_K(3); 730 break; 731 732 case AFMT_I2S: 733 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S); 734 clksel_aip = AIP_CLKSEL_AIP_I2S; 735 clksel_fs = AIP_CLKSEL_FS_ACLK; 736 cts_n = CTS_N_M(3) | CTS_N_K(3); 737 break; 738 739 default: 740 BUG(); 741 return; 742 } 743 744 reg_write(priv, REG_AIP_CLKSEL, clksel_aip); 745 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT | 746 AIP_CNTRL_0_ACR_MAN); /* auto CTS */ 747 reg_write(priv, REG_CTS_N, cts_n); 748 749 /* 750 * Audio input somehow depends on HDMI line rate which is 751 * related to pixclk. Testing showed that modes with pixclk 752 * >100MHz need a larger divider while <40MHz need the default. 753 * There is no detailed info in the datasheet, so we just 754 * assume 100MHz requires larger divider. 755 */ 756 adiv = AUDIO_DIV_SERCLK_8; 757 if (mode->clock > 100000) 758 adiv++; /* AUDIO_DIV_SERCLK_16 */ 759 760 /* S/PDIF asks for a larger divider */ 761 if (p->audio_format == AFMT_SPDIF) 762 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */ 763 764 reg_write(priv, REG_AUDIO_DIV, adiv); 765 766 /* 767 * This is the approximate value of N, which happens to be 768 * the recommended values for non-coherent clocks. 769 */ 770 n = 128 * p->audio_sample_rate / 1000; 771 772 /* Write the CTS and N values */ 773 buf[0] = 0x44; 774 buf[1] = 0x42; 775 buf[2] = 0x01; 776 buf[3] = n; 777 buf[4] = n >> 8; 778 buf[5] = n >> 16; 779 reg_write_range(priv, REG_ACR_CTS_0, buf, 6); 780 781 /* Set CTS clock reference */ 782 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs); 783 784 /* Reset CTS generator */ 785 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 786 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 787 788 /* Write the channel status */ 789 buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT; 790 buf[1] = 0x00; 791 buf[2] = IEC958_AES3_CON_FS_NOTID; 792 buf[3] = IEC958_AES4_CON_ORIGFS_NOTID | 793 IEC958_AES4_CON_MAX_WORDLEN_24; 794 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4); 795 796 tda998x_audio_mute(priv, true); 797 msleep(20); 798 tda998x_audio_mute(priv, false); 799 800 /* Write the audio information packet */ 801 tda998x_write_aif(priv, p); 802 } 803 804 /* DRM encoder functions */ 805 806 static void tda998x_encoder_set_config(struct tda998x_priv *priv, 807 const struct tda998x_encoder_params *p) 808 { 809 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | 810 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | 811 VIP_CNTRL_0_SWAP_B(p->swap_b) | 812 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); 813 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | 814 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | 815 VIP_CNTRL_1_SWAP_D(p->swap_d) | 816 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); 817 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | 818 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | 819 VIP_CNTRL_2_SWAP_F(p->swap_f) | 820 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); 821 822 priv->params = *p; 823 } 824 825 static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode) 826 { 827 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder); 828 829 /* we only care about on or off: */ 830 if (mode != DRM_MODE_DPMS_ON) 831 mode = DRM_MODE_DPMS_OFF; 832 833 if (mode == priv->dpms) 834 return; 835 836 switch (mode) { 837 case DRM_MODE_DPMS_ON: 838 /* enable video ports, audio will be enabled later */ 839 reg_write(priv, REG_ENA_VP_0, 0xff); 840 reg_write(priv, REG_ENA_VP_1, 0xff); 841 reg_write(priv, REG_ENA_VP_2, 0xff); 842 /* set muxing after enabling ports: */ 843 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0); 844 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1); 845 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2); 846 break; 847 case DRM_MODE_DPMS_OFF: 848 /* disable video ports */ 849 reg_write(priv, REG_ENA_VP_0, 0x00); 850 reg_write(priv, REG_ENA_VP_1, 0x00); 851 reg_write(priv, REG_ENA_VP_2, 0x00); 852 break; 853 } 854 855 priv->dpms = mode; 856 } 857 858 static void 859 tda998x_encoder_save(struct drm_encoder *encoder) 860 { 861 DBG(""); 862 } 863 864 static void 865 tda998x_encoder_restore(struct drm_encoder *encoder) 866 { 867 DBG(""); 868 } 869 870 static bool 871 tda998x_encoder_mode_fixup(struct drm_encoder *encoder, 872 const struct drm_display_mode *mode, 873 struct drm_display_mode *adjusted_mode) 874 { 875 return true; 876 } 877 878 static int tda998x_connector_mode_valid(struct drm_connector *connector, 879 struct drm_display_mode *mode) 880 { 881 if (mode->clock > 150000) 882 return MODE_CLOCK_HIGH; 883 if (mode->htotal >= BIT(13)) 884 return MODE_BAD_HVALUE; 885 if (mode->vtotal >= BIT(11)) 886 return MODE_BAD_VVALUE; 887 return MODE_OK; 888 } 889 890 static void 891 tda998x_encoder_mode_set(struct drm_encoder *encoder, 892 struct drm_display_mode *mode, 893 struct drm_display_mode *adjusted_mode) 894 { 895 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder); 896 u16 ref_pix, ref_line, n_pix, n_line; 897 u16 hs_pix_s, hs_pix_e; 898 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e; 899 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e; 900 u16 vwin1_line_s, vwin1_line_e; 901 u16 vwin2_line_s, vwin2_line_e; 902 u16 de_pix_s, de_pix_e; 903 u8 reg, div, rep; 904 905 /* 906 * Internally TDA998x is using ITU-R BT.656 style sync but 907 * we get VESA style sync. TDA998x is using a reference pixel 908 * relative to ITU to sync to the input frame and for output 909 * sync generation. Currently, we are using reference detection 910 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point 911 * which is position of rising VS with coincident rising HS. 912 * 913 * Now there is some issues to take care of: 914 * - HDMI data islands require sync-before-active 915 * - TDA998x register values must be > 0 to be enabled 916 * - REFLINE needs an additional offset of +1 917 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB 918 * 919 * So we add +1 to all horizontal and vertical register values, 920 * plus an additional +3 for REFPIX as we are using RGB input only. 921 */ 922 n_pix = mode->htotal; 923 n_line = mode->vtotal; 924 925 hs_pix_e = mode->hsync_end - mode->hdisplay; 926 hs_pix_s = mode->hsync_start - mode->hdisplay; 927 de_pix_e = mode->htotal; 928 de_pix_s = mode->htotal - mode->hdisplay; 929 ref_pix = 3 + hs_pix_s; 930 931 /* 932 * Attached LCD controllers may generate broken sync. Allow 933 * those to adjust the position of the rising VS edge by adding 934 * HSKEW to ref_pix. 935 */ 936 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) 937 ref_pix += adjusted_mode->hskew; 938 939 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { 940 ref_line = 1 + mode->vsync_start - mode->vdisplay; 941 vwin1_line_s = mode->vtotal - mode->vdisplay - 1; 942 vwin1_line_e = vwin1_line_s + mode->vdisplay; 943 vs1_pix_s = vs1_pix_e = hs_pix_s; 944 vs1_line_s = mode->vsync_start - mode->vdisplay; 945 vs1_line_e = vs1_line_s + 946 mode->vsync_end - mode->vsync_start; 947 vwin2_line_s = vwin2_line_e = 0; 948 vs2_pix_s = vs2_pix_e = 0; 949 vs2_line_s = vs2_line_e = 0; 950 } else { 951 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; 952 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; 953 vwin1_line_e = vwin1_line_s + mode->vdisplay/2; 954 vs1_pix_s = vs1_pix_e = hs_pix_s; 955 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; 956 vs1_line_e = vs1_line_s + 957 (mode->vsync_end - mode->vsync_start)/2; 958 vwin2_line_s = vwin1_line_s + mode->vtotal/2; 959 vwin2_line_e = vwin2_line_s + mode->vdisplay/2; 960 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; 961 vs2_line_s = vs1_line_s + mode->vtotal/2 ; 962 vs2_line_e = vs2_line_s + 963 (mode->vsync_end - mode->vsync_start)/2; 964 } 965 966 div = 148500 / mode->clock; 967 if (div != 0) { 968 div--; 969 if (div > 3) 970 div = 3; 971 } 972 973 /* mute the audio FIFO: */ 974 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 975 976 /* set HDMI HDCP mode off: */ 977 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 978 reg_clear(priv, REG_TX33, TX33_HDMI); 979 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); 980 981 /* no pre-filter or interpolator: */ 982 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | 983 HVF_CNTRL_0_INTPOL(0)); 984 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); 985 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | 986 VIP_CNTRL_4_BLC(0)); 987 988 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); 989 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR | 990 PLL_SERIAL_3_SRL_DE); 991 reg_write(priv, REG_SERIALIZER, 0); 992 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); 993 994 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */ 995 rep = 0; 996 reg_write(priv, REG_RPT_CNTRL, 0); 997 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | 998 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 999 1000 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | 1001 PLL_SERIAL_2_SRL_PR(rep)); 1002 1003 /* set color matrix bypass flag: */ 1004 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP | 1005 MAT_CONTRL_MAT_SC(1)); 1006 1007 /* set BIAS tmds value: */ 1008 reg_write(priv, REG_ANA_GENERAL, 0x09); 1009 1010 /* 1011 * Sync on rising HSYNC/VSYNC 1012 */ 1013 reg = VIP_CNTRL_3_SYNC_HS; 1014 1015 /* 1016 * TDA19988 requires high-active sync at input stage, 1017 * so invert low-active sync provided by master encoder here 1018 */ 1019 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1020 reg |= VIP_CNTRL_3_H_TGL; 1021 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1022 reg |= VIP_CNTRL_3_V_TGL; 1023 reg_write(priv, REG_VIP_CNTRL_3, reg); 1024 1025 reg_write(priv, REG_VIDFORMAT, 0x00); 1026 reg_write16(priv, REG_REFPIX_MSB, ref_pix); 1027 reg_write16(priv, REG_REFLINE_MSB, ref_line); 1028 reg_write16(priv, REG_NPIX_MSB, n_pix); 1029 reg_write16(priv, REG_NLINE_MSB, n_line); 1030 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s); 1031 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s); 1032 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e); 1033 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e); 1034 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s); 1035 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s); 1036 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e); 1037 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e); 1038 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s); 1039 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e); 1040 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s); 1041 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e); 1042 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s); 1043 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e); 1044 reg_write16(priv, REG_DE_START_MSB, de_pix_s); 1045 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e); 1046 1047 if (priv->rev == TDA19988) { 1048 /* let incoming pixels fill the active space (if any) */ 1049 reg_write(priv, REG_ENABLE_SPACE, 0x00); 1050 } 1051 1052 /* 1053 * Always generate sync polarity relative to input sync and 1054 * revert input stage toggled sync at output stage 1055 */ 1056 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN; 1057 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1058 reg |= TBG_CNTRL_1_H_TGL; 1059 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1060 reg |= TBG_CNTRL_1_V_TGL; 1061 reg_write(priv, REG_TBG_CNTRL_1, reg); 1062 1063 /* must be last register set: */ 1064 reg_write(priv, REG_TBG_CNTRL_0, 0); 1065 1066 /* Only setup the info frames if the sink is HDMI */ 1067 if (priv->is_hdmi_sink) { 1068 /* We need to turn HDMI HDCP stuff on to get audio through */ 1069 reg &= ~TBG_CNTRL_1_DWIN_DIS; 1070 reg_write(priv, REG_TBG_CNTRL_1, reg); 1071 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); 1072 reg_set(priv, REG_TX33, TX33_HDMI); 1073 1074 tda998x_write_avi(priv, adjusted_mode); 1075 1076 if (priv->params.audio_cfg) 1077 tda998x_configure_audio(priv, adjusted_mode, 1078 &priv->params); 1079 } 1080 } 1081 1082 static enum drm_connector_status 1083 tda998x_connector_detect(struct drm_connector *connector, bool force) 1084 { 1085 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1086 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV); 1087 1088 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : 1089 connector_status_disconnected; 1090 } 1091 1092 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length) 1093 { 1094 struct tda998x_priv *priv = data; 1095 u8 offset, segptr; 1096 int ret, i; 1097 1098 offset = (blk & 1) ? 128 : 0; 1099 segptr = blk / 2; 1100 1101 reg_write(priv, REG_DDC_ADDR, 0xa0); 1102 reg_write(priv, REG_DDC_OFFS, offset); 1103 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60); 1104 reg_write(priv, REG_DDC_SEGM, segptr); 1105 1106 /* enable reading EDID: */ 1107 priv->wq_edid_wait = 1; 1108 reg_write(priv, REG_EDID_CTRL, 0x1); 1109 1110 /* flag must be cleared by sw: */ 1111 reg_write(priv, REG_EDID_CTRL, 0x0); 1112 1113 /* wait for block read to complete: */ 1114 if (priv->hdmi->irq) { 1115 i = wait_event_timeout(priv->wq_edid, 1116 !priv->wq_edid_wait, 1117 msecs_to_jiffies(100)); 1118 if (i < 0) { 1119 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i); 1120 return i; 1121 } 1122 } else { 1123 for (i = 100; i > 0; i--) { 1124 msleep(1); 1125 ret = reg_read(priv, REG_INT_FLAGS_2); 1126 if (ret < 0) 1127 return ret; 1128 if (ret & INT_FLAGS_2_EDID_BLK_RD) 1129 break; 1130 } 1131 } 1132 1133 if (i == 0) { 1134 dev_err(&priv->hdmi->dev, "read edid timeout\n"); 1135 return -ETIMEDOUT; 1136 } 1137 1138 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length); 1139 if (ret != length) { 1140 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n", 1141 blk, ret); 1142 return ret; 1143 } 1144 1145 return 0; 1146 } 1147 1148 static int tda998x_connector_get_modes(struct drm_connector *connector) 1149 { 1150 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1151 struct edid *edid; 1152 int n; 1153 1154 /* 1155 * If we get killed while waiting for the HPD timeout, return 1156 * no modes found: we are not in a restartable path, so we 1157 * can't handle signals gracefully. 1158 */ 1159 if (tda998x_edid_delay_wait(priv)) 1160 return 0; 1161 1162 if (priv->rev == TDA19988) 1163 reg_clear(priv, REG_TX4, TX4_PD_RAM); 1164 1165 edid = drm_do_get_edid(connector, read_edid_block, priv); 1166 1167 if (priv->rev == TDA19988) 1168 reg_set(priv, REG_TX4, TX4_PD_RAM); 1169 1170 if (!edid) { 1171 dev_warn(&priv->hdmi->dev, "failed to read EDID\n"); 1172 return 0; 1173 } 1174 1175 drm_mode_connector_update_edid_property(connector, edid); 1176 n = drm_add_edid_modes(connector, edid); 1177 priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid); 1178 kfree(edid); 1179 1180 return n; 1181 } 1182 1183 static void tda998x_encoder_set_polling(struct tda998x_priv *priv, 1184 struct drm_connector *connector) 1185 { 1186 if (priv->hdmi->irq) 1187 connector->polled = DRM_CONNECTOR_POLL_HPD; 1188 else 1189 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1190 DRM_CONNECTOR_POLL_DISCONNECT; 1191 } 1192 1193 static void tda998x_destroy(struct tda998x_priv *priv) 1194 { 1195 /* disable all IRQs and free the IRQ handler */ 1196 cec_write(priv, REG_CEC_RXSHPDINTENA, 0); 1197 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 1198 1199 if (priv->hdmi->irq) 1200 free_irq(priv->hdmi->irq, priv); 1201 1202 del_timer_sync(&priv->edid_delay_timer); 1203 cancel_work_sync(&priv->detect_work); 1204 1205 i2c_unregister_device(priv->cec); 1206 } 1207 1208 /* I2C driver functions */ 1209 1210 static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv) 1211 { 1212 struct device_node *np = client->dev.of_node; 1213 u32 video; 1214 int rev_lo, rev_hi, ret; 1215 unsigned short cec_addr; 1216 1217 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); 1218 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); 1219 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); 1220 1221 priv->current_page = 0xff; 1222 priv->hdmi = client; 1223 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */ 1224 cec_addr = 0x34 + (client->addr & 0x03); 1225 priv->cec = i2c_new_dummy(client->adapter, cec_addr); 1226 if (!priv->cec) 1227 return -ENODEV; 1228 1229 priv->dpms = DRM_MODE_DPMS_OFF; 1230 1231 mutex_init(&priv->mutex); /* protect the page access */ 1232 init_waitqueue_head(&priv->edid_delay_waitq); 1233 setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done, 1234 (unsigned long)priv); 1235 INIT_WORK(&priv->detect_work, tda998x_detect_work); 1236 1237 /* wake up the device: */ 1238 cec_write(priv, REG_CEC_ENAMODS, 1239 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); 1240 1241 tda998x_reset(priv); 1242 1243 /* read version: */ 1244 rev_lo = reg_read(priv, REG_VERSION_LSB); 1245 rev_hi = reg_read(priv, REG_VERSION_MSB); 1246 if (rev_lo < 0 || rev_hi < 0) { 1247 ret = rev_lo < 0 ? rev_lo : rev_hi; 1248 goto fail; 1249 } 1250 1251 priv->rev = rev_lo | rev_hi << 8; 1252 1253 /* mask off feature bits: */ 1254 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ 1255 1256 switch (priv->rev) { 1257 case TDA9989N2: 1258 dev_info(&client->dev, "found TDA9989 n2"); 1259 break; 1260 case TDA19989: 1261 dev_info(&client->dev, "found TDA19989"); 1262 break; 1263 case TDA19989N2: 1264 dev_info(&client->dev, "found TDA19989 n2"); 1265 break; 1266 case TDA19988: 1267 dev_info(&client->dev, "found TDA19988"); 1268 break; 1269 default: 1270 dev_err(&client->dev, "found unsupported device: %04x\n", 1271 priv->rev); 1272 goto fail; 1273 } 1274 1275 /* after reset, enable DDC: */ 1276 reg_write(priv, REG_DDC_DISABLE, 0x00); 1277 1278 /* set clock on DDC channel: */ 1279 reg_write(priv, REG_TX3, 39); 1280 1281 /* if necessary, disable multi-master: */ 1282 if (priv->rev == TDA19989) 1283 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM); 1284 1285 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL, 1286 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); 1287 1288 /* initialize the optional IRQ */ 1289 if (client->irq) { 1290 int irqf_trigger; 1291 1292 /* init read EDID waitqueue and HDP work */ 1293 init_waitqueue_head(&priv->wq_edid); 1294 1295 /* clear pending interrupts */ 1296 reg_read(priv, REG_INT_FLAGS_0); 1297 reg_read(priv, REG_INT_FLAGS_1); 1298 reg_read(priv, REG_INT_FLAGS_2); 1299 1300 irqf_trigger = 1301 irqd_get_trigger_type(irq_get_irq_data(client->irq)); 1302 ret = request_threaded_irq(client->irq, NULL, 1303 tda998x_irq_thread, 1304 irqf_trigger | IRQF_ONESHOT, 1305 "tda998x", priv); 1306 if (ret) { 1307 dev_err(&client->dev, 1308 "failed to request IRQ#%u: %d\n", 1309 client->irq, ret); 1310 goto fail; 1311 } 1312 1313 /* enable HPD irq */ 1314 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD); 1315 } 1316 1317 /* enable EDID read irq: */ 1318 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 1319 1320 if (!np) 1321 return 0; /* non-DT */ 1322 1323 /* get the optional video properties */ 1324 ret = of_property_read_u32(np, "video-ports", &video); 1325 if (ret == 0) { 1326 priv->vip_cntrl_0 = video >> 16; 1327 priv->vip_cntrl_1 = video >> 8; 1328 priv->vip_cntrl_2 = video; 1329 } 1330 1331 return 0; 1332 1333 fail: 1334 /* if encoder_init fails, the encoder slave is never registered, 1335 * so cleanup here: 1336 */ 1337 if (priv->cec) 1338 i2c_unregister_device(priv->cec); 1339 return -ENXIO; 1340 } 1341 1342 static void tda998x_encoder_prepare(struct drm_encoder *encoder) 1343 { 1344 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 1345 } 1346 1347 static void tda998x_encoder_commit(struct drm_encoder *encoder) 1348 { 1349 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 1350 } 1351 1352 static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = { 1353 .dpms = tda998x_encoder_dpms, 1354 .save = tda998x_encoder_save, 1355 .restore = tda998x_encoder_restore, 1356 .mode_fixup = tda998x_encoder_mode_fixup, 1357 .prepare = tda998x_encoder_prepare, 1358 .commit = tda998x_encoder_commit, 1359 .mode_set = tda998x_encoder_mode_set, 1360 }; 1361 1362 static void tda998x_encoder_destroy(struct drm_encoder *encoder) 1363 { 1364 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder); 1365 1366 tda998x_destroy(priv); 1367 drm_encoder_cleanup(encoder); 1368 } 1369 1370 static const struct drm_encoder_funcs tda998x_encoder_funcs = { 1371 .destroy = tda998x_encoder_destroy, 1372 }; 1373 1374 static struct drm_encoder * 1375 tda998x_connector_best_encoder(struct drm_connector *connector) 1376 { 1377 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1378 1379 return &priv->encoder; 1380 } 1381 1382 static 1383 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = { 1384 .get_modes = tda998x_connector_get_modes, 1385 .mode_valid = tda998x_connector_mode_valid, 1386 .best_encoder = tda998x_connector_best_encoder, 1387 }; 1388 1389 static void tda998x_connector_destroy(struct drm_connector *connector) 1390 { 1391 drm_connector_unregister(connector); 1392 drm_connector_cleanup(connector); 1393 } 1394 1395 static const struct drm_connector_funcs tda998x_connector_funcs = { 1396 .dpms = drm_helper_connector_dpms, 1397 .fill_modes = drm_helper_probe_single_connector_modes, 1398 .detect = tda998x_connector_detect, 1399 .destroy = tda998x_connector_destroy, 1400 }; 1401 1402 static int tda998x_bind(struct device *dev, struct device *master, void *data) 1403 { 1404 struct tda998x_encoder_params *params = dev->platform_data; 1405 struct i2c_client *client = to_i2c_client(dev); 1406 struct drm_device *drm = data; 1407 struct tda998x_priv *priv; 1408 u32 crtcs = 0; 1409 int ret; 1410 1411 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1412 if (!priv) 1413 return -ENOMEM; 1414 1415 dev_set_drvdata(dev, priv); 1416 1417 if (dev->of_node) 1418 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); 1419 1420 /* If no CRTCs were found, fall back to our old behaviour */ 1421 if (crtcs == 0) { 1422 dev_warn(dev, "Falling back to first CRTC\n"); 1423 crtcs = 1 << 0; 1424 } 1425 1426 priv->connector.interlace_allowed = 1; 1427 priv->encoder.possible_crtcs = crtcs; 1428 1429 ret = tda998x_create(client, priv); 1430 if (ret) 1431 return ret; 1432 1433 if (!dev->of_node && params) 1434 tda998x_encoder_set_config(priv, params); 1435 1436 tda998x_encoder_set_polling(priv, &priv->connector); 1437 1438 drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs); 1439 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs, 1440 DRM_MODE_ENCODER_TMDS); 1441 if (ret) 1442 goto err_encoder; 1443 1444 drm_connector_helper_add(&priv->connector, 1445 &tda998x_connector_helper_funcs); 1446 ret = drm_connector_init(drm, &priv->connector, 1447 &tda998x_connector_funcs, 1448 DRM_MODE_CONNECTOR_HDMIA); 1449 if (ret) 1450 goto err_connector; 1451 1452 ret = drm_connector_register(&priv->connector); 1453 if (ret) 1454 goto err_sysfs; 1455 1456 priv->connector.encoder = &priv->encoder; 1457 drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder); 1458 1459 return 0; 1460 1461 err_sysfs: 1462 drm_connector_cleanup(&priv->connector); 1463 err_connector: 1464 drm_encoder_cleanup(&priv->encoder); 1465 err_encoder: 1466 tda998x_destroy(priv); 1467 return ret; 1468 } 1469 1470 static void tda998x_unbind(struct device *dev, struct device *master, 1471 void *data) 1472 { 1473 struct tda998x_priv *priv = dev_get_drvdata(dev); 1474 1475 drm_connector_cleanup(&priv->connector); 1476 drm_encoder_cleanup(&priv->encoder); 1477 tda998x_destroy(priv); 1478 } 1479 1480 static const struct component_ops tda998x_ops = { 1481 .bind = tda998x_bind, 1482 .unbind = tda998x_unbind, 1483 }; 1484 1485 static int 1486 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) 1487 { 1488 return component_add(&client->dev, &tda998x_ops); 1489 } 1490 1491 static int tda998x_remove(struct i2c_client *client) 1492 { 1493 component_del(&client->dev, &tda998x_ops); 1494 return 0; 1495 } 1496 1497 #ifdef CONFIG_OF 1498 static const struct of_device_id tda998x_dt_ids[] = { 1499 { .compatible = "nxp,tda998x", }, 1500 { } 1501 }; 1502 MODULE_DEVICE_TABLE(of, tda998x_dt_ids); 1503 #endif 1504 1505 static struct i2c_device_id tda998x_ids[] = { 1506 { "tda998x", 0 }, 1507 { } 1508 }; 1509 MODULE_DEVICE_TABLE(i2c, tda998x_ids); 1510 1511 static struct i2c_driver tda998x_driver = { 1512 .probe = tda998x_probe, 1513 .remove = tda998x_remove, 1514 .driver = { 1515 .name = "tda998x", 1516 .of_match_table = of_match_ptr(tda998x_dt_ids), 1517 }, 1518 .id_table = tda998x_ids, 1519 }; 1520 1521 module_i2c_driver(tda998x_driver); 1522 1523 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1524 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); 1525 MODULE_LICENSE("GPL"); 1526