1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Texas Instruments 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/gpio/consumer.h> 9 #include <linux/hdmi.h> 10 #include <linux/i2c.h> 11 #include <linux/module.h> 12 #include <linux/platform_data/tda9950.h> 13 #include <linux/irq.h> 14 #include <sound/asoundef.h> 15 #include <sound/hdmi-codec.h> 16 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_bridge.h> 19 #include <drm/drm_edid.h> 20 #include <drm/drm_of.h> 21 #include <drm/drm_print.h> 22 #include <drm/drm_probe_helper.h> 23 #include <drm/drm_simple_kms_helper.h> 24 #include <drm/i2c/tda998x.h> 25 26 #include <media/cec-notifier.h> 27 28 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 29 30 enum { 31 AUDIO_ROUTE_I2S, 32 AUDIO_ROUTE_SPDIF, 33 AUDIO_ROUTE_NUM 34 }; 35 36 struct tda998x_audio_route { 37 u8 ena_aclk; 38 u8 mux_ap; 39 u8 aip_clksel; 40 }; 41 42 struct tda998x_audio_settings { 43 const struct tda998x_audio_route *route; 44 struct hdmi_audio_infoframe cea; 45 unsigned int sample_rate; 46 u8 status[5]; 47 u8 ena_ap; 48 u8 i2s_format; 49 u8 cts_n; 50 }; 51 52 struct tda998x_priv { 53 struct i2c_client *cec; 54 struct i2c_client *hdmi; 55 struct mutex mutex; 56 u16 rev; 57 u8 cec_addr; 58 u8 current_page; 59 bool is_on; 60 bool supports_infoframes; 61 bool sink_has_audio; 62 enum hdmi_quantization_range rgb_quant_range; 63 u8 vip_cntrl_0; 64 u8 vip_cntrl_1; 65 u8 vip_cntrl_2; 66 unsigned long tmds_clock; 67 struct tda998x_audio_settings audio; 68 69 struct platform_device *audio_pdev; 70 struct mutex audio_mutex; 71 72 struct mutex edid_mutex; 73 wait_queue_head_t wq_edid; 74 volatile int wq_edid_wait; 75 76 struct work_struct detect_work; 77 struct timer_list edid_delay_timer; 78 wait_queue_head_t edid_delay_waitq; 79 bool edid_delay_active; 80 81 struct drm_encoder encoder; 82 struct drm_bridge bridge; 83 struct drm_connector connector; 84 85 u8 audio_port_enable[AUDIO_ROUTE_NUM]; 86 struct tda9950_glue cec_glue; 87 struct gpio_desc *calib; 88 struct cec_notifier *cec_notify; 89 }; 90 91 #define conn_to_tda998x_priv(x) \ 92 container_of(x, struct tda998x_priv, connector) 93 #define enc_to_tda998x_priv(x) \ 94 container_of(x, struct tda998x_priv, encoder) 95 #define bridge_to_tda998x_priv(x) \ 96 container_of(x, struct tda998x_priv, bridge) 97 98 /* The TDA9988 series of devices use a paged register scheme.. to simplify 99 * things we encode the page # in upper bits of the register #. To read/ 100 * write a given register, we need to make sure CURPAGE register is set 101 * appropriately. Which implies reads/writes are not atomic. Fun! 102 */ 103 104 #define REG(page, addr) (((page) << 8) | (addr)) 105 #define REG2ADDR(reg) ((reg) & 0xff) 106 #define REG2PAGE(reg) (((reg) >> 8) & 0xff) 107 108 #define REG_CURPAGE 0xff /* write */ 109 110 111 /* Page 00h: General Control */ 112 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */ 113 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ 114 # define MAIN_CNTRL0_SR (1 << 0) 115 # define MAIN_CNTRL0_DECS (1 << 1) 116 # define MAIN_CNTRL0_DEHS (1 << 2) 117 # define MAIN_CNTRL0_CECS (1 << 3) 118 # define MAIN_CNTRL0_CEHS (1 << 4) 119 # define MAIN_CNTRL0_SCALER (1 << 7) 120 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */ 121 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ 122 # define SOFTRESET_AUDIO (1 << 0) 123 # define SOFTRESET_I2C_MASTER (1 << 1) 124 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ 125 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ 126 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ 127 # define I2C_MASTER_DIS_MM (1 << 0) 128 # define I2C_MASTER_DIS_FILT (1 << 1) 129 # define I2C_MASTER_APP_STRT_LAT (1 << 2) 130 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ 131 # define FEAT_POWERDOWN_PREFILT BIT(0) 132 # define FEAT_POWERDOWN_CSC BIT(1) 133 # define FEAT_POWERDOWN_SPDIF (1 << 3) 134 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ 135 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ 136 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ 137 # define INT_FLAGS_2_EDID_BLK_RD (1 << 1) 138 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ 139 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ 140 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ 141 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ 142 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ 143 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ 144 # define VIP_CNTRL_0_MIRR_A (1 << 7) 145 # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) 146 # define VIP_CNTRL_0_MIRR_B (1 << 3) 147 # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) 148 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ 149 # define VIP_CNTRL_1_MIRR_C (1 << 7) 150 # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) 151 # define VIP_CNTRL_1_MIRR_D (1 << 3) 152 # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) 153 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ 154 # define VIP_CNTRL_2_MIRR_E (1 << 7) 155 # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) 156 # define VIP_CNTRL_2_MIRR_F (1 << 3) 157 # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) 158 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ 159 # define VIP_CNTRL_3_X_TGL (1 << 0) 160 # define VIP_CNTRL_3_H_TGL (1 << 1) 161 # define VIP_CNTRL_3_V_TGL (1 << 2) 162 # define VIP_CNTRL_3_EMB (1 << 3) 163 # define VIP_CNTRL_3_SYNC_DE (1 << 4) 164 # define VIP_CNTRL_3_SYNC_HS (1 << 5) 165 # define VIP_CNTRL_3_DE_INT (1 << 6) 166 # define VIP_CNTRL_3_EDGE (1 << 7) 167 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ 168 # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) 169 # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) 170 # define VIP_CNTRL_4_CCIR656 (1 << 4) 171 # define VIP_CNTRL_4_656_ALT (1 << 5) 172 # define VIP_CNTRL_4_TST_656 (1 << 6) 173 # define VIP_CNTRL_4_TST_PAT (1 << 7) 174 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ 175 # define VIP_CNTRL_5_CKCASE (1 << 0) 176 # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) 177 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */ 178 # define MUX_AP_SELECT_I2S 0x64 179 # define MUX_AP_SELECT_SPDIF 0x40 180 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ 181 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ 182 # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) 183 # define MAT_CONTRL_MAT_BP (1 << 2) 184 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ 185 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ 186 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ 187 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ 188 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ 189 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ 190 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ 191 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ 192 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ 193 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ 194 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ 195 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ 196 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ 197 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ 198 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ 199 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ 200 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ 201 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ 202 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ 203 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ 204 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ 205 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ 206 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ 207 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ 208 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ 209 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ 210 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ 211 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ 212 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ 213 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ 214 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ 215 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ 216 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ 217 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ 218 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ 219 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ 220 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ 221 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ 222 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ 223 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ 224 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ 225 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ 226 # define TBG_CNTRL_0_TOP_TGL (1 << 0) 227 # define TBG_CNTRL_0_TOP_SEL (1 << 1) 228 # define TBG_CNTRL_0_DE_EXT (1 << 2) 229 # define TBG_CNTRL_0_TOP_EXT (1 << 3) 230 # define TBG_CNTRL_0_FRAME_DIS (1 << 5) 231 # define TBG_CNTRL_0_SYNC_MTHD (1 << 6) 232 # define TBG_CNTRL_0_SYNC_ONCE (1 << 7) 233 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ 234 # define TBG_CNTRL_1_H_TGL (1 << 0) 235 # define TBG_CNTRL_1_V_TGL (1 << 1) 236 # define TBG_CNTRL_1_TGL_EN (1 << 2) 237 # define TBG_CNTRL_1_X_EXT (1 << 3) 238 # define TBG_CNTRL_1_H_EXT (1 << 4) 239 # define TBG_CNTRL_1_V_EXT (1 << 5) 240 # define TBG_CNTRL_1_DWIN_DIS (1 << 6) 241 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ 242 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ 243 # define HVF_CNTRL_0_SM (1 << 7) 244 # define HVF_CNTRL_0_RWB (1 << 6) 245 # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) 246 # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) 247 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ 248 # define HVF_CNTRL_1_FOR (1 << 0) 249 # define HVF_CNTRL_1_YUVBLK (1 << 1) 250 # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) 251 # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) 252 # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) 253 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ 254 # define RPT_CNTRL_REPEAT(x) ((x) & 15) 255 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ 256 # define I2S_FORMAT_PHILIPS (0 << 0) 257 # define I2S_FORMAT_LEFT_J (2 << 0) 258 # define I2S_FORMAT_RIGHT_J (3 << 0) 259 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ 260 # define AIP_CLKSEL_AIP_SPDIF (0 << 3) 261 # define AIP_CLKSEL_AIP_I2S (1 << 3) 262 # define AIP_CLKSEL_FS_ACLK (0 << 0) 263 # define AIP_CLKSEL_FS_MCLK (1 << 0) 264 # define AIP_CLKSEL_FS_FS64SPDIF (2 << 0) 265 266 /* Page 02h: PLL settings */ 267 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ 268 # define PLL_SERIAL_1_SRL_FDN (1 << 0) 269 # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) 270 # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) 271 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ 272 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0) 273 # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) 274 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ 275 # define PLL_SERIAL_3_SRL_CCIR (1 << 0) 276 # define PLL_SERIAL_3_SRL_DE (1 << 2) 277 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) 278 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ 279 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ 280 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ 281 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ 282 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ 283 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ 284 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ 285 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ 286 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ 287 # define AUDIO_DIV_SERCLK_1 0 288 # define AUDIO_DIV_SERCLK_2 1 289 # define AUDIO_DIV_SERCLK_4 2 290 # define AUDIO_DIV_SERCLK_8 3 291 # define AUDIO_DIV_SERCLK_16 4 292 # define AUDIO_DIV_SERCLK_32 5 293 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ 294 # define SEL_CLK_SEL_CLK1 (1 << 0) 295 # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) 296 # define SEL_CLK_ENA_SC_CLK (1 << 3) 297 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ 298 299 300 /* Page 09h: EDID Control */ 301 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ 302 /* next 127 successive registers are the EDID block */ 303 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ 304 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ 305 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ 306 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ 307 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ 308 309 310 /* Page 10h: information frames and packets */ 311 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ 312 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ 313 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ 314 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ 315 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ 316 317 318 /* Page 11h: audio settings and content info packets */ 319 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ 320 # define AIP_CNTRL_0_RST_FIFO (1 << 0) 321 # define AIP_CNTRL_0_SWAP (1 << 1) 322 # define AIP_CNTRL_0_LAYOUT (1 << 2) 323 # define AIP_CNTRL_0_ACR_MAN (1 << 5) 324 # define AIP_CNTRL_0_RST_CTS (1 << 6) 325 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */ 326 # define CA_I2S_CA_I2S(x) (((x) & 31) << 0) 327 # define CA_I2S_HBR_CHSTAT (1 << 6) 328 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ 329 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ 330 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ 331 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ 332 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ 333 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ 334 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ 335 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */ 336 # define CTS_N_K(x) (((x) & 7) << 0) 337 # define CTS_N_M(x) (((x) & 3) << 4) 338 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ 339 # define ENC_CNTRL_RST_ENC (1 << 0) 340 # define ENC_CNTRL_RST_SEL (1 << 1) 341 # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) 342 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ 343 # define DIP_FLAGS_ACR (1 << 0) 344 # define DIP_FLAGS_GC (1 << 1) 345 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ 346 # define DIP_IF_FLAGS_IF1 (1 << 1) 347 # define DIP_IF_FLAGS_IF2 (1 << 2) 348 # define DIP_IF_FLAGS_IF3 (1 << 3) 349 # define DIP_IF_FLAGS_IF4 (1 << 4) 350 # define DIP_IF_FLAGS_IF5 (1 << 5) 351 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ 352 353 354 /* Page 12h: HDCP and OTP */ 355 #define REG_TX3 REG(0x12, 0x9a) /* read/write */ 356 #define REG_TX4 REG(0x12, 0x9b) /* read/write */ 357 # define TX4_PD_RAM (1 << 1) 358 #define REG_TX33 REG(0x12, 0xb8) /* read/write */ 359 # define TX33_HDMI (1 << 1) 360 361 362 /* Page 13h: Gamut related metadata packets */ 363 364 365 366 /* CEC registers: (not paged) 367 */ 368 #define REG_CEC_INTSTATUS 0xee /* read */ 369 # define CEC_INTSTATUS_CEC (1 << 0) 370 # define CEC_INTSTATUS_HDMI (1 << 1) 371 #define REG_CEC_CAL_XOSC_CTRL1 0xf2 372 # define CEC_CAL_XOSC_CTRL1_ENA_CAL BIT(0) 373 #define REG_CEC_DES_FREQ2 0xf5 374 # define CEC_DES_FREQ2_DIS_AUTOCAL BIT(7) 375 #define REG_CEC_CLK 0xf6 376 # define CEC_CLK_FRO 0x11 377 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ 378 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) 379 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) 380 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) 381 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) 382 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */ 383 #define REG_CEC_RXSHPDINT 0xfd /* read */ 384 # define CEC_RXSHPDINT_RXSENS BIT(0) 385 # define CEC_RXSHPDINT_HPD BIT(1) 386 #define REG_CEC_RXSHPDLEV 0xfe /* read */ 387 # define CEC_RXSHPDLEV_RXSENS (1 << 0) 388 # define CEC_RXSHPDLEV_HPD (1 << 1) 389 390 #define REG_CEC_ENAMODS 0xff /* read/write */ 391 # define CEC_ENAMODS_EN_CEC_CLK (1 << 7) 392 # define CEC_ENAMODS_DIS_FRO (1 << 6) 393 # define CEC_ENAMODS_DIS_CCLK (1 << 5) 394 # define CEC_ENAMODS_EN_RXSENS (1 << 2) 395 # define CEC_ENAMODS_EN_HDMI (1 << 1) 396 # define CEC_ENAMODS_EN_CEC (1 << 0) 397 398 399 /* Device versions: */ 400 #define TDA9989N2 0x0101 401 #define TDA19989 0x0201 402 #define TDA19989N2 0x0202 403 #define TDA19988 0x0301 404 405 static void 406 cec_write(struct tda998x_priv *priv, u16 addr, u8 val) 407 { 408 u8 buf[] = {addr, val}; 409 struct i2c_msg msg = { 410 .addr = priv->cec_addr, 411 .len = 2, 412 .buf = buf, 413 }; 414 int ret; 415 416 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1); 417 if (ret < 0) 418 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n", 419 ret, addr); 420 } 421 422 static u8 423 cec_read(struct tda998x_priv *priv, u8 addr) 424 { 425 u8 val; 426 struct i2c_msg msg[2] = { 427 { 428 .addr = priv->cec_addr, 429 .len = 1, 430 .buf = &addr, 431 }, { 432 .addr = priv->cec_addr, 433 .flags = I2C_M_RD, 434 .len = 1, 435 .buf = &val, 436 }, 437 }; 438 int ret; 439 440 ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg)); 441 if (ret < 0) { 442 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n", 443 ret, addr); 444 val = 0; 445 } 446 447 return val; 448 } 449 450 static void cec_enamods(struct tda998x_priv *priv, u8 mods, bool enable) 451 { 452 int val = cec_read(priv, REG_CEC_ENAMODS); 453 454 if (val < 0) 455 return; 456 457 if (enable) 458 val |= mods; 459 else 460 val &= ~mods; 461 462 cec_write(priv, REG_CEC_ENAMODS, val); 463 } 464 465 static void tda998x_cec_set_calibration(struct tda998x_priv *priv, bool enable) 466 { 467 if (enable) { 468 u8 val; 469 470 cec_write(priv, 0xf3, 0xc0); 471 cec_write(priv, 0xf4, 0xd4); 472 473 /* Enable automatic calibration mode */ 474 val = cec_read(priv, REG_CEC_DES_FREQ2); 475 val &= ~CEC_DES_FREQ2_DIS_AUTOCAL; 476 cec_write(priv, REG_CEC_DES_FREQ2, val); 477 478 /* Enable free running oscillator */ 479 cec_write(priv, REG_CEC_CLK, CEC_CLK_FRO); 480 cec_enamods(priv, CEC_ENAMODS_DIS_FRO, false); 481 482 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 483 CEC_CAL_XOSC_CTRL1_ENA_CAL); 484 } else { 485 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 0); 486 } 487 } 488 489 /* 490 * Calibration for the internal oscillator: we need to set calibration mode, 491 * and then pulse the IRQ line low for a 10ms ± 1% period. 492 */ 493 static void tda998x_cec_calibration(struct tda998x_priv *priv) 494 { 495 struct gpio_desc *calib = priv->calib; 496 497 mutex_lock(&priv->edid_mutex); 498 if (priv->hdmi->irq > 0) 499 disable_irq(priv->hdmi->irq); 500 gpiod_direction_output(calib, 1); 501 tda998x_cec_set_calibration(priv, true); 502 503 local_irq_disable(); 504 gpiod_set_value(calib, 0); 505 mdelay(10); 506 gpiod_set_value(calib, 1); 507 local_irq_enable(); 508 509 tda998x_cec_set_calibration(priv, false); 510 gpiod_direction_input(calib); 511 if (priv->hdmi->irq > 0) 512 enable_irq(priv->hdmi->irq); 513 mutex_unlock(&priv->edid_mutex); 514 } 515 516 static int tda998x_cec_hook_init(void *data) 517 { 518 struct tda998x_priv *priv = data; 519 struct gpio_desc *calib; 520 521 calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS); 522 if (IS_ERR(calib)) { 523 dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n", 524 PTR_ERR(calib)); 525 return PTR_ERR(calib); 526 } 527 528 priv->calib = calib; 529 530 return 0; 531 } 532 533 static void tda998x_cec_hook_exit(void *data) 534 { 535 struct tda998x_priv *priv = data; 536 537 gpiod_put(priv->calib); 538 priv->calib = NULL; 539 } 540 541 static int tda998x_cec_hook_open(void *data) 542 { 543 struct tda998x_priv *priv = data; 544 545 cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, true); 546 tda998x_cec_calibration(priv); 547 548 return 0; 549 } 550 551 static void tda998x_cec_hook_release(void *data) 552 { 553 struct tda998x_priv *priv = data; 554 555 cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, false); 556 } 557 558 static int 559 set_page(struct tda998x_priv *priv, u16 reg) 560 { 561 if (REG2PAGE(reg) != priv->current_page) { 562 struct i2c_client *client = priv->hdmi; 563 u8 buf[] = { 564 REG_CURPAGE, REG2PAGE(reg) 565 }; 566 int ret = i2c_master_send(client, buf, sizeof(buf)); 567 if (ret < 0) { 568 dev_err(&client->dev, "%s %04x err %d\n", __func__, 569 reg, ret); 570 return ret; 571 } 572 573 priv->current_page = REG2PAGE(reg); 574 } 575 return 0; 576 } 577 578 static int 579 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt) 580 { 581 struct i2c_client *client = priv->hdmi; 582 u8 addr = REG2ADDR(reg); 583 int ret; 584 585 mutex_lock(&priv->mutex); 586 ret = set_page(priv, reg); 587 if (ret < 0) 588 goto out; 589 590 ret = i2c_master_send(client, &addr, sizeof(addr)); 591 if (ret < 0) 592 goto fail; 593 594 ret = i2c_master_recv(client, buf, cnt); 595 if (ret < 0) 596 goto fail; 597 598 goto out; 599 600 fail: 601 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); 602 out: 603 mutex_unlock(&priv->mutex); 604 return ret; 605 } 606 607 #define MAX_WRITE_RANGE_BUF 32 608 609 static void 610 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt) 611 { 612 struct i2c_client *client = priv->hdmi; 613 /* This is the maximum size of the buffer passed in */ 614 u8 buf[MAX_WRITE_RANGE_BUF + 1]; 615 int ret; 616 617 if (cnt > MAX_WRITE_RANGE_BUF) { 618 dev_err(&client->dev, "Fixed write buffer too small (%d)\n", 619 MAX_WRITE_RANGE_BUF); 620 return; 621 } 622 623 buf[0] = REG2ADDR(reg); 624 memcpy(&buf[1], p, cnt); 625 626 mutex_lock(&priv->mutex); 627 ret = set_page(priv, reg); 628 if (ret < 0) 629 goto out; 630 631 ret = i2c_master_send(client, buf, cnt + 1); 632 if (ret < 0) 633 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 634 out: 635 mutex_unlock(&priv->mutex); 636 } 637 638 static int 639 reg_read(struct tda998x_priv *priv, u16 reg) 640 { 641 u8 val = 0; 642 int ret; 643 644 ret = reg_read_range(priv, reg, &val, sizeof(val)); 645 if (ret < 0) 646 return ret; 647 return val; 648 } 649 650 static void 651 reg_write(struct tda998x_priv *priv, u16 reg, u8 val) 652 { 653 struct i2c_client *client = priv->hdmi; 654 u8 buf[] = {REG2ADDR(reg), val}; 655 int ret; 656 657 mutex_lock(&priv->mutex); 658 ret = set_page(priv, reg); 659 if (ret < 0) 660 goto out; 661 662 ret = i2c_master_send(client, buf, sizeof(buf)); 663 if (ret < 0) 664 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 665 out: 666 mutex_unlock(&priv->mutex); 667 } 668 669 static void 670 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val) 671 { 672 struct i2c_client *client = priv->hdmi; 673 u8 buf[] = {REG2ADDR(reg), val >> 8, val}; 674 int ret; 675 676 mutex_lock(&priv->mutex); 677 ret = set_page(priv, reg); 678 if (ret < 0) 679 goto out; 680 681 ret = i2c_master_send(client, buf, sizeof(buf)); 682 if (ret < 0) 683 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 684 out: 685 mutex_unlock(&priv->mutex); 686 } 687 688 static void 689 reg_set(struct tda998x_priv *priv, u16 reg, u8 val) 690 { 691 int old_val; 692 693 old_val = reg_read(priv, reg); 694 if (old_val >= 0) 695 reg_write(priv, reg, old_val | val); 696 } 697 698 static void 699 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val) 700 { 701 int old_val; 702 703 old_val = reg_read(priv, reg); 704 if (old_val >= 0) 705 reg_write(priv, reg, old_val & ~val); 706 } 707 708 static void 709 tda998x_reset(struct tda998x_priv *priv) 710 { 711 /* reset audio and i2c master: */ 712 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 713 msleep(50); 714 reg_write(priv, REG_SOFTRESET, 0); 715 msleep(50); 716 717 /* reset transmitter: */ 718 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 719 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 720 721 /* PLL registers common configuration */ 722 reg_write(priv, REG_PLL_SERIAL_1, 0x00); 723 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); 724 reg_write(priv, REG_PLL_SERIAL_3, 0x00); 725 reg_write(priv, REG_SERIALIZER, 0x00); 726 reg_write(priv, REG_BUFFER_OUT, 0x00); 727 reg_write(priv, REG_PLL_SCG1, 0x00); 728 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); 729 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 730 reg_write(priv, REG_PLL_SCGN1, 0xfa); 731 reg_write(priv, REG_PLL_SCGN2, 0x00); 732 reg_write(priv, REG_PLL_SCGR1, 0x5b); 733 reg_write(priv, REG_PLL_SCGR2, 0x00); 734 reg_write(priv, REG_PLL_SCG2, 0x10); 735 736 /* Write the default value MUX register */ 737 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24); 738 } 739 740 /* 741 * The TDA998x has a problem when trying to read the EDID close to a 742 * HPD assertion: it needs a delay of 100ms to avoid timing out while 743 * trying to read EDID data. 744 * 745 * However, tda998x_connector_get_modes() may be called at any moment 746 * after tda998x_connector_detect() indicates that we are connected, so 747 * we need to delay probing modes in tda998x_connector_get_modes() after 748 * we have seen a HPD inactive->active transition. This code implements 749 * that delay. 750 */ 751 static void tda998x_edid_delay_done(struct timer_list *t) 752 { 753 struct tda998x_priv *priv = from_timer(priv, t, edid_delay_timer); 754 755 priv->edid_delay_active = false; 756 wake_up(&priv->edid_delay_waitq); 757 schedule_work(&priv->detect_work); 758 } 759 760 static void tda998x_edid_delay_start(struct tda998x_priv *priv) 761 { 762 priv->edid_delay_active = true; 763 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10); 764 } 765 766 static int tda998x_edid_delay_wait(struct tda998x_priv *priv) 767 { 768 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active); 769 } 770 771 /* 772 * We need to run the KMS hotplug event helper outside of our threaded 773 * interrupt routine as this can call back into our get_modes method, 774 * which will want to make use of interrupts. 775 */ 776 static void tda998x_detect_work(struct work_struct *work) 777 { 778 struct tda998x_priv *priv = 779 container_of(work, struct tda998x_priv, detect_work); 780 struct drm_device *dev = priv->connector.dev; 781 782 if (dev) 783 drm_kms_helper_hotplug_event(dev); 784 } 785 786 /* 787 * only 2 interrupts may occur: screen plug/unplug and EDID read 788 */ 789 static irqreturn_t tda998x_irq_thread(int irq, void *data) 790 { 791 struct tda998x_priv *priv = data; 792 u8 sta, cec, lvl, flag0, flag1, flag2; 793 bool handled = false; 794 795 sta = cec_read(priv, REG_CEC_INTSTATUS); 796 if (sta & CEC_INTSTATUS_HDMI) { 797 cec = cec_read(priv, REG_CEC_RXSHPDINT); 798 lvl = cec_read(priv, REG_CEC_RXSHPDLEV); 799 flag0 = reg_read(priv, REG_INT_FLAGS_0); 800 flag1 = reg_read(priv, REG_INT_FLAGS_1); 801 flag2 = reg_read(priv, REG_INT_FLAGS_2); 802 DRM_DEBUG_DRIVER( 803 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n", 804 sta, cec, lvl, flag0, flag1, flag2); 805 806 if (cec & CEC_RXSHPDINT_HPD) { 807 if (lvl & CEC_RXSHPDLEV_HPD) { 808 tda998x_edid_delay_start(priv); 809 } else { 810 schedule_work(&priv->detect_work); 811 cec_notifier_phys_addr_invalidate( 812 priv->cec_notify); 813 } 814 815 handled = true; 816 } 817 818 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) { 819 priv->wq_edid_wait = 0; 820 wake_up(&priv->wq_edid); 821 handled = true; 822 } 823 } 824 825 return IRQ_RETVAL(handled); 826 } 827 828 static void 829 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr, 830 union hdmi_infoframe *frame) 831 { 832 u8 buf[MAX_WRITE_RANGE_BUF]; 833 ssize_t len; 834 835 len = hdmi_infoframe_pack(frame, buf, sizeof(buf)); 836 if (len < 0) { 837 dev_err(&priv->hdmi->dev, 838 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n", 839 frame->any.type, len); 840 return; 841 } 842 843 reg_clear(priv, REG_DIP_IF_FLAGS, bit); 844 reg_write_range(priv, addr, buf, len); 845 reg_set(priv, REG_DIP_IF_FLAGS, bit); 846 } 847 848 static void tda998x_write_aif(struct tda998x_priv *priv, 849 const struct hdmi_audio_infoframe *cea) 850 { 851 union hdmi_infoframe frame; 852 853 frame.audio = *cea; 854 855 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame); 856 } 857 858 static void 859 tda998x_write_avi(struct tda998x_priv *priv, const struct drm_display_mode *mode) 860 { 861 union hdmi_infoframe frame; 862 863 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 864 &priv->connector, mode); 865 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL; 866 drm_hdmi_avi_infoframe_quant_range(&frame.avi, &priv->connector, mode, 867 priv->rgb_quant_range); 868 869 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame); 870 } 871 872 static void tda998x_write_vsi(struct tda998x_priv *priv, 873 const struct drm_display_mode *mode) 874 { 875 union hdmi_infoframe frame; 876 877 if (drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, 878 &priv->connector, 879 mode)) 880 reg_clear(priv, REG_DIP_IF_FLAGS, DIP_IF_FLAGS_IF1); 881 else 882 tda998x_write_if(priv, DIP_IF_FLAGS_IF1, REG_IF1_HB0, &frame); 883 } 884 885 /* Audio support */ 886 887 static const struct tda998x_audio_route tda998x_audio_route[AUDIO_ROUTE_NUM] = { 888 [AUDIO_ROUTE_I2S] = { 889 .ena_aclk = 1, 890 .mux_ap = MUX_AP_SELECT_I2S, 891 .aip_clksel = AIP_CLKSEL_AIP_I2S | AIP_CLKSEL_FS_ACLK, 892 }, 893 [AUDIO_ROUTE_SPDIF] = { 894 .ena_aclk = 0, 895 .mux_ap = MUX_AP_SELECT_SPDIF, 896 .aip_clksel = AIP_CLKSEL_AIP_SPDIF | AIP_CLKSEL_FS_FS64SPDIF, 897 }, 898 }; 899 900 /* Configure the TDA998x audio data and clock routing. */ 901 static int tda998x_derive_routing(struct tda998x_priv *priv, 902 struct tda998x_audio_settings *s, 903 unsigned int route) 904 { 905 s->route = &tda998x_audio_route[route]; 906 s->ena_ap = priv->audio_port_enable[route]; 907 if (s->ena_ap == 0) { 908 dev_err(&priv->hdmi->dev, "no audio configuration found\n"); 909 return -EINVAL; 910 } 911 912 return 0; 913 } 914 915 /* 916 * The audio clock divisor register controls a divider producing Audio_Clk_Out 917 * from SERclk by dividing it by 2^n where 0 <= n <= 5. We don't know what 918 * Audio_Clk_Out or SERclk are. We guess SERclk is the same as TMDS clock. 919 * 920 * It seems that Audio_Clk_Out must be the smallest value that is greater 921 * than 128*fs, otherwise audio does not function. There is some suggestion 922 * that 126*fs is a better value. 923 */ 924 static u8 tda998x_get_adiv(struct tda998x_priv *priv, unsigned int fs) 925 { 926 unsigned long min_audio_clk = fs * 128; 927 unsigned long ser_clk = priv->tmds_clock * 1000; 928 u8 adiv; 929 930 for (adiv = AUDIO_DIV_SERCLK_32; adiv != AUDIO_DIV_SERCLK_1; adiv--) 931 if (ser_clk > min_audio_clk << adiv) 932 break; 933 934 dev_dbg(&priv->hdmi->dev, 935 "ser_clk=%luHz fs=%uHz min_aclk=%luHz adiv=%d\n", 936 ser_clk, fs, min_audio_clk, adiv); 937 938 return adiv; 939 } 940 941 /* 942 * In auto-CTS mode, the TDA998x uses a "measured time stamp" counter to 943 * generate the CTS value. It appears that the "measured time stamp" is 944 * the number of TDMS clock cycles within a number of audio input clock 945 * cycles defined by the k and N parameters defined below, in a similar 946 * way to that which is set out in the CTS generation in the HDMI spec. 947 * 948 * tmdsclk ----> mts -> /m ---> CTS 949 * ^ 950 * sclk -> /k -> /N 951 * 952 * CTS = mts / m, where m is 2^M. 953 * /k is a divider based on the K value below, K+1 for K < 4, or 8 for K >= 4 954 * /N is a divider based on the HDMI specified N value. 955 * 956 * This produces the following equation: 957 * CTS = tmds_clock * k * N / (sclk * m) 958 * 959 * When combined with the sink-side equation, and realising that sclk is 960 * bclk_ratio * fs, we end up with: 961 * k = m * bclk_ratio / 128. 962 * 963 * Note: S/PDIF always uses a bclk_ratio of 64. 964 */ 965 static int tda998x_derive_cts_n(struct tda998x_priv *priv, 966 struct tda998x_audio_settings *settings, 967 unsigned int ratio) 968 { 969 switch (ratio) { 970 case 16: 971 settings->cts_n = CTS_N_M(3) | CTS_N_K(0); 972 break; 973 case 32: 974 settings->cts_n = CTS_N_M(3) | CTS_N_K(1); 975 break; 976 case 48: 977 settings->cts_n = CTS_N_M(3) | CTS_N_K(2); 978 break; 979 case 64: 980 settings->cts_n = CTS_N_M(3) | CTS_N_K(3); 981 break; 982 case 128: 983 settings->cts_n = CTS_N_M(0) | CTS_N_K(0); 984 break; 985 default: 986 dev_err(&priv->hdmi->dev, "unsupported bclk ratio %ufs\n", 987 ratio); 988 return -EINVAL; 989 } 990 return 0; 991 } 992 993 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on) 994 { 995 if (on) { 996 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO); 997 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO); 998 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 999 } else { 1000 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 1001 } 1002 } 1003 1004 static void tda998x_configure_audio(struct tda998x_priv *priv) 1005 { 1006 const struct tda998x_audio_settings *settings = &priv->audio; 1007 u8 buf[6], adiv; 1008 u32 n; 1009 1010 /* If audio is not configured, there is nothing to do. */ 1011 if (settings->ena_ap == 0) 1012 return; 1013 1014 adiv = tda998x_get_adiv(priv, settings->sample_rate); 1015 1016 /* Enable audio ports */ 1017 reg_write(priv, REG_ENA_AP, settings->ena_ap); 1018 reg_write(priv, REG_ENA_ACLK, settings->route->ena_aclk); 1019 reg_write(priv, REG_MUX_AP, settings->route->mux_ap); 1020 reg_write(priv, REG_I2S_FORMAT, settings->i2s_format); 1021 reg_write(priv, REG_AIP_CLKSEL, settings->route->aip_clksel); 1022 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT | 1023 AIP_CNTRL_0_ACR_MAN); /* auto CTS */ 1024 reg_write(priv, REG_CTS_N, settings->cts_n); 1025 reg_write(priv, REG_AUDIO_DIV, adiv); 1026 1027 /* 1028 * This is the approximate value of N, which happens to be 1029 * the recommended values for non-coherent clocks. 1030 */ 1031 n = 128 * settings->sample_rate / 1000; 1032 1033 /* Write the CTS and N values */ 1034 buf[0] = 0x44; 1035 buf[1] = 0x42; 1036 buf[2] = 0x01; 1037 buf[3] = n; 1038 buf[4] = n >> 8; 1039 buf[5] = n >> 16; 1040 reg_write_range(priv, REG_ACR_CTS_0, buf, 6); 1041 1042 /* Reset CTS generator */ 1043 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 1044 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 1045 1046 /* Write the channel status 1047 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because 1048 * there is a separate register for each I2S wire. 1049 */ 1050 buf[0] = settings->status[0]; 1051 buf[1] = settings->status[1]; 1052 buf[2] = settings->status[3]; 1053 buf[3] = settings->status[4]; 1054 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4); 1055 1056 tda998x_audio_mute(priv, true); 1057 msleep(20); 1058 tda998x_audio_mute(priv, false); 1059 1060 tda998x_write_aif(priv, &settings->cea); 1061 } 1062 1063 static int tda998x_audio_hw_params(struct device *dev, void *data, 1064 struct hdmi_codec_daifmt *daifmt, 1065 struct hdmi_codec_params *params) 1066 { 1067 struct tda998x_priv *priv = dev_get_drvdata(dev); 1068 unsigned int bclk_ratio; 1069 bool spdif = daifmt->fmt == HDMI_SPDIF; 1070 int ret; 1071 struct tda998x_audio_settings audio = { 1072 .sample_rate = params->sample_rate, 1073 .cea = params->cea, 1074 }; 1075 1076 memcpy(audio.status, params->iec.status, 1077 min(sizeof(audio.status), sizeof(params->iec.status))); 1078 1079 switch (daifmt->fmt) { 1080 case HDMI_I2S: 1081 audio.i2s_format = I2S_FORMAT_PHILIPS; 1082 break; 1083 case HDMI_LEFT_J: 1084 audio.i2s_format = I2S_FORMAT_LEFT_J; 1085 break; 1086 case HDMI_RIGHT_J: 1087 audio.i2s_format = I2S_FORMAT_RIGHT_J; 1088 break; 1089 case HDMI_SPDIF: 1090 audio.i2s_format = 0; 1091 break; 1092 default: 1093 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt); 1094 return -EINVAL; 1095 } 1096 1097 if (!spdif && 1098 (daifmt->bit_clk_inv || daifmt->frame_clk_inv || 1099 daifmt->bit_clk_provider || daifmt->frame_clk_provider)) { 1100 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__, 1101 daifmt->bit_clk_inv, daifmt->frame_clk_inv, 1102 daifmt->bit_clk_provider, 1103 daifmt->frame_clk_provider); 1104 return -EINVAL; 1105 } 1106 1107 ret = tda998x_derive_routing(priv, &audio, AUDIO_ROUTE_I2S + spdif); 1108 if (ret < 0) 1109 return ret; 1110 1111 bclk_ratio = spdif ? 64 : params->sample_width * 2; 1112 ret = tda998x_derive_cts_n(priv, &audio, bclk_ratio); 1113 if (ret < 0) 1114 return ret; 1115 1116 mutex_lock(&priv->audio_mutex); 1117 priv->audio = audio; 1118 if (priv->supports_infoframes && priv->sink_has_audio) 1119 tda998x_configure_audio(priv); 1120 mutex_unlock(&priv->audio_mutex); 1121 1122 return 0; 1123 } 1124 1125 static void tda998x_audio_shutdown(struct device *dev, void *data) 1126 { 1127 struct tda998x_priv *priv = dev_get_drvdata(dev); 1128 1129 mutex_lock(&priv->audio_mutex); 1130 1131 reg_write(priv, REG_ENA_AP, 0); 1132 priv->audio.ena_ap = 0; 1133 1134 mutex_unlock(&priv->audio_mutex); 1135 } 1136 1137 static int tda998x_audio_mute_stream(struct device *dev, void *data, 1138 bool enable, int direction) 1139 { 1140 struct tda998x_priv *priv = dev_get_drvdata(dev); 1141 1142 mutex_lock(&priv->audio_mutex); 1143 1144 tda998x_audio_mute(priv, enable); 1145 1146 mutex_unlock(&priv->audio_mutex); 1147 return 0; 1148 } 1149 1150 static int tda998x_audio_get_eld(struct device *dev, void *data, 1151 uint8_t *buf, size_t len) 1152 { 1153 struct tda998x_priv *priv = dev_get_drvdata(dev); 1154 1155 mutex_lock(&priv->audio_mutex); 1156 memcpy(buf, priv->connector.eld, 1157 min(sizeof(priv->connector.eld), len)); 1158 mutex_unlock(&priv->audio_mutex); 1159 1160 return 0; 1161 } 1162 1163 static const struct hdmi_codec_ops audio_codec_ops = { 1164 .hw_params = tda998x_audio_hw_params, 1165 .audio_shutdown = tda998x_audio_shutdown, 1166 .mute_stream = tda998x_audio_mute_stream, 1167 .get_eld = tda998x_audio_get_eld, 1168 .no_capture_mute = 1, 1169 }; 1170 1171 static int tda998x_audio_codec_init(struct tda998x_priv *priv, 1172 struct device *dev) 1173 { 1174 struct hdmi_codec_pdata codec_data = { 1175 .ops = &audio_codec_ops, 1176 .max_i2s_channels = 2, 1177 }; 1178 1179 if (priv->audio_port_enable[AUDIO_ROUTE_I2S]) 1180 codec_data.i2s = 1; 1181 if (priv->audio_port_enable[AUDIO_ROUTE_SPDIF]) 1182 codec_data.spdif = 1; 1183 1184 priv->audio_pdev = platform_device_register_data( 1185 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, 1186 &codec_data, sizeof(codec_data)); 1187 1188 return PTR_ERR_OR_ZERO(priv->audio_pdev); 1189 } 1190 1191 /* DRM connector functions */ 1192 1193 static enum drm_connector_status 1194 tda998x_connector_detect(struct drm_connector *connector, bool force) 1195 { 1196 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1197 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV); 1198 1199 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : 1200 connector_status_disconnected; 1201 } 1202 1203 static void tda998x_connector_destroy(struct drm_connector *connector) 1204 { 1205 drm_connector_cleanup(connector); 1206 } 1207 1208 static const struct drm_connector_funcs tda998x_connector_funcs = { 1209 .reset = drm_atomic_helper_connector_reset, 1210 .fill_modes = drm_helper_probe_single_connector_modes, 1211 .detect = tda998x_connector_detect, 1212 .destroy = tda998x_connector_destroy, 1213 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1214 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1215 }; 1216 1217 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length) 1218 { 1219 struct tda998x_priv *priv = data; 1220 u8 offset, segptr; 1221 int ret, i; 1222 1223 offset = (blk & 1) ? 128 : 0; 1224 segptr = blk / 2; 1225 1226 mutex_lock(&priv->edid_mutex); 1227 1228 reg_write(priv, REG_DDC_ADDR, 0xa0); 1229 reg_write(priv, REG_DDC_OFFS, offset); 1230 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60); 1231 reg_write(priv, REG_DDC_SEGM, segptr); 1232 1233 /* enable reading EDID: */ 1234 priv->wq_edid_wait = 1; 1235 reg_write(priv, REG_EDID_CTRL, 0x1); 1236 1237 /* flag must be cleared by sw: */ 1238 reg_write(priv, REG_EDID_CTRL, 0x0); 1239 1240 /* wait for block read to complete: */ 1241 if (priv->hdmi->irq) { 1242 i = wait_event_timeout(priv->wq_edid, 1243 !priv->wq_edid_wait, 1244 msecs_to_jiffies(100)); 1245 if (i < 0) { 1246 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i); 1247 ret = i; 1248 goto failed; 1249 } 1250 } else { 1251 for (i = 100; i > 0; i--) { 1252 msleep(1); 1253 ret = reg_read(priv, REG_INT_FLAGS_2); 1254 if (ret < 0) 1255 goto failed; 1256 if (ret & INT_FLAGS_2_EDID_BLK_RD) 1257 break; 1258 } 1259 } 1260 1261 if (i == 0) { 1262 dev_err(&priv->hdmi->dev, "read edid timeout\n"); 1263 ret = -ETIMEDOUT; 1264 goto failed; 1265 } 1266 1267 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length); 1268 if (ret != length) { 1269 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n", 1270 blk, ret); 1271 goto failed; 1272 } 1273 1274 ret = 0; 1275 1276 failed: 1277 mutex_unlock(&priv->edid_mutex); 1278 return ret; 1279 } 1280 1281 static int tda998x_connector_get_modes(struct drm_connector *connector) 1282 { 1283 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1284 struct edid *edid; 1285 int n; 1286 1287 /* 1288 * If we get killed while waiting for the HPD timeout, return 1289 * no modes found: we are not in a restartable path, so we 1290 * can't handle signals gracefully. 1291 */ 1292 if (tda998x_edid_delay_wait(priv)) 1293 return 0; 1294 1295 if (priv->rev == TDA19988) 1296 reg_clear(priv, REG_TX4, TX4_PD_RAM); 1297 1298 edid = drm_do_get_edid(connector, read_edid_block, priv); 1299 1300 if (priv->rev == TDA19988) 1301 reg_set(priv, REG_TX4, TX4_PD_RAM); 1302 1303 if (!edid) { 1304 dev_warn(&priv->hdmi->dev, "failed to read EDID\n"); 1305 return 0; 1306 } 1307 1308 drm_connector_update_edid_property(connector, edid); 1309 cec_notifier_set_phys_addr_from_edid(priv->cec_notify, edid); 1310 1311 mutex_lock(&priv->audio_mutex); 1312 n = drm_add_edid_modes(connector, edid); 1313 priv->sink_has_audio = drm_detect_monitor_audio(edid); 1314 mutex_unlock(&priv->audio_mutex); 1315 1316 kfree(edid); 1317 1318 return n; 1319 } 1320 1321 static struct drm_encoder * 1322 tda998x_connector_best_encoder(struct drm_connector *connector) 1323 { 1324 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1325 1326 return priv->bridge.encoder; 1327 } 1328 1329 static 1330 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = { 1331 .get_modes = tda998x_connector_get_modes, 1332 .best_encoder = tda998x_connector_best_encoder, 1333 }; 1334 1335 static int tda998x_connector_init(struct tda998x_priv *priv, 1336 struct drm_device *drm) 1337 { 1338 struct drm_connector *connector = &priv->connector; 1339 int ret; 1340 1341 connector->interlace_allowed = 1; 1342 1343 if (priv->hdmi->irq) 1344 connector->polled = DRM_CONNECTOR_POLL_HPD; 1345 else 1346 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1347 DRM_CONNECTOR_POLL_DISCONNECT; 1348 1349 drm_connector_helper_add(connector, &tda998x_connector_helper_funcs); 1350 ret = drm_connector_init(drm, connector, &tda998x_connector_funcs, 1351 DRM_MODE_CONNECTOR_HDMIA); 1352 if (ret) 1353 return ret; 1354 1355 drm_connector_attach_encoder(&priv->connector, 1356 priv->bridge.encoder); 1357 1358 return 0; 1359 } 1360 1361 /* DRM bridge functions */ 1362 1363 static int tda998x_bridge_attach(struct drm_bridge *bridge, 1364 enum drm_bridge_attach_flags flags) 1365 { 1366 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1367 1368 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) { 1369 DRM_ERROR("Fix bridge driver to make connector optional!"); 1370 return -EINVAL; 1371 } 1372 1373 return tda998x_connector_init(priv, bridge->dev); 1374 } 1375 1376 static void tda998x_bridge_detach(struct drm_bridge *bridge) 1377 { 1378 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1379 1380 drm_connector_cleanup(&priv->connector); 1381 } 1382 1383 static enum drm_mode_status tda998x_bridge_mode_valid(struct drm_bridge *bridge, 1384 const struct drm_display_info *info, 1385 const struct drm_display_mode *mode) 1386 { 1387 /* TDA19988 dotclock can go up to 165MHz */ 1388 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1389 1390 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000)) 1391 return MODE_CLOCK_HIGH; 1392 if (mode->htotal >= BIT(13)) 1393 return MODE_BAD_HVALUE; 1394 if (mode->vtotal >= BIT(11)) 1395 return MODE_BAD_VVALUE; 1396 return MODE_OK; 1397 } 1398 1399 static void tda998x_bridge_enable(struct drm_bridge *bridge) 1400 { 1401 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1402 1403 if (!priv->is_on) { 1404 /* enable video ports, audio will be enabled later */ 1405 reg_write(priv, REG_ENA_VP_0, 0xff); 1406 reg_write(priv, REG_ENA_VP_1, 0xff); 1407 reg_write(priv, REG_ENA_VP_2, 0xff); 1408 /* set muxing after enabling ports: */ 1409 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0); 1410 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1); 1411 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2); 1412 1413 priv->is_on = true; 1414 } 1415 } 1416 1417 static void tda998x_bridge_disable(struct drm_bridge *bridge) 1418 { 1419 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1420 1421 if (priv->is_on) { 1422 /* disable video ports */ 1423 reg_write(priv, REG_ENA_VP_0, 0x00); 1424 reg_write(priv, REG_ENA_VP_1, 0x00); 1425 reg_write(priv, REG_ENA_VP_2, 0x00); 1426 1427 priv->is_on = false; 1428 } 1429 } 1430 1431 static void tda998x_bridge_mode_set(struct drm_bridge *bridge, 1432 const struct drm_display_mode *mode, 1433 const struct drm_display_mode *adjusted_mode) 1434 { 1435 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1436 unsigned long tmds_clock; 1437 u16 ref_pix, ref_line, n_pix, n_line; 1438 u16 hs_pix_s, hs_pix_e; 1439 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e; 1440 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e; 1441 u16 vwin1_line_s, vwin1_line_e; 1442 u16 vwin2_line_s, vwin2_line_e; 1443 u16 de_pix_s, de_pix_e; 1444 u8 reg, div, rep, sel_clk; 1445 1446 /* 1447 * Since we are "computer" like, our source invariably produces 1448 * full-range RGB. If the monitor supports full-range, then use 1449 * it, otherwise reduce to limited-range. 1450 */ 1451 priv->rgb_quant_range = 1452 priv->connector.display_info.rgb_quant_range_selectable ? 1453 HDMI_QUANTIZATION_RANGE_FULL : 1454 drm_default_rgb_quant_range(adjusted_mode); 1455 1456 /* 1457 * Internally TDA998x is using ITU-R BT.656 style sync but 1458 * we get VESA style sync. TDA998x is using a reference pixel 1459 * relative to ITU to sync to the input frame and for output 1460 * sync generation. Currently, we are using reference detection 1461 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point 1462 * which is position of rising VS with coincident rising HS. 1463 * 1464 * Now there is some issues to take care of: 1465 * - HDMI data islands require sync-before-active 1466 * - TDA998x register values must be > 0 to be enabled 1467 * - REFLINE needs an additional offset of +1 1468 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB 1469 * 1470 * So we add +1 to all horizontal and vertical register values, 1471 * plus an additional +3 for REFPIX as we are using RGB input only. 1472 */ 1473 n_pix = mode->htotal; 1474 n_line = mode->vtotal; 1475 1476 hs_pix_e = mode->hsync_end - mode->hdisplay; 1477 hs_pix_s = mode->hsync_start - mode->hdisplay; 1478 de_pix_e = mode->htotal; 1479 de_pix_s = mode->htotal - mode->hdisplay; 1480 ref_pix = 3 + hs_pix_s; 1481 1482 /* 1483 * Attached LCD controllers may generate broken sync. Allow 1484 * those to adjust the position of the rising VS edge by adding 1485 * HSKEW to ref_pix. 1486 */ 1487 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) 1488 ref_pix += adjusted_mode->hskew; 1489 1490 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { 1491 ref_line = 1 + mode->vsync_start - mode->vdisplay; 1492 vwin1_line_s = mode->vtotal - mode->vdisplay - 1; 1493 vwin1_line_e = vwin1_line_s + mode->vdisplay; 1494 vs1_pix_s = vs1_pix_e = hs_pix_s; 1495 vs1_line_s = mode->vsync_start - mode->vdisplay; 1496 vs1_line_e = vs1_line_s + 1497 mode->vsync_end - mode->vsync_start; 1498 vwin2_line_s = vwin2_line_e = 0; 1499 vs2_pix_s = vs2_pix_e = 0; 1500 vs2_line_s = vs2_line_e = 0; 1501 } else { 1502 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; 1503 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; 1504 vwin1_line_e = vwin1_line_s + mode->vdisplay/2; 1505 vs1_pix_s = vs1_pix_e = hs_pix_s; 1506 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; 1507 vs1_line_e = vs1_line_s + 1508 (mode->vsync_end - mode->vsync_start)/2; 1509 vwin2_line_s = vwin1_line_s + mode->vtotal/2; 1510 vwin2_line_e = vwin2_line_s + mode->vdisplay/2; 1511 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; 1512 vs2_line_s = vs1_line_s + mode->vtotal/2 ; 1513 vs2_line_e = vs2_line_s + 1514 (mode->vsync_end - mode->vsync_start)/2; 1515 } 1516 1517 /* 1518 * Select pixel repeat depending on the double-clock flag 1519 * (which means we have to repeat each pixel once.) 1520 */ 1521 rep = mode->flags & DRM_MODE_FLAG_DBLCLK ? 1 : 0; 1522 sel_clk = SEL_CLK_ENA_SC_CLK | SEL_CLK_SEL_CLK1 | 1523 SEL_CLK_SEL_VRF_CLK(rep ? 2 : 0); 1524 1525 /* the TMDS clock is scaled up by the pixel repeat */ 1526 tmds_clock = mode->clock * (1 + rep); 1527 1528 /* 1529 * The divisor is power-of-2. The TDA9983B datasheet gives 1530 * this as ranges of Msample/s, which is 10x the TMDS clock: 1531 * 0 - 800 to 1500 Msample/s 1532 * 1 - 400 to 800 Msample/s 1533 * 2 - 200 to 400 Msample/s 1534 * 3 - as 2 above 1535 */ 1536 for (div = 0; div < 3; div++) 1537 if (80000 >> div <= tmds_clock) 1538 break; 1539 1540 mutex_lock(&priv->audio_mutex); 1541 1542 priv->tmds_clock = tmds_clock; 1543 1544 /* mute the audio FIFO: */ 1545 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 1546 1547 /* set HDMI HDCP mode off: */ 1548 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 1549 reg_clear(priv, REG_TX33, TX33_HDMI); 1550 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); 1551 1552 /* no pre-filter or interpolator: */ 1553 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | 1554 HVF_CNTRL_0_INTPOL(0)); 1555 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT); 1556 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); 1557 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | 1558 VIP_CNTRL_4_BLC(0)); 1559 1560 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); 1561 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR | 1562 PLL_SERIAL_3_SRL_DE); 1563 reg_write(priv, REG_SERIALIZER, 0); 1564 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); 1565 1566 reg_write(priv, REG_RPT_CNTRL, RPT_CNTRL_REPEAT(rep)); 1567 reg_write(priv, REG_SEL_CLK, sel_clk); 1568 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | 1569 PLL_SERIAL_2_SRL_PR(rep)); 1570 1571 /* set color matrix according to output rgb quant range */ 1572 if (priv->rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) { 1573 static u8 tda998x_full_to_limited_range[] = { 1574 MAT_CONTRL_MAT_SC(2), 1575 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1576 0x03, 0x6f, 0x00, 0x00, 0x00, 0x00, 1577 0x00, 0x00, 0x03, 0x6f, 0x00, 0x00, 1578 0x00, 0x00, 0x00, 0x00, 0x03, 0x6f, 1579 0x00, 0x40, 0x00, 0x40, 0x00, 0x40 1580 }; 1581 reg_clear(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC); 1582 reg_write_range(priv, REG_MAT_CONTRL, 1583 tda998x_full_to_limited_range, 1584 sizeof(tda998x_full_to_limited_range)); 1585 } else { 1586 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP | 1587 MAT_CONTRL_MAT_SC(1)); 1588 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC); 1589 } 1590 1591 /* set BIAS tmds value: */ 1592 reg_write(priv, REG_ANA_GENERAL, 0x09); 1593 1594 /* 1595 * Sync on rising HSYNC/VSYNC 1596 */ 1597 reg = VIP_CNTRL_3_SYNC_HS; 1598 1599 /* 1600 * TDA19988 requires high-active sync at input stage, 1601 * so invert low-active sync provided by master encoder here 1602 */ 1603 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1604 reg |= VIP_CNTRL_3_H_TGL; 1605 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1606 reg |= VIP_CNTRL_3_V_TGL; 1607 reg_write(priv, REG_VIP_CNTRL_3, reg); 1608 1609 reg_write(priv, REG_VIDFORMAT, 0x00); 1610 reg_write16(priv, REG_REFPIX_MSB, ref_pix); 1611 reg_write16(priv, REG_REFLINE_MSB, ref_line); 1612 reg_write16(priv, REG_NPIX_MSB, n_pix); 1613 reg_write16(priv, REG_NLINE_MSB, n_line); 1614 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s); 1615 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s); 1616 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e); 1617 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e); 1618 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s); 1619 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s); 1620 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e); 1621 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e); 1622 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s); 1623 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e); 1624 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s); 1625 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e); 1626 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s); 1627 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e); 1628 reg_write16(priv, REG_DE_START_MSB, de_pix_s); 1629 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e); 1630 1631 if (priv->rev == TDA19988) { 1632 /* let incoming pixels fill the active space (if any) */ 1633 reg_write(priv, REG_ENABLE_SPACE, 0x00); 1634 } 1635 1636 /* 1637 * Always generate sync polarity relative to input sync and 1638 * revert input stage toggled sync at output stage 1639 */ 1640 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN; 1641 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1642 reg |= TBG_CNTRL_1_H_TGL; 1643 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1644 reg |= TBG_CNTRL_1_V_TGL; 1645 reg_write(priv, REG_TBG_CNTRL_1, reg); 1646 1647 /* must be last register set: */ 1648 reg_write(priv, REG_TBG_CNTRL_0, 0); 1649 1650 /* CEA-861B section 6 says that: 1651 * CEA version 1 (CEA-861) has no support for infoframes. 1652 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes, 1653 * and optional basic audio. 1654 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes, 1655 * and optional digital audio, with audio infoframes. 1656 * 1657 * Since we only support generation of version 2 AVI infoframes, 1658 * ignore CEA version 2 and below (iow, behave as if we're a 1659 * CEA-861 source.) 1660 */ 1661 priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3; 1662 1663 if (priv->supports_infoframes) { 1664 /* We need to turn HDMI HDCP stuff on to get audio through */ 1665 reg &= ~TBG_CNTRL_1_DWIN_DIS; 1666 reg_write(priv, REG_TBG_CNTRL_1, reg); 1667 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); 1668 reg_set(priv, REG_TX33, TX33_HDMI); 1669 1670 tda998x_write_avi(priv, adjusted_mode); 1671 tda998x_write_vsi(priv, adjusted_mode); 1672 1673 if (priv->sink_has_audio) 1674 tda998x_configure_audio(priv); 1675 } 1676 1677 mutex_unlock(&priv->audio_mutex); 1678 } 1679 1680 static const struct drm_bridge_funcs tda998x_bridge_funcs = { 1681 .attach = tda998x_bridge_attach, 1682 .detach = tda998x_bridge_detach, 1683 .mode_valid = tda998x_bridge_mode_valid, 1684 .disable = tda998x_bridge_disable, 1685 .mode_set = tda998x_bridge_mode_set, 1686 .enable = tda998x_bridge_enable, 1687 }; 1688 1689 /* I2C driver functions */ 1690 1691 static int tda998x_get_audio_ports(struct tda998x_priv *priv, 1692 struct device_node *np) 1693 { 1694 const u32 *port_data; 1695 u32 size; 1696 int i; 1697 1698 port_data = of_get_property(np, "audio-ports", &size); 1699 if (!port_data) 1700 return 0; 1701 1702 size /= sizeof(u32); 1703 if (size > 2 * ARRAY_SIZE(priv->audio_port_enable) || size % 2 != 0) { 1704 dev_err(&priv->hdmi->dev, 1705 "Bad number of elements in audio-ports dt-property\n"); 1706 return -EINVAL; 1707 } 1708 1709 size /= 2; 1710 1711 for (i = 0; i < size; i++) { 1712 unsigned int route; 1713 u8 afmt = be32_to_cpup(&port_data[2*i]); 1714 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]); 1715 1716 switch (afmt) { 1717 case AFMT_I2S: 1718 route = AUDIO_ROUTE_I2S; 1719 break; 1720 case AFMT_SPDIF: 1721 route = AUDIO_ROUTE_SPDIF; 1722 break; 1723 default: 1724 dev_err(&priv->hdmi->dev, 1725 "Bad audio format %u\n", afmt); 1726 return -EINVAL; 1727 } 1728 1729 if (!ena_ap) { 1730 dev_err(&priv->hdmi->dev, "invalid zero port config\n"); 1731 continue; 1732 } 1733 1734 if (priv->audio_port_enable[route]) { 1735 dev_err(&priv->hdmi->dev, 1736 "%s format already configured\n", 1737 route == AUDIO_ROUTE_SPDIF ? "SPDIF" : "I2S"); 1738 return -EINVAL; 1739 } 1740 1741 priv->audio_port_enable[route] = ena_ap; 1742 } 1743 return 0; 1744 } 1745 1746 static int tda998x_set_config(struct tda998x_priv *priv, 1747 const struct tda998x_encoder_params *p) 1748 { 1749 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | 1750 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | 1751 VIP_CNTRL_0_SWAP_B(p->swap_b) | 1752 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); 1753 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | 1754 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | 1755 VIP_CNTRL_1_SWAP_D(p->swap_d) | 1756 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); 1757 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | 1758 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | 1759 VIP_CNTRL_2_SWAP_F(p->swap_f) | 1760 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); 1761 1762 if (p->audio_params.format != AFMT_UNUSED) { 1763 unsigned int ratio, route; 1764 bool spdif = p->audio_params.format == AFMT_SPDIF; 1765 1766 route = AUDIO_ROUTE_I2S + spdif; 1767 1768 priv->audio.route = &tda998x_audio_route[route]; 1769 priv->audio.cea = p->audio_params.cea; 1770 priv->audio.sample_rate = p->audio_params.sample_rate; 1771 memcpy(priv->audio.status, p->audio_params.status, 1772 min(sizeof(priv->audio.status), 1773 sizeof(p->audio_params.status))); 1774 priv->audio.ena_ap = p->audio_params.config; 1775 priv->audio.i2s_format = I2S_FORMAT_PHILIPS; 1776 1777 ratio = spdif ? 64 : p->audio_params.sample_width * 2; 1778 return tda998x_derive_cts_n(priv, &priv->audio, ratio); 1779 } 1780 1781 return 0; 1782 } 1783 1784 static void tda998x_destroy(struct device *dev) 1785 { 1786 struct tda998x_priv *priv = dev_get_drvdata(dev); 1787 1788 drm_bridge_remove(&priv->bridge); 1789 1790 /* disable all IRQs and free the IRQ handler */ 1791 cec_write(priv, REG_CEC_RXSHPDINTENA, 0); 1792 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 1793 1794 if (priv->audio_pdev) 1795 platform_device_unregister(priv->audio_pdev); 1796 1797 if (priv->hdmi->irq) 1798 free_irq(priv->hdmi->irq, priv); 1799 1800 del_timer_sync(&priv->edid_delay_timer); 1801 cancel_work_sync(&priv->detect_work); 1802 1803 i2c_unregister_device(priv->cec); 1804 1805 cec_notifier_conn_unregister(priv->cec_notify); 1806 } 1807 1808 static int tda998x_create(struct device *dev) 1809 { 1810 struct i2c_client *client = to_i2c_client(dev); 1811 struct device_node *np = client->dev.of_node; 1812 struct i2c_board_info cec_info; 1813 struct tda998x_priv *priv; 1814 u32 video; 1815 int rev_lo, rev_hi, ret; 1816 1817 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1818 if (!priv) 1819 return -ENOMEM; 1820 1821 dev_set_drvdata(dev, priv); 1822 1823 mutex_init(&priv->mutex); /* protect the page access */ 1824 mutex_init(&priv->audio_mutex); /* protect access from audio thread */ 1825 mutex_init(&priv->edid_mutex); 1826 INIT_LIST_HEAD(&priv->bridge.list); 1827 init_waitqueue_head(&priv->edid_delay_waitq); 1828 timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0); 1829 INIT_WORK(&priv->detect_work, tda998x_detect_work); 1830 1831 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); 1832 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); 1833 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); 1834 1835 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */ 1836 priv->cec_addr = 0x34 + (client->addr & 0x03); 1837 priv->current_page = 0xff; 1838 priv->hdmi = client; 1839 1840 /* wake up the device: */ 1841 cec_write(priv, REG_CEC_ENAMODS, 1842 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); 1843 1844 tda998x_reset(priv); 1845 1846 /* read version: */ 1847 rev_lo = reg_read(priv, REG_VERSION_LSB); 1848 if (rev_lo < 0) { 1849 dev_err(dev, "failed to read version: %d\n", rev_lo); 1850 return rev_lo; 1851 } 1852 1853 rev_hi = reg_read(priv, REG_VERSION_MSB); 1854 if (rev_hi < 0) { 1855 dev_err(dev, "failed to read version: %d\n", rev_hi); 1856 return rev_hi; 1857 } 1858 1859 priv->rev = rev_lo | rev_hi << 8; 1860 1861 /* mask off feature bits: */ 1862 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ 1863 1864 switch (priv->rev) { 1865 case TDA9989N2: 1866 dev_info(dev, "found TDA9989 n2"); 1867 break; 1868 case TDA19989: 1869 dev_info(dev, "found TDA19989"); 1870 break; 1871 case TDA19989N2: 1872 dev_info(dev, "found TDA19989 n2"); 1873 break; 1874 case TDA19988: 1875 dev_info(dev, "found TDA19988"); 1876 break; 1877 default: 1878 dev_err(dev, "found unsupported device: %04x\n", priv->rev); 1879 return -ENXIO; 1880 } 1881 1882 /* after reset, enable DDC: */ 1883 reg_write(priv, REG_DDC_DISABLE, 0x00); 1884 1885 /* set clock on DDC channel: */ 1886 reg_write(priv, REG_TX3, 39); 1887 1888 /* if necessary, disable multi-master: */ 1889 if (priv->rev == TDA19989) 1890 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM); 1891 1892 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL, 1893 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); 1894 1895 /* ensure interrupts are disabled */ 1896 cec_write(priv, REG_CEC_RXSHPDINTENA, 0); 1897 1898 /* clear pending interrupts */ 1899 cec_read(priv, REG_CEC_RXSHPDINT); 1900 reg_read(priv, REG_INT_FLAGS_0); 1901 reg_read(priv, REG_INT_FLAGS_1); 1902 reg_read(priv, REG_INT_FLAGS_2); 1903 1904 /* initialize the optional IRQ */ 1905 if (client->irq) { 1906 unsigned long irq_flags; 1907 1908 /* init read EDID waitqueue and HDP work */ 1909 init_waitqueue_head(&priv->wq_edid); 1910 1911 irq_flags = 1912 irqd_get_trigger_type(irq_get_irq_data(client->irq)); 1913 1914 priv->cec_glue.irq_flags = irq_flags; 1915 1916 irq_flags |= IRQF_SHARED | IRQF_ONESHOT; 1917 ret = request_threaded_irq(client->irq, NULL, 1918 tda998x_irq_thread, irq_flags, 1919 "tda998x", priv); 1920 if (ret) { 1921 dev_err(dev, "failed to request IRQ#%u: %d\n", 1922 client->irq, ret); 1923 goto err_irq; 1924 } 1925 1926 /* enable HPD irq */ 1927 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD); 1928 } 1929 1930 priv->cec_notify = cec_notifier_conn_register(dev, NULL, NULL); 1931 if (!priv->cec_notify) { 1932 ret = -ENOMEM; 1933 goto fail; 1934 } 1935 1936 priv->cec_glue.parent = dev; 1937 priv->cec_glue.data = priv; 1938 priv->cec_glue.init = tda998x_cec_hook_init; 1939 priv->cec_glue.exit = tda998x_cec_hook_exit; 1940 priv->cec_glue.open = tda998x_cec_hook_open; 1941 priv->cec_glue.release = tda998x_cec_hook_release; 1942 1943 /* 1944 * Some TDA998x are actually two I2C devices merged onto one piece 1945 * of silicon: TDA9989 and TDA19989 combine the HDMI transmitter 1946 * with a slightly modified TDA9950 CEC device. The CEC device 1947 * is at the TDA9950 address, with the address pins strapped across 1948 * to the TDA998x address pins. Hence, it always has the same 1949 * offset. 1950 */ 1951 memset(&cec_info, 0, sizeof(cec_info)); 1952 strlcpy(cec_info.type, "tda9950", sizeof(cec_info.type)); 1953 cec_info.addr = priv->cec_addr; 1954 cec_info.platform_data = &priv->cec_glue; 1955 cec_info.irq = client->irq; 1956 1957 priv->cec = i2c_new_client_device(client->adapter, &cec_info); 1958 if (IS_ERR(priv->cec)) { 1959 ret = PTR_ERR(priv->cec); 1960 goto fail; 1961 } 1962 1963 /* enable EDID read irq: */ 1964 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 1965 1966 if (np) { 1967 /* get the device tree parameters */ 1968 ret = of_property_read_u32(np, "video-ports", &video); 1969 if (ret == 0) { 1970 priv->vip_cntrl_0 = video >> 16; 1971 priv->vip_cntrl_1 = video >> 8; 1972 priv->vip_cntrl_2 = video; 1973 } 1974 1975 ret = tda998x_get_audio_ports(priv, np); 1976 if (ret) 1977 goto fail; 1978 1979 if (priv->audio_port_enable[AUDIO_ROUTE_I2S] || 1980 priv->audio_port_enable[AUDIO_ROUTE_SPDIF]) 1981 tda998x_audio_codec_init(priv, &client->dev); 1982 } else if (dev->platform_data) { 1983 ret = tda998x_set_config(priv, dev->platform_data); 1984 if (ret) 1985 goto fail; 1986 } 1987 1988 priv->bridge.funcs = &tda998x_bridge_funcs; 1989 #ifdef CONFIG_OF 1990 priv->bridge.of_node = dev->of_node; 1991 #endif 1992 1993 drm_bridge_add(&priv->bridge); 1994 1995 return 0; 1996 1997 fail: 1998 tda998x_destroy(dev); 1999 err_irq: 2000 return ret; 2001 } 2002 2003 /* DRM encoder functions */ 2004 2005 static int tda998x_encoder_init(struct device *dev, struct drm_device *drm) 2006 { 2007 struct tda998x_priv *priv = dev_get_drvdata(dev); 2008 u32 crtcs = 0; 2009 int ret; 2010 2011 if (dev->of_node) 2012 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); 2013 2014 /* If no CRTCs were found, fall back to our old behaviour */ 2015 if (crtcs == 0) { 2016 dev_warn(dev, "Falling back to first CRTC\n"); 2017 crtcs = 1 << 0; 2018 } 2019 2020 priv->encoder.possible_crtcs = crtcs; 2021 2022 ret = drm_simple_encoder_init(drm, &priv->encoder, 2023 DRM_MODE_ENCODER_TMDS); 2024 if (ret) 2025 goto err_encoder; 2026 2027 ret = drm_bridge_attach(&priv->encoder, &priv->bridge, NULL, 0); 2028 if (ret) 2029 goto err_bridge; 2030 2031 return 0; 2032 2033 err_bridge: 2034 drm_encoder_cleanup(&priv->encoder); 2035 err_encoder: 2036 return ret; 2037 } 2038 2039 static int tda998x_bind(struct device *dev, struct device *master, void *data) 2040 { 2041 struct drm_device *drm = data; 2042 2043 return tda998x_encoder_init(dev, drm); 2044 } 2045 2046 static void tda998x_unbind(struct device *dev, struct device *master, 2047 void *data) 2048 { 2049 struct tda998x_priv *priv = dev_get_drvdata(dev); 2050 2051 drm_encoder_cleanup(&priv->encoder); 2052 } 2053 2054 static const struct component_ops tda998x_ops = { 2055 .bind = tda998x_bind, 2056 .unbind = tda998x_unbind, 2057 }; 2058 2059 static int 2060 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) 2061 { 2062 int ret; 2063 2064 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 2065 dev_warn(&client->dev, "adapter does not support I2C\n"); 2066 return -EIO; 2067 } 2068 2069 ret = tda998x_create(&client->dev); 2070 if (ret) 2071 return ret; 2072 2073 ret = component_add(&client->dev, &tda998x_ops); 2074 if (ret) 2075 tda998x_destroy(&client->dev); 2076 return ret; 2077 } 2078 2079 static void tda998x_remove(struct i2c_client *client) 2080 { 2081 component_del(&client->dev, &tda998x_ops); 2082 tda998x_destroy(&client->dev); 2083 } 2084 2085 #ifdef CONFIG_OF 2086 static const struct of_device_id tda998x_dt_ids[] = { 2087 { .compatible = "nxp,tda998x", }, 2088 { } 2089 }; 2090 MODULE_DEVICE_TABLE(of, tda998x_dt_ids); 2091 #endif 2092 2093 static const struct i2c_device_id tda998x_ids[] = { 2094 { "tda998x", 0 }, 2095 { } 2096 }; 2097 MODULE_DEVICE_TABLE(i2c, tda998x_ids); 2098 2099 static struct i2c_driver tda998x_driver = { 2100 .probe = tda998x_probe, 2101 .remove = tda998x_remove, 2102 .driver = { 2103 .name = "tda998x", 2104 .of_match_table = of_match_ptr(tda998x_dt_ids), 2105 }, 2106 .id_table = tda998x_ids, 2107 }; 2108 2109 module_i2c_driver(tda998x_driver); 2110 2111 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 2112 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); 2113 MODULE_LICENSE("GPL"); 2114