1 /* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include <linux/component.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/hdmi.h> 21 #include <linux/module.h> 22 #include <linux/platform_data/tda9950.h> 23 #include <linux/irq.h> 24 #include <sound/asoundef.h> 25 #include <sound/hdmi-codec.h> 26 27 #include <drm/drmP.h> 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_crtc_helper.h> 30 #include <drm/drm_edid.h> 31 #include <drm/drm_of.h> 32 #include <drm/i2c/tda998x.h> 33 34 #include <media/cec-notifier.h> 35 36 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 37 38 struct tda998x_audio_port { 39 u8 format; /* AFMT_xxx */ 40 u8 config; /* AP value */ 41 }; 42 43 struct tda998x_priv { 44 struct i2c_client *cec; 45 struct i2c_client *hdmi; 46 struct mutex mutex; 47 u16 rev; 48 u8 cec_addr; 49 u8 current_page; 50 bool is_on; 51 bool supports_infoframes; 52 bool sink_has_audio; 53 u8 vip_cntrl_0; 54 u8 vip_cntrl_1; 55 u8 vip_cntrl_2; 56 unsigned long tmds_clock; 57 struct tda998x_audio_params audio_params; 58 59 struct platform_device *audio_pdev; 60 struct mutex audio_mutex; 61 62 struct mutex edid_mutex; 63 wait_queue_head_t wq_edid; 64 volatile int wq_edid_wait; 65 66 struct work_struct detect_work; 67 struct timer_list edid_delay_timer; 68 wait_queue_head_t edid_delay_waitq; 69 bool edid_delay_active; 70 71 struct drm_encoder encoder; 72 struct drm_connector connector; 73 74 struct tda998x_audio_port audio_port[2]; 75 struct tda9950_glue cec_glue; 76 struct gpio_desc *calib; 77 struct cec_notifier *cec_notify; 78 }; 79 80 #define conn_to_tda998x_priv(x) \ 81 container_of(x, struct tda998x_priv, connector) 82 83 #define enc_to_tda998x_priv(x) \ 84 container_of(x, struct tda998x_priv, encoder) 85 86 /* The TDA9988 series of devices use a paged register scheme.. to simplify 87 * things we encode the page # in upper bits of the register #. To read/ 88 * write a given register, we need to make sure CURPAGE register is set 89 * appropriately. Which implies reads/writes are not atomic. Fun! 90 */ 91 92 #define REG(page, addr) (((page) << 8) | (addr)) 93 #define REG2ADDR(reg) ((reg) & 0xff) 94 #define REG2PAGE(reg) (((reg) >> 8) & 0xff) 95 96 #define REG_CURPAGE 0xff /* write */ 97 98 99 /* Page 00h: General Control */ 100 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */ 101 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ 102 # define MAIN_CNTRL0_SR (1 << 0) 103 # define MAIN_CNTRL0_DECS (1 << 1) 104 # define MAIN_CNTRL0_DEHS (1 << 2) 105 # define MAIN_CNTRL0_CECS (1 << 3) 106 # define MAIN_CNTRL0_CEHS (1 << 4) 107 # define MAIN_CNTRL0_SCALER (1 << 7) 108 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */ 109 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ 110 # define SOFTRESET_AUDIO (1 << 0) 111 # define SOFTRESET_I2C_MASTER (1 << 1) 112 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ 113 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ 114 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ 115 # define I2C_MASTER_DIS_MM (1 << 0) 116 # define I2C_MASTER_DIS_FILT (1 << 1) 117 # define I2C_MASTER_APP_STRT_LAT (1 << 2) 118 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ 119 # define FEAT_POWERDOWN_PREFILT BIT(0) 120 # define FEAT_POWERDOWN_CSC BIT(1) 121 # define FEAT_POWERDOWN_SPDIF (1 << 3) 122 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ 123 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ 124 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ 125 # define INT_FLAGS_2_EDID_BLK_RD (1 << 1) 126 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ 127 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ 128 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ 129 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ 130 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ 131 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ 132 # define VIP_CNTRL_0_MIRR_A (1 << 7) 133 # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) 134 # define VIP_CNTRL_0_MIRR_B (1 << 3) 135 # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) 136 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ 137 # define VIP_CNTRL_1_MIRR_C (1 << 7) 138 # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) 139 # define VIP_CNTRL_1_MIRR_D (1 << 3) 140 # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) 141 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ 142 # define VIP_CNTRL_2_MIRR_E (1 << 7) 143 # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) 144 # define VIP_CNTRL_2_MIRR_F (1 << 3) 145 # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) 146 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ 147 # define VIP_CNTRL_3_X_TGL (1 << 0) 148 # define VIP_CNTRL_3_H_TGL (1 << 1) 149 # define VIP_CNTRL_3_V_TGL (1 << 2) 150 # define VIP_CNTRL_3_EMB (1 << 3) 151 # define VIP_CNTRL_3_SYNC_DE (1 << 4) 152 # define VIP_CNTRL_3_SYNC_HS (1 << 5) 153 # define VIP_CNTRL_3_DE_INT (1 << 6) 154 # define VIP_CNTRL_3_EDGE (1 << 7) 155 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ 156 # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) 157 # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) 158 # define VIP_CNTRL_4_CCIR656 (1 << 4) 159 # define VIP_CNTRL_4_656_ALT (1 << 5) 160 # define VIP_CNTRL_4_TST_656 (1 << 6) 161 # define VIP_CNTRL_4_TST_PAT (1 << 7) 162 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ 163 # define VIP_CNTRL_5_CKCASE (1 << 0) 164 # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) 165 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */ 166 # define MUX_AP_SELECT_I2S 0x64 167 # define MUX_AP_SELECT_SPDIF 0x40 168 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ 169 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ 170 # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) 171 # define MAT_CONTRL_MAT_BP (1 << 2) 172 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ 173 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ 174 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ 175 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ 176 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ 177 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ 178 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ 179 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ 180 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ 181 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ 182 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ 183 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ 184 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ 185 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ 186 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ 187 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ 188 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ 189 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ 190 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ 191 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ 192 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ 193 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ 194 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ 195 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ 196 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ 197 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ 198 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ 199 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ 200 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ 201 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ 202 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ 203 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ 204 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ 205 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ 206 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ 207 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ 208 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ 209 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ 210 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ 211 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ 212 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ 213 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ 214 # define TBG_CNTRL_0_TOP_TGL (1 << 0) 215 # define TBG_CNTRL_0_TOP_SEL (1 << 1) 216 # define TBG_CNTRL_0_DE_EXT (1 << 2) 217 # define TBG_CNTRL_0_TOP_EXT (1 << 3) 218 # define TBG_CNTRL_0_FRAME_DIS (1 << 5) 219 # define TBG_CNTRL_0_SYNC_MTHD (1 << 6) 220 # define TBG_CNTRL_0_SYNC_ONCE (1 << 7) 221 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ 222 # define TBG_CNTRL_1_H_TGL (1 << 0) 223 # define TBG_CNTRL_1_V_TGL (1 << 1) 224 # define TBG_CNTRL_1_TGL_EN (1 << 2) 225 # define TBG_CNTRL_1_X_EXT (1 << 3) 226 # define TBG_CNTRL_1_H_EXT (1 << 4) 227 # define TBG_CNTRL_1_V_EXT (1 << 5) 228 # define TBG_CNTRL_1_DWIN_DIS (1 << 6) 229 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ 230 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ 231 # define HVF_CNTRL_0_SM (1 << 7) 232 # define HVF_CNTRL_0_RWB (1 << 6) 233 # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) 234 # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) 235 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ 236 # define HVF_CNTRL_1_FOR (1 << 0) 237 # define HVF_CNTRL_1_YUVBLK (1 << 1) 238 # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) 239 # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) 240 # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) 241 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ 242 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ 243 # define I2S_FORMAT(x) (((x) & 3) << 0) 244 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ 245 # define AIP_CLKSEL_AIP_SPDIF (0 << 3) 246 # define AIP_CLKSEL_AIP_I2S (1 << 3) 247 # define AIP_CLKSEL_FS_ACLK (0 << 0) 248 # define AIP_CLKSEL_FS_MCLK (1 << 0) 249 # define AIP_CLKSEL_FS_FS64SPDIF (2 << 0) 250 251 /* Page 02h: PLL settings */ 252 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ 253 # define PLL_SERIAL_1_SRL_FDN (1 << 0) 254 # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) 255 # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) 256 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ 257 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0) 258 # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) 259 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ 260 # define PLL_SERIAL_3_SRL_CCIR (1 << 0) 261 # define PLL_SERIAL_3_SRL_DE (1 << 2) 262 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) 263 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ 264 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ 265 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ 266 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ 267 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ 268 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ 269 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ 270 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ 271 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ 272 # define AUDIO_DIV_SERCLK_1 0 273 # define AUDIO_DIV_SERCLK_2 1 274 # define AUDIO_DIV_SERCLK_4 2 275 # define AUDIO_DIV_SERCLK_8 3 276 # define AUDIO_DIV_SERCLK_16 4 277 # define AUDIO_DIV_SERCLK_32 5 278 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ 279 # define SEL_CLK_SEL_CLK1 (1 << 0) 280 # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) 281 # define SEL_CLK_ENA_SC_CLK (1 << 3) 282 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ 283 284 285 /* Page 09h: EDID Control */ 286 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ 287 /* next 127 successive registers are the EDID block */ 288 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ 289 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ 290 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ 291 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ 292 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ 293 294 295 /* Page 10h: information frames and packets */ 296 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ 297 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ 298 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ 299 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ 300 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ 301 302 303 /* Page 11h: audio settings and content info packets */ 304 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ 305 # define AIP_CNTRL_0_RST_FIFO (1 << 0) 306 # define AIP_CNTRL_0_SWAP (1 << 1) 307 # define AIP_CNTRL_0_LAYOUT (1 << 2) 308 # define AIP_CNTRL_0_ACR_MAN (1 << 5) 309 # define AIP_CNTRL_0_RST_CTS (1 << 6) 310 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */ 311 # define CA_I2S_CA_I2S(x) (((x) & 31) << 0) 312 # define CA_I2S_HBR_CHSTAT (1 << 6) 313 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ 314 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ 315 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ 316 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ 317 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ 318 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ 319 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ 320 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */ 321 # define CTS_N_K(x) (((x) & 7) << 0) 322 # define CTS_N_M(x) (((x) & 3) << 4) 323 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ 324 # define ENC_CNTRL_RST_ENC (1 << 0) 325 # define ENC_CNTRL_RST_SEL (1 << 1) 326 # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) 327 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ 328 # define DIP_FLAGS_ACR (1 << 0) 329 # define DIP_FLAGS_GC (1 << 1) 330 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ 331 # define DIP_IF_FLAGS_IF1 (1 << 1) 332 # define DIP_IF_FLAGS_IF2 (1 << 2) 333 # define DIP_IF_FLAGS_IF3 (1 << 3) 334 # define DIP_IF_FLAGS_IF4 (1 << 4) 335 # define DIP_IF_FLAGS_IF5 (1 << 5) 336 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ 337 338 339 /* Page 12h: HDCP and OTP */ 340 #define REG_TX3 REG(0x12, 0x9a) /* read/write */ 341 #define REG_TX4 REG(0x12, 0x9b) /* read/write */ 342 # define TX4_PD_RAM (1 << 1) 343 #define REG_TX33 REG(0x12, 0xb8) /* read/write */ 344 # define TX33_HDMI (1 << 1) 345 346 347 /* Page 13h: Gamut related metadata packets */ 348 349 350 351 /* CEC registers: (not paged) 352 */ 353 #define REG_CEC_INTSTATUS 0xee /* read */ 354 # define CEC_INTSTATUS_CEC (1 << 0) 355 # define CEC_INTSTATUS_HDMI (1 << 1) 356 #define REG_CEC_CAL_XOSC_CTRL1 0xf2 357 # define CEC_CAL_XOSC_CTRL1_ENA_CAL BIT(0) 358 #define REG_CEC_DES_FREQ2 0xf5 359 # define CEC_DES_FREQ2_DIS_AUTOCAL BIT(7) 360 #define REG_CEC_CLK 0xf6 361 # define CEC_CLK_FRO 0x11 362 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ 363 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) 364 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) 365 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) 366 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) 367 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */ 368 #define REG_CEC_RXSHPDINT 0xfd /* read */ 369 # define CEC_RXSHPDINT_RXSENS BIT(0) 370 # define CEC_RXSHPDINT_HPD BIT(1) 371 #define REG_CEC_RXSHPDLEV 0xfe /* read */ 372 # define CEC_RXSHPDLEV_RXSENS (1 << 0) 373 # define CEC_RXSHPDLEV_HPD (1 << 1) 374 375 #define REG_CEC_ENAMODS 0xff /* read/write */ 376 # define CEC_ENAMODS_EN_CEC_CLK (1 << 7) 377 # define CEC_ENAMODS_DIS_FRO (1 << 6) 378 # define CEC_ENAMODS_DIS_CCLK (1 << 5) 379 # define CEC_ENAMODS_EN_RXSENS (1 << 2) 380 # define CEC_ENAMODS_EN_HDMI (1 << 1) 381 # define CEC_ENAMODS_EN_CEC (1 << 0) 382 383 384 /* Device versions: */ 385 #define TDA9989N2 0x0101 386 #define TDA19989 0x0201 387 #define TDA19989N2 0x0202 388 #define TDA19988 0x0301 389 390 static void 391 cec_write(struct tda998x_priv *priv, u16 addr, u8 val) 392 { 393 u8 buf[] = {addr, val}; 394 struct i2c_msg msg = { 395 .addr = priv->cec_addr, 396 .len = 2, 397 .buf = buf, 398 }; 399 int ret; 400 401 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1); 402 if (ret < 0) 403 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n", 404 ret, addr); 405 } 406 407 static u8 408 cec_read(struct tda998x_priv *priv, u8 addr) 409 { 410 u8 val; 411 struct i2c_msg msg[2] = { 412 { 413 .addr = priv->cec_addr, 414 .len = 1, 415 .buf = &addr, 416 }, { 417 .addr = priv->cec_addr, 418 .flags = I2C_M_RD, 419 .len = 1, 420 .buf = &val, 421 }, 422 }; 423 int ret; 424 425 ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg)); 426 if (ret < 0) { 427 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n", 428 ret, addr); 429 val = 0; 430 } 431 432 return val; 433 } 434 435 static void cec_enamods(struct tda998x_priv *priv, u8 mods, bool enable) 436 { 437 int val = cec_read(priv, REG_CEC_ENAMODS); 438 439 if (val < 0) 440 return; 441 442 if (enable) 443 val |= mods; 444 else 445 val &= ~mods; 446 447 cec_write(priv, REG_CEC_ENAMODS, val); 448 } 449 450 static void tda998x_cec_set_calibration(struct tda998x_priv *priv, bool enable) 451 { 452 if (enable) { 453 u8 val; 454 455 cec_write(priv, 0xf3, 0xc0); 456 cec_write(priv, 0xf4, 0xd4); 457 458 /* Enable automatic calibration mode */ 459 val = cec_read(priv, REG_CEC_DES_FREQ2); 460 val &= ~CEC_DES_FREQ2_DIS_AUTOCAL; 461 cec_write(priv, REG_CEC_DES_FREQ2, val); 462 463 /* Enable free running oscillator */ 464 cec_write(priv, REG_CEC_CLK, CEC_CLK_FRO); 465 cec_enamods(priv, CEC_ENAMODS_DIS_FRO, false); 466 467 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 468 CEC_CAL_XOSC_CTRL1_ENA_CAL); 469 } else { 470 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 0); 471 } 472 } 473 474 /* 475 * Calibration for the internal oscillator: we need to set calibration mode, 476 * and then pulse the IRQ line low for a 10ms ± 1% period. 477 */ 478 static void tda998x_cec_calibration(struct tda998x_priv *priv) 479 { 480 struct gpio_desc *calib = priv->calib; 481 482 mutex_lock(&priv->edid_mutex); 483 if (priv->hdmi->irq > 0) 484 disable_irq(priv->hdmi->irq); 485 gpiod_direction_output(calib, 1); 486 tda998x_cec_set_calibration(priv, true); 487 488 local_irq_disable(); 489 gpiod_set_value(calib, 0); 490 mdelay(10); 491 gpiod_set_value(calib, 1); 492 local_irq_enable(); 493 494 tda998x_cec_set_calibration(priv, false); 495 gpiod_direction_input(calib); 496 if (priv->hdmi->irq > 0) 497 enable_irq(priv->hdmi->irq); 498 mutex_unlock(&priv->edid_mutex); 499 } 500 501 static int tda998x_cec_hook_init(void *data) 502 { 503 struct tda998x_priv *priv = data; 504 struct gpio_desc *calib; 505 506 calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS); 507 if (IS_ERR(calib)) { 508 dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n", 509 PTR_ERR(calib)); 510 return PTR_ERR(calib); 511 } 512 513 priv->calib = calib; 514 515 return 0; 516 } 517 518 static void tda998x_cec_hook_exit(void *data) 519 { 520 struct tda998x_priv *priv = data; 521 522 gpiod_put(priv->calib); 523 priv->calib = NULL; 524 } 525 526 static int tda998x_cec_hook_open(void *data) 527 { 528 struct tda998x_priv *priv = data; 529 530 cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, true); 531 tda998x_cec_calibration(priv); 532 533 return 0; 534 } 535 536 static void tda998x_cec_hook_release(void *data) 537 { 538 struct tda998x_priv *priv = data; 539 540 cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, false); 541 } 542 543 static int 544 set_page(struct tda998x_priv *priv, u16 reg) 545 { 546 if (REG2PAGE(reg) != priv->current_page) { 547 struct i2c_client *client = priv->hdmi; 548 u8 buf[] = { 549 REG_CURPAGE, REG2PAGE(reg) 550 }; 551 int ret = i2c_master_send(client, buf, sizeof(buf)); 552 if (ret < 0) { 553 dev_err(&client->dev, "%s %04x err %d\n", __func__, 554 reg, ret); 555 return ret; 556 } 557 558 priv->current_page = REG2PAGE(reg); 559 } 560 return 0; 561 } 562 563 static int 564 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt) 565 { 566 struct i2c_client *client = priv->hdmi; 567 u8 addr = REG2ADDR(reg); 568 int ret; 569 570 mutex_lock(&priv->mutex); 571 ret = set_page(priv, reg); 572 if (ret < 0) 573 goto out; 574 575 ret = i2c_master_send(client, &addr, sizeof(addr)); 576 if (ret < 0) 577 goto fail; 578 579 ret = i2c_master_recv(client, buf, cnt); 580 if (ret < 0) 581 goto fail; 582 583 goto out; 584 585 fail: 586 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); 587 out: 588 mutex_unlock(&priv->mutex); 589 return ret; 590 } 591 592 static void 593 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt) 594 { 595 struct i2c_client *client = priv->hdmi; 596 u8 buf[cnt+1]; 597 int ret; 598 599 buf[0] = REG2ADDR(reg); 600 memcpy(&buf[1], p, cnt); 601 602 mutex_lock(&priv->mutex); 603 ret = set_page(priv, reg); 604 if (ret < 0) 605 goto out; 606 607 ret = i2c_master_send(client, buf, cnt + 1); 608 if (ret < 0) 609 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 610 out: 611 mutex_unlock(&priv->mutex); 612 } 613 614 static int 615 reg_read(struct tda998x_priv *priv, u16 reg) 616 { 617 u8 val = 0; 618 int ret; 619 620 ret = reg_read_range(priv, reg, &val, sizeof(val)); 621 if (ret < 0) 622 return ret; 623 return val; 624 } 625 626 static void 627 reg_write(struct tda998x_priv *priv, u16 reg, u8 val) 628 { 629 struct i2c_client *client = priv->hdmi; 630 u8 buf[] = {REG2ADDR(reg), val}; 631 int ret; 632 633 mutex_lock(&priv->mutex); 634 ret = set_page(priv, reg); 635 if (ret < 0) 636 goto out; 637 638 ret = i2c_master_send(client, buf, sizeof(buf)); 639 if (ret < 0) 640 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 641 out: 642 mutex_unlock(&priv->mutex); 643 } 644 645 static void 646 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val) 647 { 648 struct i2c_client *client = priv->hdmi; 649 u8 buf[] = {REG2ADDR(reg), val >> 8, val}; 650 int ret; 651 652 mutex_lock(&priv->mutex); 653 ret = set_page(priv, reg); 654 if (ret < 0) 655 goto out; 656 657 ret = i2c_master_send(client, buf, sizeof(buf)); 658 if (ret < 0) 659 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 660 out: 661 mutex_unlock(&priv->mutex); 662 } 663 664 static void 665 reg_set(struct tda998x_priv *priv, u16 reg, u8 val) 666 { 667 int old_val; 668 669 old_val = reg_read(priv, reg); 670 if (old_val >= 0) 671 reg_write(priv, reg, old_val | val); 672 } 673 674 static void 675 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val) 676 { 677 int old_val; 678 679 old_val = reg_read(priv, reg); 680 if (old_val >= 0) 681 reg_write(priv, reg, old_val & ~val); 682 } 683 684 static void 685 tda998x_reset(struct tda998x_priv *priv) 686 { 687 /* reset audio and i2c master: */ 688 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 689 msleep(50); 690 reg_write(priv, REG_SOFTRESET, 0); 691 msleep(50); 692 693 /* reset transmitter: */ 694 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 695 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 696 697 /* PLL registers common configuration */ 698 reg_write(priv, REG_PLL_SERIAL_1, 0x00); 699 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); 700 reg_write(priv, REG_PLL_SERIAL_3, 0x00); 701 reg_write(priv, REG_SERIALIZER, 0x00); 702 reg_write(priv, REG_BUFFER_OUT, 0x00); 703 reg_write(priv, REG_PLL_SCG1, 0x00); 704 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); 705 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 706 reg_write(priv, REG_PLL_SCGN1, 0xfa); 707 reg_write(priv, REG_PLL_SCGN2, 0x00); 708 reg_write(priv, REG_PLL_SCGR1, 0x5b); 709 reg_write(priv, REG_PLL_SCGR2, 0x00); 710 reg_write(priv, REG_PLL_SCG2, 0x10); 711 712 /* Write the default value MUX register */ 713 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24); 714 } 715 716 /* 717 * The TDA998x has a problem when trying to read the EDID close to a 718 * HPD assertion: it needs a delay of 100ms to avoid timing out while 719 * trying to read EDID data. 720 * 721 * However, tda998x_connector_get_modes() may be called at any moment 722 * after tda998x_connector_detect() indicates that we are connected, so 723 * we need to delay probing modes in tda998x_connector_get_modes() after 724 * we have seen a HPD inactive->active transition. This code implements 725 * that delay. 726 */ 727 static void tda998x_edid_delay_done(struct timer_list *t) 728 { 729 struct tda998x_priv *priv = from_timer(priv, t, edid_delay_timer); 730 731 priv->edid_delay_active = false; 732 wake_up(&priv->edid_delay_waitq); 733 schedule_work(&priv->detect_work); 734 } 735 736 static void tda998x_edid_delay_start(struct tda998x_priv *priv) 737 { 738 priv->edid_delay_active = true; 739 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10); 740 } 741 742 static int tda998x_edid_delay_wait(struct tda998x_priv *priv) 743 { 744 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active); 745 } 746 747 /* 748 * We need to run the KMS hotplug event helper outside of our threaded 749 * interrupt routine as this can call back into our get_modes method, 750 * which will want to make use of interrupts. 751 */ 752 static void tda998x_detect_work(struct work_struct *work) 753 { 754 struct tda998x_priv *priv = 755 container_of(work, struct tda998x_priv, detect_work); 756 struct drm_device *dev = priv->encoder.dev; 757 758 if (dev) 759 drm_kms_helper_hotplug_event(dev); 760 } 761 762 /* 763 * only 2 interrupts may occur: screen plug/unplug and EDID read 764 */ 765 static irqreturn_t tda998x_irq_thread(int irq, void *data) 766 { 767 struct tda998x_priv *priv = data; 768 u8 sta, cec, lvl, flag0, flag1, flag2; 769 bool handled = false; 770 771 sta = cec_read(priv, REG_CEC_INTSTATUS); 772 if (sta & CEC_INTSTATUS_HDMI) { 773 cec = cec_read(priv, REG_CEC_RXSHPDINT); 774 lvl = cec_read(priv, REG_CEC_RXSHPDLEV); 775 flag0 = reg_read(priv, REG_INT_FLAGS_0); 776 flag1 = reg_read(priv, REG_INT_FLAGS_1); 777 flag2 = reg_read(priv, REG_INT_FLAGS_2); 778 DRM_DEBUG_DRIVER( 779 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n", 780 sta, cec, lvl, flag0, flag1, flag2); 781 782 if (cec & CEC_RXSHPDINT_HPD) { 783 if (lvl & CEC_RXSHPDLEV_HPD) { 784 tda998x_edid_delay_start(priv); 785 } else { 786 schedule_work(&priv->detect_work); 787 cec_notifier_set_phys_addr(priv->cec_notify, 788 CEC_PHYS_ADDR_INVALID); 789 } 790 791 handled = true; 792 } 793 794 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) { 795 priv->wq_edid_wait = 0; 796 wake_up(&priv->wq_edid); 797 handled = true; 798 } 799 } 800 801 return IRQ_RETVAL(handled); 802 } 803 804 static void 805 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr, 806 union hdmi_infoframe *frame) 807 { 808 u8 buf[32]; 809 ssize_t len; 810 811 len = hdmi_infoframe_pack(frame, buf, sizeof(buf)); 812 if (len < 0) { 813 dev_err(&priv->hdmi->dev, 814 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n", 815 frame->any.type, len); 816 return; 817 } 818 819 reg_clear(priv, REG_DIP_IF_FLAGS, bit); 820 reg_write_range(priv, addr, buf, len); 821 reg_set(priv, REG_DIP_IF_FLAGS, bit); 822 } 823 824 static int tda998x_write_aif(struct tda998x_priv *priv, 825 struct hdmi_audio_infoframe *cea) 826 { 827 union hdmi_infoframe frame; 828 829 frame.audio = *cea; 830 831 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame); 832 833 return 0; 834 } 835 836 static void 837 tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode) 838 { 839 union hdmi_infoframe frame; 840 841 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false); 842 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL; 843 844 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame); 845 } 846 847 /* Audio support */ 848 849 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on) 850 { 851 if (on) { 852 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO); 853 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO); 854 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 855 } else { 856 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 857 } 858 } 859 860 static int 861 tda998x_configure_audio(struct tda998x_priv *priv, 862 struct tda998x_audio_params *params) 863 { 864 u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv; 865 u32 n; 866 867 /* Enable audio ports */ 868 reg_write(priv, REG_ENA_AP, params->config); 869 870 /* Set audio input source */ 871 switch (params->format) { 872 case AFMT_SPDIF: 873 reg_write(priv, REG_ENA_ACLK, 0); 874 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF); 875 clksel_aip = AIP_CLKSEL_AIP_SPDIF; 876 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF; 877 cts_n = CTS_N_M(3) | CTS_N_K(3); 878 break; 879 880 case AFMT_I2S: 881 reg_write(priv, REG_ENA_ACLK, 1); 882 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S); 883 clksel_aip = AIP_CLKSEL_AIP_I2S; 884 clksel_fs = AIP_CLKSEL_FS_ACLK; 885 switch (params->sample_width) { 886 case 16: 887 cts_n = CTS_N_M(3) | CTS_N_K(1); 888 break; 889 case 18: 890 case 20: 891 case 24: 892 cts_n = CTS_N_M(3) | CTS_N_K(2); 893 break; 894 default: 895 case 32: 896 cts_n = CTS_N_M(3) | CTS_N_K(3); 897 break; 898 } 899 break; 900 901 default: 902 dev_err(&priv->hdmi->dev, "Unsupported I2S format\n"); 903 return -EINVAL; 904 } 905 906 reg_write(priv, REG_AIP_CLKSEL, clksel_aip); 907 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT | 908 AIP_CNTRL_0_ACR_MAN); /* auto CTS */ 909 reg_write(priv, REG_CTS_N, cts_n); 910 911 /* 912 * Audio input somehow depends on HDMI line rate which is 913 * related to pixclk. Testing showed that modes with pixclk 914 * >100MHz need a larger divider while <40MHz need the default. 915 * There is no detailed info in the datasheet, so we just 916 * assume 100MHz requires larger divider. 917 */ 918 adiv = AUDIO_DIV_SERCLK_8; 919 if (priv->tmds_clock > 100000) 920 adiv++; /* AUDIO_DIV_SERCLK_16 */ 921 922 /* S/PDIF asks for a larger divider */ 923 if (params->format == AFMT_SPDIF) 924 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */ 925 926 reg_write(priv, REG_AUDIO_DIV, adiv); 927 928 /* 929 * This is the approximate value of N, which happens to be 930 * the recommended values for non-coherent clocks. 931 */ 932 n = 128 * params->sample_rate / 1000; 933 934 /* Write the CTS and N values */ 935 buf[0] = 0x44; 936 buf[1] = 0x42; 937 buf[2] = 0x01; 938 buf[3] = n; 939 buf[4] = n >> 8; 940 buf[5] = n >> 16; 941 reg_write_range(priv, REG_ACR_CTS_0, buf, 6); 942 943 /* Set CTS clock reference */ 944 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs); 945 946 /* Reset CTS generator */ 947 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 948 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 949 950 /* Write the channel status 951 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because 952 * there is a separate register for each I2S wire. 953 */ 954 buf[0] = params->status[0]; 955 buf[1] = params->status[1]; 956 buf[2] = params->status[3]; 957 buf[3] = params->status[4]; 958 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4); 959 960 tda998x_audio_mute(priv, true); 961 msleep(20); 962 tda998x_audio_mute(priv, false); 963 964 return tda998x_write_aif(priv, ¶ms->cea); 965 } 966 967 static int tda998x_audio_hw_params(struct device *dev, void *data, 968 struct hdmi_codec_daifmt *daifmt, 969 struct hdmi_codec_params *params) 970 { 971 struct tda998x_priv *priv = dev_get_drvdata(dev); 972 int i, ret; 973 struct tda998x_audio_params audio = { 974 .sample_width = params->sample_width, 975 .sample_rate = params->sample_rate, 976 .cea = params->cea, 977 }; 978 979 memcpy(audio.status, params->iec.status, 980 min(sizeof(audio.status), sizeof(params->iec.status))); 981 982 switch (daifmt->fmt) { 983 case HDMI_I2S: 984 if (daifmt->bit_clk_inv || daifmt->frame_clk_inv || 985 daifmt->bit_clk_master || daifmt->frame_clk_master) { 986 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__, 987 daifmt->bit_clk_inv, daifmt->frame_clk_inv, 988 daifmt->bit_clk_master, 989 daifmt->frame_clk_master); 990 return -EINVAL; 991 } 992 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) 993 if (priv->audio_port[i].format == AFMT_I2S) 994 audio.config = priv->audio_port[i].config; 995 audio.format = AFMT_I2S; 996 break; 997 case HDMI_SPDIF: 998 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) 999 if (priv->audio_port[i].format == AFMT_SPDIF) 1000 audio.config = priv->audio_port[i].config; 1001 audio.format = AFMT_SPDIF; 1002 break; 1003 default: 1004 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt); 1005 return -EINVAL; 1006 } 1007 1008 if (audio.config == 0) { 1009 dev_err(dev, "%s: No audio configuration found\n", __func__); 1010 return -EINVAL; 1011 } 1012 1013 mutex_lock(&priv->audio_mutex); 1014 if (priv->supports_infoframes && priv->sink_has_audio) 1015 ret = tda998x_configure_audio(priv, &audio); 1016 else 1017 ret = 0; 1018 1019 if (ret == 0) 1020 priv->audio_params = audio; 1021 mutex_unlock(&priv->audio_mutex); 1022 1023 return ret; 1024 } 1025 1026 static void tda998x_audio_shutdown(struct device *dev, void *data) 1027 { 1028 struct tda998x_priv *priv = dev_get_drvdata(dev); 1029 1030 mutex_lock(&priv->audio_mutex); 1031 1032 reg_write(priv, REG_ENA_AP, 0); 1033 1034 priv->audio_params.format = AFMT_UNUSED; 1035 1036 mutex_unlock(&priv->audio_mutex); 1037 } 1038 1039 int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable) 1040 { 1041 struct tda998x_priv *priv = dev_get_drvdata(dev); 1042 1043 mutex_lock(&priv->audio_mutex); 1044 1045 tda998x_audio_mute(priv, enable); 1046 1047 mutex_unlock(&priv->audio_mutex); 1048 return 0; 1049 } 1050 1051 static int tda998x_audio_get_eld(struct device *dev, void *data, 1052 uint8_t *buf, size_t len) 1053 { 1054 struct tda998x_priv *priv = dev_get_drvdata(dev); 1055 1056 mutex_lock(&priv->audio_mutex); 1057 memcpy(buf, priv->connector.eld, 1058 min(sizeof(priv->connector.eld), len)); 1059 mutex_unlock(&priv->audio_mutex); 1060 1061 return 0; 1062 } 1063 1064 static const struct hdmi_codec_ops audio_codec_ops = { 1065 .hw_params = tda998x_audio_hw_params, 1066 .audio_shutdown = tda998x_audio_shutdown, 1067 .digital_mute = tda998x_audio_digital_mute, 1068 .get_eld = tda998x_audio_get_eld, 1069 }; 1070 1071 static int tda998x_audio_codec_init(struct tda998x_priv *priv, 1072 struct device *dev) 1073 { 1074 struct hdmi_codec_pdata codec_data = { 1075 .ops = &audio_codec_ops, 1076 .max_i2s_channels = 2, 1077 }; 1078 int i; 1079 1080 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) { 1081 if (priv->audio_port[i].format == AFMT_I2S && 1082 priv->audio_port[i].config != 0) 1083 codec_data.i2s = 1; 1084 if (priv->audio_port[i].format == AFMT_SPDIF && 1085 priv->audio_port[i].config != 0) 1086 codec_data.spdif = 1; 1087 } 1088 1089 priv->audio_pdev = platform_device_register_data( 1090 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, 1091 &codec_data, sizeof(codec_data)); 1092 1093 return PTR_ERR_OR_ZERO(priv->audio_pdev); 1094 } 1095 1096 /* DRM connector functions */ 1097 1098 static int tda998x_connector_fill_modes(struct drm_connector *connector, 1099 uint32_t maxX, uint32_t maxY) 1100 { 1101 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1102 int ret; 1103 1104 mutex_lock(&priv->audio_mutex); 1105 ret = drm_helper_probe_single_connector_modes(connector, maxX, maxY); 1106 1107 if (connector->edid_blob_ptr) { 1108 struct edid *edid = (void *)connector->edid_blob_ptr->data; 1109 1110 cec_notifier_set_phys_addr_from_edid(priv->cec_notify, edid); 1111 1112 priv->sink_has_audio = drm_detect_monitor_audio(edid); 1113 } else { 1114 priv->sink_has_audio = false; 1115 } 1116 mutex_unlock(&priv->audio_mutex); 1117 1118 return ret; 1119 } 1120 1121 static enum drm_connector_status 1122 tda998x_connector_detect(struct drm_connector *connector, bool force) 1123 { 1124 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1125 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV); 1126 1127 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : 1128 connector_status_disconnected; 1129 } 1130 1131 static void tda998x_connector_destroy(struct drm_connector *connector) 1132 { 1133 drm_connector_cleanup(connector); 1134 } 1135 1136 static const struct drm_connector_funcs tda998x_connector_funcs = { 1137 .dpms = drm_helper_connector_dpms, 1138 .reset = drm_atomic_helper_connector_reset, 1139 .fill_modes = tda998x_connector_fill_modes, 1140 .detect = tda998x_connector_detect, 1141 .destroy = tda998x_connector_destroy, 1142 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1143 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1144 }; 1145 1146 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length) 1147 { 1148 struct tda998x_priv *priv = data; 1149 u8 offset, segptr; 1150 int ret, i; 1151 1152 offset = (blk & 1) ? 128 : 0; 1153 segptr = blk / 2; 1154 1155 mutex_lock(&priv->edid_mutex); 1156 1157 reg_write(priv, REG_DDC_ADDR, 0xa0); 1158 reg_write(priv, REG_DDC_OFFS, offset); 1159 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60); 1160 reg_write(priv, REG_DDC_SEGM, segptr); 1161 1162 /* enable reading EDID: */ 1163 priv->wq_edid_wait = 1; 1164 reg_write(priv, REG_EDID_CTRL, 0x1); 1165 1166 /* flag must be cleared by sw: */ 1167 reg_write(priv, REG_EDID_CTRL, 0x0); 1168 1169 /* wait for block read to complete: */ 1170 if (priv->hdmi->irq) { 1171 i = wait_event_timeout(priv->wq_edid, 1172 !priv->wq_edid_wait, 1173 msecs_to_jiffies(100)); 1174 if (i < 0) { 1175 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i); 1176 ret = i; 1177 goto failed; 1178 } 1179 } else { 1180 for (i = 100; i > 0; i--) { 1181 msleep(1); 1182 ret = reg_read(priv, REG_INT_FLAGS_2); 1183 if (ret < 0) 1184 goto failed; 1185 if (ret & INT_FLAGS_2_EDID_BLK_RD) 1186 break; 1187 } 1188 } 1189 1190 if (i == 0) { 1191 dev_err(&priv->hdmi->dev, "read edid timeout\n"); 1192 ret = -ETIMEDOUT; 1193 goto failed; 1194 } 1195 1196 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length); 1197 if (ret != length) { 1198 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n", 1199 blk, ret); 1200 goto failed; 1201 } 1202 1203 ret = 0; 1204 1205 failed: 1206 mutex_unlock(&priv->edid_mutex); 1207 return ret; 1208 } 1209 1210 static int tda998x_connector_get_modes(struct drm_connector *connector) 1211 { 1212 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1213 struct edid *edid; 1214 int n; 1215 1216 /* 1217 * If we get killed while waiting for the HPD timeout, return 1218 * no modes found: we are not in a restartable path, so we 1219 * can't handle signals gracefully. 1220 */ 1221 if (tda998x_edid_delay_wait(priv)) 1222 return 0; 1223 1224 if (priv->rev == TDA19988) 1225 reg_clear(priv, REG_TX4, TX4_PD_RAM); 1226 1227 edid = drm_do_get_edid(connector, read_edid_block, priv); 1228 1229 if (priv->rev == TDA19988) 1230 reg_set(priv, REG_TX4, TX4_PD_RAM); 1231 1232 if (!edid) { 1233 dev_warn(&priv->hdmi->dev, "failed to read EDID\n"); 1234 return 0; 1235 } 1236 1237 drm_mode_connector_update_edid_property(connector, edid); 1238 n = drm_add_edid_modes(connector, edid); 1239 1240 kfree(edid); 1241 1242 return n; 1243 } 1244 1245 static enum drm_mode_status tda998x_connector_mode_valid(struct drm_connector *connector, 1246 struct drm_display_mode *mode) 1247 { 1248 /* TDA19988 dotclock can go up to 165MHz */ 1249 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1250 1251 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000)) 1252 return MODE_CLOCK_HIGH; 1253 if (mode->htotal >= BIT(13)) 1254 return MODE_BAD_HVALUE; 1255 if (mode->vtotal >= BIT(11)) 1256 return MODE_BAD_VVALUE; 1257 return MODE_OK; 1258 } 1259 1260 static struct drm_encoder * 1261 tda998x_connector_best_encoder(struct drm_connector *connector) 1262 { 1263 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1264 1265 return &priv->encoder; 1266 } 1267 1268 static 1269 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = { 1270 .get_modes = tda998x_connector_get_modes, 1271 .mode_valid = tda998x_connector_mode_valid, 1272 .best_encoder = tda998x_connector_best_encoder, 1273 }; 1274 1275 static int tda998x_connector_init(struct tda998x_priv *priv, 1276 struct drm_device *drm) 1277 { 1278 struct drm_connector *connector = &priv->connector; 1279 int ret; 1280 1281 connector->interlace_allowed = 1; 1282 1283 if (priv->hdmi->irq) 1284 connector->polled = DRM_CONNECTOR_POLL_HPD; 1285 else 1286 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1287 DRM_CONNECTOR_POLL_DISCONNECT; 1288 1289 drm_connector_helper_add(connector, &tda998x_connector_helper_funcs); 1290 ret = drm_connector_init(drm, connector, &tda998x_connector_funcs, 1291 DRM_MODE_CONNECTOR_HDMIA); 1292 if (ret) 1293 return ret; 1294 1295 drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder); 1296 1297 return 0; 1298 } 1299 1300 /* DRM encoder functions */ 1301 1302 static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode) 1303 { 1304 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder); 1305 bool on; 1306 1307 /* we only care about on or off: */ 1308 on = mode == DRM_MODE_DPMS_ON; 1309 1310 if (on == priv->is_on) 1311 return; 1312 1313 if (on) { 1314 /* enable video ports, audio will be enabled later */ 1315 reg_write(priv, REG_ENA_VP_0, 0xff); 1316 reg_write(priv, REG_ENA_VP_1, 0xff); 1317 reg_write(priv, REG_ENA_VP_2, 0xff); 1318 /* set muxing after enabling ports: */ 1319 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0); 1320 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1); 1321 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2); 1322 1323 priv->is_on = true; 1324 } else { 1325 /* disable video ports */ 1326 reg_write(priv, REG_ENA_VP_0, 0x00); 1327 reg_write(priv, REG_ENA_VP_1, 0x00); 1328 reg_write(priv, REG_ENA_VP_2, 0x00); 1329 1330 priv->is_on = false; 1331 } 1332 } 1333 1334 static void 1335 tda998x_encoder_mode_set(struct drm_encoder *encoder, 1336 struct drm_display_mode *mode, 1337 struct drm_display_mode *adjusted_mode) 1338 { 1339 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder); 1340 u16 ref_pix, ref_line, n_pix, n_line; 1341 u16 hs_pix_s, hs_pix_e; 1342 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e; 1343 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e; 1344 u16 vwin1_line_s, vwin1_line_e; 1345 u16 vwin2_line_s, vwin2_line_e; 1346 u16 de_pix_s, de_pix_e; 1347 u8 reg, div, rep; 1348 1349 /* 1350 * Internally TDA998x is using ITU-R BT.656 style sync but 1351 * we get VESA style sync. TDA998x is using a reference pixel 1352 * relative to ITU to sync to the input frame and for output 1353 * sync generation. Currently, we are using reference detection 1354 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point 1355 * which is position of rising VS with coincident rising HS. 1356 * 1357 * Now there is some issues to take care of: 1358 * - HDMI data islands require sync-before-active 1359 * - TDA998x register values must be > 0 to be enabled 1360 * - REFLINE needs an additional offset of +1 1361 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB 1362 * 1363 * So we add +1 to all horizontal and vertical register values, 1364 * plus an additional +3 for REFPIX as we are using RGB input only. 1365 */ 1366 n_pix = mode->htotal; 1367 n_line = mode->vtotal; 1368 1369 hs_pix_e = mode->hsync_end - mode->hdisplay; 1370 hs_pix_s = mode->hsync_start - mode->hdisplay; 1371 de_pix_e = mode->htotal; 1372 de_pix_s = mode->htotal - mode->hdisplay; 1373 ref_pix = 3 + hs_pix_s; 1374 1375 /* 1376 * Attached LCD controllers may generate broken sync. Allow 1377 * those to adjust the position of the rising VS edge by adding 1378 * HSKEW to ref_pix. 1379 */ 1380 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) 1381 ref_pix += adjusted_mode->hskew; 1382 1383 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { 1384 ref_line = 1 + mode->vsync_start - mode->vdisplay; 1385 vwin1_line_s = mode->vtotal - mode->vdisplay - 1; 1386 vwin1_line_e = vwin1_line_s + mode->vdisplay; 1387 vs1_pix_s = vs1_pix_e = hs_pix_s; 1388 vs1_line_s = mode->vsync_start - mode->vdisplay; 1389 vs1_line_e = vs1_line_s + 1390 mode->vsync_end - mode->vsync_start; 1391 vwin2_line_s = vwin2_line_e = 0; 1392 vs2_pix_s = vs2_pix_e = 0; 1393 vs2_line_s = vs2_line_e = 0; 1394 } else { 1395 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; 1396 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; 1397 vwin1_line_e = vwin1_line_s + mode->vdisplay/2; 1398 vs1_pix_s = vs1_pix_e = hs_pix_s; 1399 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; 1400 vs1_line_e = vs1_line_s + 1401 (mode->vsync_end - mode->vsync_start)/2; 1402 vwin2_line_s = vwin1_line_s + mode->vtotal/2; 1403 vwin2_line_e = vwin2_line_s + mode->vdisplay/2; 1404 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; 1405 vs2_line_s = vs1_line_s + mode->vtotal/2 ; 1406 vs2_line_e = vs2_line_s + 1407 (mode->vsync_end - mode->vsync_start)/2; 1408 } 1409 1410 div = 148500 / mode->clock; 1411 if (div != 0) { 1412 div--; 1413 if (div > 3) 1414 div = 3; 1415 } 1416 1417 mutex_lock(&priv->audio_mutex); 1418 1419 /* mute the audio FIFO: */ 1420 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 1421 1422 /* set HDMI HDCP mode off: */ 1423 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 1424 reg_clear(priv, REG_TX33, TX33_HDMI); 1425 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); 1426 1427 /* no pre-filter or interpolator: */ 1428 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | 1429 HVF_CNTRL_0_INTPOL(0)); 1430 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT); 1431 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); 1432 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | 1433 VIP_CNTRL_4_BLC(0)); 1434 1435 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); 1436 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR | 1437 PLL_SERIAL_3_SRL_DE); 1438 reg_write(priv, REG_SERIALIZER, 0); 1439 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); 1440 1441 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */ 1442 rep = 0; 1443 reg_write(priv, REG_RPT_CNTRL, 0); 1444 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | 1445 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 1446 1447 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | 1448 PLL_SERIAL_2_SRL_PR(rep)); 1449 1450 /* set color matrix bypass flag: */ 1451 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP | 1452 MAT_CONTRL_MAT_SC(1)); 1453 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC); 1454 1455 /* set BIAS tmds value: */ 1456 reg_write(priv, REG_ANA_GENERAL, 0x09); 1457 1458 /* 1459 * Sync on rising HSYNC/VSYNC 1460 */ 1461 reg = VIP_CNTRL_3_SYNC_HS; 1462 1463 /* 1464 * TDA19988 requires high-active sync at input stage, 1465 * so invert low-active sync provided by master encoder here 1466 */ 1467 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1468 reg |= VIP_CNTRL_3_H_TGL; 1469 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1470 reg |= VIP_CNTRL_3_V_TGL; 1471 reg_write(priv, REG_VIP_CNTRL_3, reg); 1472 1473 reg_write(priv, REG_VIDFORMAT, 0x00); 1474 reg_write16(priv, REG_REFPIX_MSB, ref_pix); 1475 reg_write16(priv, REG_REFLINE_MSB, ref_line); 1476 reg_write16(priv, REG_NPIX_MSB, n_pix); 1477 reg_write16(priv, REG_NLINE_MSB, n_line); 1478 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s); 1479 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s); 1480 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e); 1481 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e); 1482 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s); 1483 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s); 1484 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e); 1485 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e); 1486 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s); 1487 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e); 1488 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s); 1489 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e); 1490 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s); 1491 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e); 1492 reg_write16(priv, REG_DE_START_MSB, de_pix_s); 1493 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e); 1494 1495 if (priv->rev == TDA19988) { 1496 /* let incoming pixels fill the active space (if any) */ 1497 reg_write(priv, REG_ENABLE_SPACE, 0x00); 1498 } 1499 1500 /* 1501 * Always generate sync polarity relative to input sync and 1502 * revert input stage toggled sync at output stage 1503 */ 1504 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN; 1505 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1506 reg |= TBG_CNTRL_1_H_TGL; 1507 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1508 reg |= TBG_CNTRL_1_V_TGL; 1509 reg_write(priv, REG_TBG_CNTRL_1, reg); 1510 1511 /* must be last register set: */ 1512 reg_write(priv, REG_TBG_CNTRL_0, 0); 1513 1514 priv->tmds_clock = adjusted_mode->clock; 1515 1516 /* CEA-861B section 6 says that: 1517 * CEA version 1 (CEA-861) has no support for infoframes. 1518 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes, 1519 * and optional basic audio. 1520 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes, 1521 * and optional digital audio, with audio infoframes. 1522 * 1523 * Since we only support generation of version 2 AVI infoframes, 1524 * ignore CEA version 2 and below (iow, behave as if we're a 1525 * CEA-861 source.) 1526 */ 1527 priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3; 1528 1529 if (priv->supports_infoframes) { 1530 /* We need to turn HDMI HDCP stuff on to get audio through */ 1531 reg &= ~TBG_CNTRL_1_DWIN_DIS; 1532 reg_write(priv, REG_TBG_CNTRL_1, reg); 1533 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); 1534 reg_set(priv, REG_TX33, TX33_HDMI); 1535 1536 tda998x_write_avi(priv, adjusted_mode); 1537 1538 if (priv->audio_params.format != AFMT_UNUSED && 1539 priv->sink_has_audio) 1540 tda998x_configure_audio(priv, &priv->audio_params); 1541 } 1542 1543 mutex_unlock(&priv->audio_mutex); 1544 } 1545 1546 static void tda998x_destroy(struct tda998x_priv *priv) 1547 { 1548 /* disable all IRQs and free the IRQ handler */ 1549 cec_write(priv, REG_CEC_RXSHPDINTENA, 0); 1550 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 1551 1552 if (priv->audio_pdev) 1553 platform_device_unregister(priv->audio_pdev); 1554 1555 if (priv->hdmi->irq) 1556 free_irq(priv->hdmi->irq, priv); 1557 1558 del_timer_sync(&priv->edid_delay_timer); 1559 cancel_work_sync(&priv->detect_work); 1560 1561 i2c_unregister_device(priv->cec); 1562 1563 if (priv->cec_notify) 1564 cec_notifier_put(priv->cec_notify); 1565 } 1566 1567 /* I2C driver functions */ 1568 1569 static int tda998x_get_audio_ports(struct tda998x_priv *priv, 1570 struct device_node *np) 1571 { 1572 const u32 *port_data; 1573 u32 size; 1574 int i; 1575 1576 port_data = of_get_property(np, "audio-ports", &size); 1577 if (!port_data) 1578 return 0; 1579 1580 size /= sizeof(u32); 1581 if (size > 2 * ARRAY_SIZE(priv->audio_port) || size % 2 != 0) { 1582 dev_err(&priv->hdmi->dev, 1583 "Bad number of elements in audio-ports dt-property\n"); 1584 return -EINVAL; 1585 } 1586 1587 size /= 2; 1588 1589 for (i = 0; i < size; i++) { 1590 u8 afmt = be32_to_cpup(&port_data[2*i]); 1591 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]); 1592 1593 if (afmt != AFMT_SPDIF && afmt != AFMT_I2S) { 1594 dev_err(&priv->hdmi->dev, 1595 "Bad audio format %u\n", afmt); 1596 return -EINVAL; 1597 } 1598 1599 priv->audio_port[i].format = afmt; 1600 priv->audio_port[i].config = ena_ap; 1601 } 1602 1603 if (priv->audio_port[0].format == priv->audio_port[1].format) { 1604 dev_err(&priv->hdmi->dev, 1605 "There can only be on I2S port and one SPDIF port\n"); 1606 return -EINVAL; 1607 } 1608 return 0; 1609 } 1610 1611 static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv) 1612 { 1613 struct device_node *np = client->dev.of_node; 1614 struct i2c_board_info cec_info; 1615 u32 video; 1616 int rev_lo, rev_hi, ret; 1617 1618 mutex_init(&priv->mutex); /* protect the page access */ 1619 mutex_init(&priv->audio_mutex); /* protect access from audio thread */ 1620 mutex_init(&priv->edid_mutex); 1621 init_waitqueue_head(&priv->edid_delay_waitq); 1622 timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0); 1623 INIT_WORK(&priv->detect_work, tda998x_detect_work); 1624 1625 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); 1626 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); 1627 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); 1628 1629 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */ 1630 priv->cec_addr = 0x34 + (client->addr & 0x03); 1631 priv->current_page = 0xff; 1632 priv->hdmi = client; 1633 1634 /* wake up the device: */ 1635 cec_write(priv, REG_CEC_ENAMODS, 1636 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); 1637 1638 tda998x_reset(priv); 1639 1640 /* read version: */ 1641 rev_lo = reg_read(priv, REG_VERSION_LSB); 1642 if (rev_lo < 0) { 1643 dev_err(&client->dev, "failed to read version: %d\n", rev_lo); 1644 return rev_lo; 1645 } 1646 1647 rev_hi = reg_read(priv, REG_VERSION_MSB); 1648 if (rev_hi < 0) { 1649 dev_err(&client->dev, "failed to read version: %d\n", rev_hi); 1650 return rev_hi; 1651 } 1652 1653 priv->rev = rev_lo | rev_hi << 8; 1654 1655 /* mask off feature bits: */ 1656 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ 1657 1658 switch (priv->rev) { 1659 case TDA9989N2: 1660 dev_info(&client->dev, "found TDA9989 n2"); 1661 break; 1662 case TDA19989: 1663 dev_info(&client->dev, "found TDA19989"); 1664 break; 1665 case TDA19989N2: 1666 dev_info(&client->dev, "found TDA19989 n2"); 1667 break; 1668 case TDA19988: 1669 dev_info(&client->dev, "found TDA19988"); 1670 break; 1671 default: 1672 dev_err(&client->dev, "found unsupported device: %04x\n", 1673 priv->rev); 1674 return -ENXIO; 1675 } 1676 1677 /* after reset, enable DDC: */ 1678 reg_write(priv, REG_DDC_DISABLE, 0x00); 1679 1680 /* set clock on DDC channel: */ 1681 reg_write(priv, REG_TX3, 39); 1682 1683 /* if necessary, disable multi-master: */ 1684 if (priv->rev == TDA19989) 1685 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM); 1686 1687 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL, 1688 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); 1689 1690 /* ensure interrupts are disabled */ 1691 cec_write(priv, REG_CEC_RXSHPDINTENA, 0); 1692 1693 /* clear pending interrupts */ 1694 cec_read(priv, REG_CEC_RXSHPDINT); 1695 reg_read(priv, REG_INT_FLAGS_0); 1696 reg_read(priv, REG_INT_FLAGS_1); 1697 reg_read(priv, REG_INT_FLAGS_2); 1698 1699 /* initialize the optional IRQ */ 1700 if (client->irq) { 1701 unsigned long irq_flags; 1702 1703 /* init read EDID waitqueue and HDP work */ 1704 init_waitqueue_head(&priv->wq_edid); 1705 1706 irq_flags = 1707 irqd_get_trigger_type(irq_get_irq_data(client->irq)); 1708 1709 priv->cec_glue.irq_flags = irq_flags; 1710 1711 irq_flags |= IRQF_SHARED | IRQF_ONESHOT; 1712 ret = request_threaded_irq(client->irq, NULL, 1713 tda998x_irq_thread, irq_flags, 1714 "tda998x", priv); 1715 if (ret) { 1716 dev_err(&client->dev, 1717 "failed to request IRQ#%u: %d\n", 1718 client->irq, ret); 1719 goto err_irq; 1720 } 1721 1722 /* enable HPD irq */ 1723 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD); 1724 } 1725 1726 priv->cec_notify = cec_notifier_get(&client->dev); 1727 if (!priv->cec_notify) { 1728 ret = -ENOMEM; 1729 goto fail; 1730 } 1731 1732 priv->cec_glue.parent = &client->dev; 1733 priv->cec_glue.data = priv; 1734 priv->cec_glue.init = tda998x_cec_hook_init; 1735 priv->cec_glue.exit = tda998x_cec_hook_exit; 1736 priv->cec_glue.open = tda998x_cec_hook_open; 1737 priv->cec_glue.release = tda998x_cec_hook_release; 1738 1739 /* 1740 * Some TDA998x are actually two I2C devices merged onto one piece 1741 * of silicon: TDA9989 and TDA19989 combine the HDMI transmitter 1742 * with a slightly modified TDA9950 CEC device. The CEC device 1743 * is at the TDA9950 address, with the address pins strapped across 1744 * to the TDA998x address pins. Hence, it always has the same 1745 * offset. 1746 */ 1747 memset(&cec_info, 0, sizeof(cec_info)); 1748 strlcpy(cec_info.type, "tda9950", sizeof(cec_info.type)); 1749 cec_info.addr = priv->cec_addr; 1750 cec_info.platform_data = &priv->cec_glue; 1751 cec_info.irq = client->irq; 1752 1753 priv->cec = i2c_new_device(client->adapter, &cec_info); 1754 if (!priv->cec) { 1755 ret = -ENODEV; 1756 goto fail; 1757 } 1758 1759 /* enable EDID read irq: */ 1760 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 1761 1762 if (!np) 1763 return 0; /* non-DT */ 1764 1765 /* get the device tree parameters */ 1766 ret = of_property_read_u32(np, "video-ports", &video); 1767 if (ret == 0) { 1768 priv->vip_cntrl_0 = video >> 16; 1769 priv->vip_cntrl_1 = video >> 8; 1770 priv->vip_cntrl_2 = video; 1771 } 1772 1773 ret = tda998x_get_audio_ports(priv, np); 1774 if (ret) 1775 goto fail; 1776 1777 if (priv->audio_port[0].format != AFMT_UNUSED) 1778 tda998x_audio_codec_init(priv, &client->dev); 1779 1780 return 0; 1781 1782 fail: 1783 /* if encoder_init fails, the encoder slave is never registered, 1784 * so cleanup here: 1785 */ 1786 i2c_unregister_device(priv->cec); 1787 if (priv->cec_notify) 1788 cec_notifier_put(priv->cec_notify); 1789 if (client->irq) 1790 free_irq(client->irq, priv); 1791 err_irq: 1792 return ret; 1793 } 1794 1795 static void tda998x_encoder_prepare(struct drm_encoder *encoder) 1796 { 1797 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 1798 } 1799 1800 static void tda998x_encoder_commit(struct drm_encoder *encoder) 1801 { 1802 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 1803 } 1804 1805 static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = { 1806 .dpms = tda998x_encoder_dpms, 1807 .prepare = tda998x_encoder_prepare, 1808 .commit = tda998x_encoder_commit, 1809 .mode_set = tda998x_encoder_mode_set, 1810 }; 1811 1812 static void tda998x_encoder_destroy(struct drm_encoder *encoder) 1813 { 1814 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder); 1815 1816 tda998x_destroy(priv); 1817 drm_encoder_cleanup(encoder); 1818 } 1819 1820 static const struct drm_encoder_funcs tda998x_encoder_funcs = { 1821 .destroy = tda998x_encoder_destroy, 1822 }; 1823 1824 static void tda998x_set_config(struct tda998x_priv *priv, 1825 const struct tda998x_encoder_params *p) 1826 { 1827 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | 1828 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | 1829 VIP_CNTRL_0_SWAP_B(p->swap_b) | 1830 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); 1831 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | 1832 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | 1833 VIP_CNTRL_1_SWAP_D(p->swap_d) | 1834 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); 1835 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | 1836 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | 1837 VIP_CNTRL_2_SWAP_F(p->swap_f) | 1838 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); 1839 1840 priv->audio_params = p->audio_params; 1841 } 1842 1843 static int tda998x_bind(struct device *dev, struct device *master, void *data) 1844 { 1845 struct tda998x_encoder_params *params = dev->platform_data; 1846 struct i2c_client *client = to_i2c_client(dev); 1847 struct drm_device *drm = data; 1848 struct tda998x_priv *priv; 1849 u32 crtcs = 0; 1850 int ret; 1851 1852 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1853 if (!priv) 1854 return -ENOMEM; 1855 1856 dev_set_drvdata(dev, priv); 1857 1858 if (dev->of_node) 1859 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); 1860 1861 /* If no CRTCs were found, fall back to our old behaviour */ 1862 if (crtcs == 0) { 1863 dev_warn(dev, "Falling back to first CRTC\n"); 1864 crtcs = 1 << 0; 1865 } 1866 1867 priv->encoder.possible_crtcs = crtcs; 1868 1869 ret = tda998x_create(client, priv); 1870 if (ret) 1871 return ret; 1872 1873 if (!dev->of_node && params) 1874 tda998x_set_config(priv, params); 1875 1876 drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs); 1877 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs, 1878 DRM_MODE_ENCODER_TMDS, NULL); 1879 if (ret) 1880 goto err_encoder; 1881 1882 ret = tda998x_connector_init(priv, drm); 1883 if (ret) 1884 goto err_connector; 1885 1886 return 0; 1887 1888 err_connector: 1889 drm_encoder_cleanup(&priv->encoder); 1890 err_encoder: 1891 tda998x_destroy(priv); 1892 return ret; 1893 } 1894 1895 static void tda998x_unbind(struct device *dev, struct device *master, 1896 void *data) 1897 { 1898 struct tda998x_priv *priv = dev_get_drvdata(dev); 1899 1900 drm_connector_cleanup(&priv->connector); 1901 drm_encoder_cleanup(&priv->encoder); 1902 tda998x_destroy(priv); 1903 } 1904 1905 static const struct component_ops tda998x_ops = { 1906 .bind = tda998x_bind, 1907 .unbind = tda998x_unbind, 1908 }; 1909 1910 static int 1911 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) 1912 { 1913 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1914 dev_warn(&client->dev, "adapter does not support I2C\n"); 1915 return -EIO; 1916 } 1917 return component_add(&client->dev, &tda998x_ops); 1918 } 1919 1920 static int tda998x_remove(struct i2c_client *client) 1921 { 1922 component_del(&client->dev, &tda998x_ops); 1923 return 0; 1924 } 1925 1926 #ifdef CONFIG_OF 1927 static const struct of_device_id tda998x_dt_ids[] = { 1928 { .compatible = "nxp,tda998x", }, 1929 { } 1930 }; 1931 MODULE_DEVICE_TABLE(of, tda998x_dt_ids); 1932 #endif 1933 1934 static const struct i2c_device_id tda998x_ids[] = { 1935 { "tda998x", 0 }, 1936 { } 1937 }; 1938 MODULE_DEVICE_TABLE(i2c, tda998x_ids); 1939 1940 static struct i2c_driver tda998x_driver = { 1941 .probe = tda998x_probe, 1942 .remove = tda998x_remove, 1943 .driver = { 1944 .name = "tda998x", 1945 .of_match_table = of_match_ptr(tda998x_dt_ids), 1946 }, 1947 .id_table = tda998x_ids, 1948 }; 1949 1950 module_i2c_driver(tda998x_driver); 1951 1952 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1953 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); 1954 MODULE_LICENSE("GPL"); 1955