1 /* 2 * Copyright (C) 2009 Francisco Jerez. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef __DRM_I2C_CH7006_PRIV_H__ 28 #define __DRM_I2C_CH7006_PRIV_H__ 29 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/drm_encoder_slave.h> 33 #include <drm/drm_probe_helper.h> 34 #include <drm/i2c/ch7006.h> 35 36 typedef int64_t fixed; 37 #define fixed1 (1LL << 32) 38 39 enum ch7006_tv_norm { 40 TV_NORM_PAL, 41 TV_NORM_PAL_M, 42 TV_NORM_PAL_N, 43 TV_NORM_PAL_NC, 44 TV_NORM_PAL_60, 45 TV_NORM_NTSC_M, 46 TV_NORM_NTSC_J, 47 NUM_TV_NORMS 48 }; 49 50 struct ch7006_tv_norm_info { 51 fixed vrefresh; 52 int vdisplay; 53 int vtotal; 54 int hvirtual; 55 56 fixed subc_freq; 57 fixed black_level; 58 59 uint32_t dispmode; 60 int voffset; 61 }; 62 63 struct ch7006_mode { 64 struct drm_display_mode mode; 65 66 int enc_hdisp; 67 int enc_vdisp; 68 69 fixed subc_coeff; 70 uint32_t dispmode; 71 72 uint32_t valid_scales; 73 uint32_t valid_norms; 74 }; 75 76 struct ch7006_state { 77 uint8_t regs[0x26]; 78 }; 79 80 struct ch7006_priv { 81 struct ch7006_encoder_params params; 82 const struct ch7006_mode *mode; 83 84 struct ch7006_state state; 85 struct ch7006_state saved_state; 86 87 struct drm_property *scale_property; 88 89 int select_subconnector; 90 int subconnector; 91 int hmargin; 92 int vmargin; 93 enum ch7006_tv_norm norm; 94 int brightness; 95 int contrast; 96 int flicker; 97 int scale; 98 99 int chip_version; 100 int last_dpms; 101 }; 102 103 #define to_ch7006_priv(x) \ 104 ((struct ch7006_priv *)to_encoder_slave(x)->slave_priv) 105 106 extern int ch7006_debug; 107 extern char *ch7006_tv_norm; 108 extern int ch7006_scale; 109 110 extern const char * const ch7006_tv_norm_names[]; 111 extern const struct ch7006_tv_norm_info ch7006_tv_norms[]; 112 extern const struct ch7006_mode ch7006_modes[]; 113 114 const struct ch7006_mode *ch7006_lookup_mode(struct drm_encoder *encoder, 115 const struct drm_display_mode *drm_mode); 116 117 void ch7006_setup_levels(struct drm_encoder *encoder); 118 void ch7006_setup_subcarrier(struct drm_encoder *encoder); 119 void ch7006_setup_pll(struct drm_encoder *encoder); 120 void ch7006_setup_power_state(struct drm_encoder *encoder); 121 void ch7006_setup_properties(struct drm_encoder *encoder); 122 123 void ch7006_write(struct i2c_client *client, uint8_t addr, uint8_t val); 124 uint8_t ch7006_read(struct i2c_client *client, uint8_t addr); 125 126 void ch7006_state_load(struct i2c_client *client, 127 struct ch7006_state *state); 128 void ch7006_state_save(struct i2c_client *client, 129 struct ch7006_state *state); 130 131 /* Some helper macros */ 132 133 #define ch7006_dbg(client, format, ...) do { \ 134 if (ch7006_debug) \ 135 dev_printk(KERN_DEBUG, &client->dev, \ 136 "%s: " format, __func__, ## __VA_ARGS__); \ 137 } while (0) 138 #define ch7006_info(client, format, ...) \ 139 dev_info(&client->dev, format, __VA_ARGS__) 140 #define ch7006_err(client, format, ...) \ 141 dev_err(&client->dev, format, __VA_ARGS__) 142 143 #define __mask(src, bitfield) \ 144 (((2 << (1 ? bitfield)) - 1) & ~((1 << (0 ? bitfield)) - 1)) 145 #define mask(bitfield) __mask(bitfield) 146 147 #define __bitf(src, bitfield, x) \ 148 (((x) >> (src) << (0 ? bitfield)) & __mask(src, bitfield)) 149 #define bitf(bitfield, x) __bitf(bitfield, x) 150 #define bitfs(bitfield, s) __bitf(bitfield, bitfield##_##s) 151 #define setbitf(state, reg, bitfield, x) \ 152 state->regs[reg] = (state->regs[reg] & ~mask(reg##_##bitfield)) \ 153 | bitf(reg##_##bitfield, x) 154 155 #define __unbitf(src, bitfield, x) \ 156 ((x & __mask(src, bitfield)) >> (0 ? bitfield) << (src)) 157 #define unbitf(bitfield, x) __unbitf(bitfield, x) 158 159 static inline int interpolate(int y0, int y1, int y2, int x) 160 { 161 return y1 + (x < 50 ? y1 - y0 : y2 - y1) * (x - 50) / 50; 162 } 163 164 static inline int32_t round_fixed(fixed x) 165 { 166 return (x + fixed1/2) >> 32; 167 } 168 169 #define ch7006_load_reg(client, state, reg) ch7006_write(client, reg, state->regs[reg]) 170 #define ch7006_save_reg(client, state, reg) state->regs[reg] = ch7006_read(client, reg) 171 172 /* Fixed hardware specs */ 173 174 #define CH7006_FREQ0 14318 175 #define CH7006_MAXN 650 176 #define CH7006_MAXM 315 177 178 /* Register definitions */ 179 180 #define CH7006_DISPMODE 0x00 181 #define CH7006_DISPMODE_INPUT_RES 0, 7:5 182 #define CH7006_DISPMODE_INPUT_RES_512x384 0x0 183 #define CH7006_DISPMODE_INPUT_RES_720x400 0x1 184 #define CH7006_DISPMODE_INPUT_RES_640x400 0x2 185 #define CH7006_DISPMODE_INPUT_RES_640x480 0x3 186 #define CH7006_DISPMODE_INPUT_RES_800x600 0x4 187 #define CH7006_DISPMODE_INPUT_RES_NATIVE 0x5 188 #define CH7006_DISPMODE_OUTPUT_STD 0, 4:3 189 #define CH7006_DISPMODE_OUTPUT_STD_PAL 0x0 190 #define CH7006_DISPMODE_OUTPUT_STD_NTSC 0x1 191 #define CH7006_DISPMODE_OUTPUT_STD_PAL_M 0x2 192 #define CH7006_DISPMODE_OUTPUT_STD_NTSC_J 0x3 193 #define CH7006_DISPMODE_SCALING_RATIO 0, 2:0 194 #define CH7006_DISPMODE_SCALING_RATIO_5_4 0x0 195 #define CH7006_DISPMODE_SCALING_RATIO_1_1 0x1 196 #define CH7006_DISPMODE_SCALING_RATIO_7_8 0x2 197 #define CH7006_DISPMODE_SCALING_RATIO_5_6 0x3 198 #define CH7006_DISPMODE_SCALING_RATIO_3_4 0x4 199 #define CH7006_DISPMODE_SCALING_RATIO_7_10 0x5 200 201 #define CH7006_FFILTER 0x01 202 #define CH7006_FFILTER_TEXT 0, 5:4 203 #define CH7006_FFILTER_LUMA 0, 3:2 204 #define CH7006_FFILTER_CHROMA 0, 1:0 205 #define CH7006_FFILTER_CHROMA_NO_DCRAWL 0x3 206 207 #define CH7006_BWIDTH 0x03 208 #define CH7006_BWIDTH_5L_FFILER (1 << 7) 209 #define CH7006_BWIDTH_CVBS_NO_CHROMA (1 << 6) 210 #define CH7006_BWIDTH_CHROMA 0, 5:4 211 #define CH7006_BWIDTH_SVIDEO_YPEAK (1 << 3) 212 #define CH7006_BWIDTH_SVIDEO_LUMA 0, 2:1 213 #define CH7006_BWIDTH_CVBS_LUMA 0, 0:0 214 215 #define CH7006_INPUT_FORMAT 0x04 216 #define CH7006_INPUT_FORMAT_DAC_GAIN (1 << 6) 217 #define CH7006_INPUT_FORMAT_RGB_PASS_THROUGH (1 << 5) 218 #define CH7006_INPUT_FORMAT_FORMAT 0, 3:0 219 #define CH7006_INPUT_FORMAT_FORMAT_RGB16 0x0 220 #define CH7006_INPUT_FORMAT_FORMAT_YCrCb24m16 0x1 221 #define CH7006_INPUT_FORMAT_FORMAT_RGB24m16 0x2 222 #define CH7006_INPUT_FORMAT_FORMAT_RGB15 0x3 223 #define CH7006_INPUT_FORMAT_FORMAT_RGB24m12C 0x4 224 #define CH7006_INPUT_FORMAT_FORMAT_RGB24m12I 0x5 225 #define CH7006_INPUT_FORMAT_FORMAT_RGB24m8 0x6 226 #define CH7006_INPUT_FORMAT_FORMAT_RGB16m8 0x7 227 #define CH7006_INPUT_FORMAT_FORMAT_RGB15m8 0x8 228 #define CH7006_INPUT_FORMAT_FORMAT_YCrCb24m8 0x9 229 230 #define CH7006_CLKMODE 0x06 231 #define CH7006_CLKMODE_SUBC_LOCK (1 << 7) 232 #define CH7006_CLKMODE_MASTER (1 << 6) 233 #define CH7006_CLKMODE_POS_EDGE (1 << 4) 234 #define CH7006_CLKMODE_XCM 0, 3:2 235 #define CH7006_CLKMODE_PCM 0, 1:0 236 237 #define CH7006_START_ACTIVE 0x07 238 #define CH7006_START_ACTIVE_0 0, 7:0 239 240 #define CH7006_POV 0x08 241 #define CH7006_POV_START_ACTIVE_8 8, 2:2 242 #define CH7006_POV_HPOS_8 8, 1:1 243 #define CH7006_POV_VPOS_8 8, 0:0 244 245 #define CH7006_BLACK_LEVEL 0x09 246 #define CH7006_BLACK_LEVEL_0 0, 7:0 247 248 #define CH7006_HPOS 0x0a 249 #define CH7006_HPOS_0 0, 7:0 250 251 #define CH7006_VPOS 0x0b 252 #define CH7006_VPOS_0 0, 7:0 253 254 #define CH7006_INPUT_SYNC 0x0d 255 #define CH7006_INPUT_SYNC_EMBEDDED (1 << 3) 256 #define CH7006_INPUT_SYNC_OUTPUT (1 << 2) 257 #define CH7006_INPUT_SYNC_PVSYNC (1 << 1) 258 #define CH7006_INPUT_SYNC_PHSYNC (1 << 0) 259 260 #define CH7006_POWER 0x0e 261 #define CH7006_POWER_SCART (1 << 4) 262 #define CH7006_POWER_RESET (1 << 3) 263 #define CH7006_POWER_LEVEL 0, 2:0 264 #define CH7006_POWER_LEVEL_CVBS_OFF 0x0 265 #define CH7006_POWER_LEVEL_POWER_OFF 0x1 266 #define CH7006_POWER_LEVEL_SVIDEO_OFF 0x2 267 #define CH7006_POWER_LEVEL_NORMAL 0x3 268 #define CH7006_POWER_LEVEL_FULL_POWER_OFF 0x4 269 270 #define CH7006_DETECT 0x10 271 #define CH7006_DETECT_SVIDEO_Y_TEST (1 << 3) 272 #define CH7006_DETECT_SVIDEO_C_TEST (1 << 2) 273 #define CH7006_DETECT_CVBS_TEST (1 << 1) 274 #define CH7006_DETECT_SENSE (1 << 0) 275 276 #define CH7006_CONTRAST 0x11 277 #define CH7006_CONTRAST_0 0, 2:0 278 279 #define CH7006_PLLOV 0x13 280 #define CH7006_PLLOV_N_8 8, 2:1 281 #define CH7006_PLLOV_M_8 8, 0:0 282 283 #define CH7006_PLLM 0x14 284 #define CH7006_PLLM_0 0, 7:0 285 286 #define CH7006_PLLN 0x15 287 #define CH7006_PLLN_0 0, 7:0 288 289 #define CH7006_BCLKOUT 0x17 290 291 #define CH7006_SUBC_INC0 0x18 292 #define CH7006_SUBC_INC0_28 28, 3:0 293 294 #define CH7006_SUBC_INC1 0x19 295 #define CH7006_SUBC_INC1_24 24, 3:0 296 297 #define CH7006_SUBC_INC2 0x1a 298 #define CH7006_SUBC_INC2_20 20, 3:0 299 300 #define CH7006_SUBC_INC3 0x1b 301 #define CH7006_SUBC_INC3_GPIO1_VAL (1 << 7) 302 #define CH7006_SUBC_INC3_GPIO0_VAL (1 << 6) 303 #define CH7006_SUBC_INC3_POUT_3_3V (1 << 5) 304 #define CH7006_SUBC_INC3_POUT_INV (1 << 4) 305 #define CH7006_SUBC_INC3_16 16, 3:0 306 307 #define CH7006_SUBC_INC4 0x1c 308 #define CH7006_SUBC_INC4_GPIO1_IN (1 << 7) 309 #define CH7006_SUBC_INC4_GPIO0_IN (1 << 6) 310 #define CH7006_SUBC_INC4_DS_INPUT (1 << 4) 311 #define CH7006_SUBC_INC4_12 12, 3:0 312 313 #define CH7006_SUBC_INC5 0x1d 314 #define CH7006_SUBC_INC5_8 8, 3:0 315 316 #define CH7006_SUBC_INC6 0x1e 317 #define CH7006_SUBC_INC6_4 4, 3:0 318 319 #define CH7006_SUBC_INC7 0x1f 320 #define CH7006_SUBC_INC7_0 0, 3:0 321 322 #define CH7006_PLL_CONTROL 0x20 323 #define CH7006_PLL_CONTROL_CPI (1 << 5) 324 #define CH7006_PLL_CONTROL_CAPACITOR (1 << 4) 325 #define CH7006_PLL_CONTROL_7STAGES (1 << 3) 326 #define CH7006_PLL_CONTROL_DIGITAL_5V (1 << 2) 327 #define CH7006_PLL_CONTROL_ANALOG_5V (1 << 1) 328 #define CH7006_PLL_CONTROL_MEMORY_5V (1 << 0) 329 330 #define CH7006_CALC_SUBC_INC0 0x21 331 #define CH7006_CALC_SUBC_INC0_24 24, 4:3 332 #define CH7006_CALC_SUBC_INC0_HYST 0, 2:1 333 #define CH7006_CALC_SUBC_INC0_AUTO (1 << 0) 334 335 #define CH7006_CALC_SUBC_INC1 0x22 336 #define CH7006_CALC_SUBC_INC1_16 16, 7:0 337 338 #define CH7006_CALC_SUBC_INC2 0x23 339 #define CH7006_CALC_SUBC_INC2_8 8, 7:0 340 341 #define CH7006_CALC_SUBC_INC3 0x24 342 #define CH7006_CALC_SUBC_INC3_0 0, 7:0 343 344 #define CH7006_VERSION_ID 0x25 345 346 #endif 347