1 /*
2  * Hisilicon Hi6220 SoC ADE(Advanced Display Engine)'s crtc&plane driver
3  *
4  * Copyright (c) 2016 Linaro Limited.
5  * Copyright (c) 2014-2016 Hisilicon Limited.
6  *
7  * Author:
8  *	Xinliang Liu <z.liuxinliang@hisilicon.com>
9  *	Xinliang Liu <xinliang.liu@linaro.org>
10  *	Xinwei Kong <kong.kongxinwei@hisilicon.com>
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation.
15  *
16  */
17 
18 #include <linux/bitops.h>
19 #include <linux/clk.h>
20 #include <video/display_timing.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/regmap.h>
23 #include <linux/reset.h>
24 
25 #include <drm/drmP.h>
26 #include <drm/drm_crtc.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_plane_helper.h>
31 #include <drm/drm_gem_cma_helper.h>
32 #include <drm/drm_fb_cma_helper.h>
33 
34 #include "kirin_drm_drv.h"
35 #include "kirin_ade_reg.h"
36 
37 #define PRIMARY_CH	ADE_CH1 /* primary plane */
38 #define OUT_OVLY	ADE_OVLY2 /* output overlay compositor */
39 #define ADE_DEBUG	1
40 
41 #define to_ade_crtc(crtc) \
42 	container_of(crtc, struct ade_crtc, base)
43 
44 #define to_ade_plane(plane) \
45 	container_of(plane, struct ade_plane, base)
46 
47 struct ade_hw_ctx {
48 	void __iomem  *base;
49 	struct regmap *noc_regmap;
50 	struct clk *ade_core_clk;
51 	struct clk *media_noc_clk;
52 	struct clk *ade_pix_clk;
53 	struct reset_control *reset;
54 	bool power_on;
55 	int irq;
56 };
57 
58 struct ade_crtc {
59 	struct drm_crtc base;
60 	struct ade_hw_ctx *ctx;
61 	bool enable;
62 	u32 out_format;
63 };
64 
65 struct ade_plane {
66 	struct drm_plane base;
67 	void *ctx;
68 	u8 ch; /* channel */
69 };
70 
71 struct ade_data {
72 	struct ade_crtc acrtc;
73 	struct ade_plane aplane[ADE_CH_NUM];
74 	struct ade_hw_ctx ctx;
75 };
76 
77 /* ade-format info: */
78 struct ade_format {
79 	u32 pixel_format;
80 	enum ade_fb_format ade_format;
81 };
82 
83 static const struct ade_format ade_formats[] = {
84 	/* 16bpp RGB: */
85 	{ DRM_FORMAT_RGB565, ADE_RGB_565 },
86 	{ DRM_FORMAT_BGR565, ADE_BGR_565 },
87 	/* 24bpp RGB: */
88 	{ DRM_FORMAT_RGB888, ADE_RGB_888 },
89 	{ DRM_FORMAT_BGR888, ADE_BGR_888 },
90 	/* 32bpp [A]RGB: */
91 	{ DRM_FORMAT_XRGB8888, ADE_XRGB_8888 },
92 	{ DRM_FORMAT_XBGR8888, ADE_XBGR_8888 },
93 	{ DRM_FORMAT_RGBA8888, ADE_RGBA_8888 },
94 	{ DRM_FORMAT_BGRA8888, ADE_BGRA_8888 },
95 	{ DRM_FORMAT_ARGB8888, ADE_ARGB_8888 },
96 	{ DRM_FORMAT_ABGR8888, ADE_ABGR_8888 },
97 };
98 
99 static const u32 channel_formats1[] = {
100 	/* channel 1,2,3,4 */
101 	DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888,
102 	DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
103 	DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888,
104 	DRM_FORMAT_ABGR8888
105 };
106 
107 u32 ade_get_channel_formats(u8 ch, const u32 **formats)
108 {
109 	switch (ch) {
110 	case ADE_CH1:
111 		*formats = channel_formats1;
112 		return ARRAY_SIZE(channel_formats1);
113 	default:
114 		DRM_ERROR("no this channel %d\n", ch);
115 		*formats = NULL;
116 		return 0;
117 	}
118 }
119 
120 /* convert from fourcc format to ade format */
121 static u32 ade_get_format(u32 pixel_format)
122 {
123 	int i;
124 
125 	for (i = 0; i < ARRAY_SIZE(ade_formats); i++)
126 		if (ade_formats[i].pixel_format == pixel_format)
127 			return ade_formats[i].ade_format;
128 
129 	/* not found */
130 	DRM_ERROR("Not found pixel format!!fourcc_format= %d\n",
131 		  pixel_format);
132 	return ADE_FORMAT_UNSUPPORT;
133 }
134 
135 static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val)
136 {
137 	u32 bit_ofst, reg_num;
138 
139 	bit_ofst = bit_num % 32;
140 	reg_num = bit_num / 32;
141 
142 	ade_update_bits(base + ADE_RELOAD_DIS(reg_num), bit_ofst,
143 			MASK(1), !!val);
144 }
145 
146 static u32 ade_read_reload_bit(void __iomem *base, u32 bit_num)
147 {
148 	u32 tmp, bit_ofst, reg_num;
149 
150 	bit_ofst = bit_num % 32;
151 	reg_num = bit_num / 32;
152 
153 	tmp = readl(base + ADE_RELOAD_DIS(reg_num));
154 	return !!(BIT(bit_ofst) & tmp);
155 }
156 
157 static void ade_init(struct ade_hw_ctx *ctx)
158 {
159 	void __iomem *base = ctx->base;
160 
161 	/* enable clk gate */
162 	ade_update_bits(base + ADE_CTRL1, AUTO_CLK_GATE_EN_OFST,
163 			AUTO_CLK_GATE_EN, ADE_ENABLE);
164 	/* clear overlay */
165 	writel(0, base + ADE_OVLY1_TRANS_CFG);
166 	writel(0, base + ADE_OVLY_CTL);
167 	writel(0, base + ADE_OVLYX_CTL(OUT_OVLY));
168 	/* clear reset and reload regs */
169 	writel(MASK(32), base + ADE_SOFT_RST_SEL(0));
170 	writel(MASK(32), base + ADE_SOFT_RST_SEL(1));
171 	writel(MASK(32), base + ADE_RELOAD_DIS(0));
172 	writel(MASK(32), base + ADE_RELOAD_DIS(1));
173 	/*
174 	 * for video mode, all the ade registers should
175 	 * become effective at frame end.
176 	 */
177 	ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST,
178 			FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND);
179 }
180 
181 static bool ade_crtc_mode_fixup(struct drm_crtc *crtc,
182 				const struct drm_display_mode *mode,
183 				struct drm_display_mode *adjusted_mode)
184 {
185 	struct ade_crtc *acrtc = to_ade_crtc(crtc);
186 	struct ade_hw_ctx *ctx = acrtc->ctx;
187 
188 	adjusted_mode->clock =
189 		clk_round_rate(ctx->ade_pix_clk, mode->clock * 1000) / 1000;
190 	return true;
191 }
192 
193 
194 static void ade_set_pix_clk(struct ade_hw_ctx *ctx,
195 			    struct drm_display_mode *mode,
196 			    struct drm_display_mode *adj_mode)
197 {
198 	u32 clk_Hz = mode->clock * 1000;
199 	int ret;
200 
201 	/*
202 	 * Success should be guaranteed in mode_valid call back,
203 	 * so failure shouldn't happen here
204 	 */
205 	ret = clk_set_rate(ctx->ade_pix_clk, clk_Hz);
206 	if (ret)
207 		DRM_ERROR("failed to set pixel clk %dHz (%d)\n", clk_Hz, ret);
208 	adj_mode->clock = clk_get_rate(ctx->ade_pix_clk) / 1000;
209 }
210 
211 static void ade_ldi_set_mode(struct ade_crtc *acrtc,
212 			     struct drm_display_mode *mode,
213 			     struct drm_display_mode *adj_mode)
214 {
215 	struct ade_hw_ctx *ctx = acrtc->ctx;
216 	void __iomem *base = ctx->base;
217 	u32 width = mode->hdisplay;
218 	u32 height = mode->vdisplay;
219 	u32 hfp, hbp, hsw, vfp, vbp, vsw;
220 	u32 plr_flags;
221 
222 	plr_flags = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? FLAG_NVSYNC : 0;
223 	plr_flags |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? FLAG_NHSYNC : 0;
224 	hfp = mode->hsync_start - mode->hdisplay;
225 	hbp = mode->htotal - mode->hsync_end;
226 	hsw = mode->hsync_end - mode->hsync_start;
227 	vfp = mode->vsync_start - mode->vdisplay;
228 	vbp = mode->vtotal - mode->vsync_end;
229 	vsw = mode->vsync_end - mode->vsync_start;
230 	if (vsw > 15) {
231 		DRM_DEBUG_DRIVER("vsw exceeded 15\n");
232 		vsw = 15;
233 	}
234 
235 	writel((hbp << HBP_OFST) | hfp, base + LDI_HRZ_CTRL0);
236 	 /* the configured value is actual value - 1 */
237 	writel(hsw - 1, base + LDI_HRZ_CTRL1);
238 	writel((vbp << VBP_OFST) | vfp, base + LDI_VRT_CTRL0);
239 	 /* the configured value is actual value - 1 */
240 	writel(vsw - 1, base + LDI_VRT_CTRL1);
241 	 /* the configured value is actual value - 1 */
242 	writel(((height - 1) << VSIZE_OFST) | (width - 1),
243 	       base + LDI_DSP_SIZE);
244 	writel(plr_flags, base + LDI_PLR_CTRL);
245 
246 	/* set overlay compositor output size */
247 	writel(((width - 1) << OUTPUT_XSIZE_OFST) | (height - 1),
248 	       base + ADE_OVLY_OUTPUT_SIZE(OUT_OVLY));
249 
250 	/* ctran6 setting */
251 	writel(CTRAN_BYPASS_ON, base + ADE_CTRAN_DIS(ADE_CTRAN6));
252 	 /* the configured value is actual value - 1 */
253 	writel(width * height - 1, base + ADE_CTRAN_IMAGE_SIZE(ADE_CTRAN6));
254 	ade_update_reload_bit(base, CTRAN_OFST + ADE_CTRAN6, 0);
255 
256 	ade_set_pix_clk(ctx, mode, adj_mode);
257 
258 	DRM_DEBUG_DRIVER("set mode: %dx%d\n", width, height);
259 }
260 
261 static int ade_power_up(struct ade_hw_ctx *ctx)
262 {
263 	int ret;
264 
265 	ret = clk_prepare_enable(ctx->media_noc_clk);
266 	if (ret) {
267 		DRM_ERROR("failed to enable media_noc_clk (%d)\n", ret);
268 		return ret;
269 	}
270 
271 	ret = reset_control_deassert(ctx->reset);
272 	if (ret) {
273 		DRM_ERROR("failed to deassert reset\n");
274 		return ret;
275 	}
276 
277 	ret = clk_prepare_enable(ctx->ade_core_clk);
278 	if (ret) {
279 		DRM_ERROR("failed to enable ade_core_clk (%d)\n", ret);
280 		return ret;
281 	}
282 
283 	ade_init(ctx);
284 	ctx->power_on = true;
285 	return 0;
286 }
287 
288 static void ade_power_down(struct ade_hw_ctx *ctx)
289 {
290 	void __iomem *base = ctx->base;
291 
292 	writel(ADE_DISABLE, base + LDI_CTRL);
293 	/* dsi pixel off */
294 	writel(DSI_PCLK_OFF, base + LDI_HDMI_DSI_GT);
295 
296 	clk_disable_unprepare(ctx->ade_core_clk);
297 	reset_control_assert(ctx->reset);
298 	clk_disable_unprepare(ctx->media_noc_clk);
299 	ctx->power_on = false;
300 }
301 
302 static void ade_set_medianoc_qos(struct ade_crtc *acrtc)
303 {
304 	struct ade_hw_ctx *ctx = acrtc->ctx;
305 	struct regmap *map = ctx->noc_regmap;
306 
307 	regmap_update_bits(map, ADE0_QOSGENERATOR_MODE,
308 			   QOSGENERATOR_MODE_MASK, BYPASS_MODE);
309 	regmap_update_bits(map, ADE0_QOSGENERATOR_EXTCONTROL,
310 			   SOCKET_QOS_EN, SOCKET_QOS_EN);
311 
312 	regmap_update_bits(map, ADE1_QOSGENERATOR_MODE,
313 			   QOSGENERATOR_MODE_MASK, BYPASS_MODE);
314 	regmap_update_bits(map, ADE1_QOSGENERATOR_EXTCONTROL,
315 			   SOCKET_QOS_EN, SOCKET_QOS_EN);
316 }
317 
318 static int ade_crtc_enable_vblank(struct drm_crtc *crtc)
319 {
320 	struct ade_crtc *acrtc = to_ade_crtc(crtc);
321 	struct ade_hw_ctx *ctx = acrtc->ctx;
322 	void __iomem *base = ctx->base;
323 
324 	if (!ctx->power_on)
325 		(void)ade_power_up(ctx);
326 
327 	ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST,
328 			MASK(1), 1);
329 
330 	return 0;
331 }
332 
333 static void ade_crtc_disable_vblank(struct drm_crtc *crtc)
334 {
335 	struct ade_crtc *acrtc = to_ade_crtc(crtc);
336 	struct ade_hw_ctx *ctx = acrtc->ctx;
337 	void __iomem *base = ctx->base;
338 
339 	if (!ctx->power_on) {
340 		DRM_ERROR("power is down! vblank disable fail\n");
341 		return;
342 	}
343 
344 	ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST,
345 			MASK(1), 0);
346 }
347 
348 static irqreturn_t ade_irq_handler(int irq, void *data)
349 {
350 	struct ade_crtc *acrtc = data;
351 	struct ade_hw_ctx *ctx = acrtc->ctx;
352 	struct drm_crtc *crtc = &acrtc->base;
353 	void __iomem *base = ctx->base;
354 	u32 status;
355 
356 	status = readl(base + LDI_MSK_INT);
357 	DRM_DEBUG_VBL("LDI IRQ: status=0x%X\n", status);
358 
359 	/* vblank irq */
360 	if (status & BIT(FRAME_END_INT_EN_OFST)) {
361 		ade_update_bits(base + LDI_INT_CLR, FRAME_END_INT_EN_OFST,
362 				MASK(1), 1);
363 		drm_crtc_handle_vblank(crtc);
364 	}
365 
366 	return IRQ_HANDLED;
367 }
368 
369 static void ade_display_enable(struct ade_crtc *acrtc)
370 {
371 	struct ade_hw_ctx *ctx = acrtc->ctx;
372 	void __iomem *base = ctx->base;
373 	u32 out_fmt = acrtc->out_format;
374 
375 	/* enable output overlay compositor */
376 	writel(ADE_ENABLE, base + ADE_OVLYX_CTL(OUT_OVLY));
377 	ade_update_reload_bit(base, OVLY_OFST + OUT_OVLY, 0);
378 
379 	/* display source setting */
380 	writel(DISP_SRC_OVLY2, base + ADE_DISP_SRC_CFG);
381 
382 	/* enable ade */
383 	writel(ADE_ENABLE, base + ADE_EN);
384 	/* enable ldi */
385 	writel(NORMAL_MODE, base + LDI_WORK_MODE);
386 	writel((out_fmt << BPP_OFST) | DATA_GATE_EN | LDI_EN,
387 	       base + LDI_CTRL);
388 	/* dsi pixel on */
389 	writel(DSI_PCLK_ON, base + LDI_HDMI_DSI_GT);
390 }
391 
392 #if ADE_DEBUG
393 static void ade_rdma_dump_regs(void __iomem *base, u32 ch)
394 {
395 	u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en;
396 	u32 val;
397 
398 	reg_ctrl = RD_CH_CTRL(ch);
399 	reg_addr = RD_CH_ADDR(ch);
400 	reg_size = RD_CH_SIZE(ch);
401 	reg_stride = RD_CH_STRIDE(ch);
402 	reg_space = RD_CH_SPACE(ch);
403 	reg_en = RD_CH_EN(ch);
404 
405 	val = ade_read_reload_bit(base, RDMA_OFST + ch);
406 	DRM_DEBUG_DRIVER("[rdma%d]: reload(%d)\n", ch + 1, val);
407 	val = readl(base + reg_ctrl);
408 	DRM_DEBUG_DRIVER("[rdma%d]: reg_ctrl(0x%08x)\n", ch + 1, val);
409 	val = readl(base + reg_addr);
410 	DRM_DEBUG_DRIVER("[rdma%d]: reg_addr(0x%08x)\n", ch + 1, val);
411 	val = readl(base + reg_size);
412 	DRM_DEBUG_DRIVER("[rdma%d]: reg_size(0x%08x)\n", ch + 1, val);
413 	val = readl(base + reg_stride);
414 	DRM_DEBUG_DRIVER("[rdma%d]: reg_stride(0x%08x)\n", ch + 1, val);
415 	val = readl(base + reg_space);
416 	DRM_DEBUG_DRIVER("[rdma%d]: reg_space(0x%08x)\n", ch + 1, val);
417 	val = readl(base + reg_en);
418 	DRM_DEBUG_DRIVER("[rdma%d]: reg_en(0x%08x)\n", ch + 1, val);
419 }
420 
421 static void ade_clip_dump_regs(void __iomem *base, u32 ch)
422 {
423 	u32 val;
424 
425 	val = ade_read_reload_bit(base, CLIP_OFST + ch);
426 	DRM_DEBUG_DRIVER("[clip%d]: reload(%d)\n", ch + 1, val);
427 	val = readl(base + ADE_CLIP_DISABLE(ch));
428 	DRM_DEBUG_DRIVER("[clip%d]: reg_clip_disable(0x%08x)\n", ch + 1, val);
429 	val = readl(base + ADE_CLIP_SIZE0(ch));
430 	DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size0(0x%08x)\n", ch + 1, val);
431 	val = readl(base + ADE_CLIP_SIZE1(ch));
432 	DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size1(0x%08x)\n", ch + 1, val);
433 }
434 
435 static void ade_compositor_routing_dump_regs(void __iomem *base, u32 ch)
436 {
437 	u8 ovly_ch = 0; /* TODO: Only primary plane now */
438 	u32 val;
439 
440 	val = readl(base + ADE_OVLY_CH_XY0(ovly_ch));
441 	DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy0(0x%08x)\n", ovly_ch, val);
442 	val = readl(base + ADE_OVLY_CH_XY1(ovly_ch));
443 	DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy1(0x%08x)\n", ovly_ch, val);
444 	val = readl(base + ADE_OVLY_CH_CTL(ovly_ch));
445 	DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_ctl(0x%08x)\n", ovly_ch, val);
446 }
447 
448 static void ade_dump_overlay_compositor_regs(void __iomem *base, u32 comp)
449 {
450 	u32 val;
451 
452 	val = ade_read_reload_bit(base, OVLY_OFST + comp);
453 	DRM_DEBUG_DRIVER("[overlay%d]: reload(%d)\n", comp + 1, val);
454 	writel(ADE_ENABLE, base + ADE_OVLYX_CTL(comp));
455 	DRM_DEBUG_DRIVER("[overlay%d]: reg_ctl(0x%08x)\n", comp + 1, val);
456 	val = readl(base + ADE_OVLY_CTL);
457 	DRM_DEBUG_DRIVER("ovly_ctl(0x%08x)\n", val);
458 }
459 
460 static void ade_dump_regs(void __iomem *base)
461 {
462 	u32 i;
463 
464 	/* dump channel regs */
465 	for (i = 0; i < ADE_CH_NUM; i++) {
466 		/* dump rdma regs */
467 		ade_rdma_dump_regs(base, i);
468 
469 		/* dump clip regs */
470 		ade_clip_dump_regs(base, i);
471 
472 		/* dump compositor routing regs */
473 		ade_compositor_routing_dump_regs(base, i);
474 	}
475 
476 	/* dump overlay compositor regs */
477 	ade_dump_overlay_compositor_regs(base, OUT_OVLY);
478 }
479 #else
480 static void ade_dump_regs(void __iomem *base) { }
481 #endif
482 
483 static void ade_crtc_atomic_enable(struct drm_crtc *crtc,
484 				   struct drm_crtc_state *old_state)
485 {
486 	struct ade_crtc *acrtc = to_ade_crtc(crtc);
487 	struct ade_hw_ctx *ctx = acrtc->ctx;
488 	int ret;
489 
490 	if (acrtc->enable)
491 		return;
492 
493 	if (!ctx->power_on) {
494 		ret = ade_power_up(ctx);
495 		if (ret)
496 			return;
497 	}
498 
499 	ade_set_medianoc_qos(acrtc);
500 	ade_display_enable(acrtc);
501 	ade_dump_regs(ctx->base);
502 	drm_crtc_vblank_on(crtc);
503 	acrtc->enable = true;
504 }
505 
506 static void ade_crtc_atomic_disable(struct drm_crtc *crtc,
507 				    struct drm_crtc_state *old_state)
508 {
509 	struct ade_crtc *acrtc = to_ade_crtc(crtc);
510 	struct ade_hw_ctx *ctx = acrtc->ctx;
511 
512 	if (!acrtc->enable)
513 		return;
514 
515 	drm_crtc_vblank_off(crtc);
516 	ade_power_down(ctx);
517 	acrtc->enable = false;
518 }
519 
520 static void ade_crtc_mode_set_nofb(struct drm_crtc *crtc)
521 {
522 	struct ade_crtc *acrtc = to_ade_crtc(crtc);
523 	struct ade_hw_ctx *ctx = acrtc->ctx;
524 	struct drm_display_mode *mode = &crtc->state->mode;
525 	struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode;
526 
527 	if (!ctx->power_on)
528 		(void)ade_power_up(ctx);
529 	ade_ldi_set_mode(acrtc, mode, adj_mode);
530 }
531 
532 static void ade_crtc_atomic_begin(struct drm_crtc *crtc,
533 				  struct drm_crtc_state *old_state)
534 {
535 	struct ade_crtc *acrtc = to_ade_crtc(crtc);
536 	struct ade_hw_ctx *ctx = acrtc->ctx;
537 	struct drm_display_mode *mode = &crtc->state->mode;
538 	struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode;
539 
540 	if (!ctx->power_on)
541 		(void)ade_power_up(ctx);
542 	ade_ldi_set_mode(acrtc, mode, adj_mode);
543 }
544 
545 static void ade_crtc_atomic_flush(struct drm_crtc *crtc,
546 				  struct drm_crtc_state *old_state)
547 
548 {
549 	struct ade_crtc *acrtc = to_ade_crtc(crtc);
550 	struct ade_hw_ctx *ctx = acrtc->ctx;
551 	struct drm_pending_vblank_event *event = crtc->state->event;
552 	void __iomem *base = ctx->base;
553 
554 	/* only crtc is enabled regs take effect */
555 	if (acrtc->enable) {
556 		ade_dump_regs(base);
557 		/* flush ade registers */
558 		writel(ADE_ENABLE, base + ADE_EN);
559 	}
560 
561 	if (event) {
562 		crtc->state->event = NULL;
563 
564 		spin_lock_irq(&crtc->dev->event_lock);
565 		if (drm_crtc_vblank_get(crtc) == 0)
566 			drm_crtc_arm_vblank_event(crtc, event);
567 		else
568 			drm_crtc_send_vblank_event(crtc, event);
569 		spin_unlock_irq(&crtc->dev->event_lock);
570 	}
571 }
572 
573 static const struct drm_crtc_helper_funcs ade_crtc_helper_funcs = {
574 	.mode_fixup	= ade_crtc_mode_fixup,
575 	.mode_set_nofb	= ade_crtc_mode_set_nofb,
576 	.atomic_begin	= ade_crtc_atomic_begin,
577 	.atomic_flush	= ade_crtc_atomic_flush,
578 	.atomic_enable	= ade_crtc_atomic_enable,
579 	.atomic_disable	= ade_crtc_atomic_disable,
580 };
581 
582 static const struct drm_crtc_funcs ade_crtc_funcs = {
583 	.destroy	= drm_crtc_cleanup,
584 	.set_config	= drm_atomic_helper_set_config,
585 	.page_flip	= drm_atomic_helper_page_flip,
586 	.reset		= drm_atomic_helper_crtc_reset,
587 	.atomic_duplicate_state	= drm_atomic_helper_crtc_duplicate_state,
588 	.atomic_destroy_state	= drm_atomic_helper_crtc_destroy_state,
589 	.enable_vblank	= ade_crtc_enable_vblank,
590 	.disable_vblank	= ade_crtc_disable_vblank,
591 };
592 
593 static int ade_crtc_init(struct drm_device *dev, struct drm_crtc *crtc,
594 			 struct drm_plane *plane)
595 {
596 	struct device_node *port;
597 	int ret;
598 
599 	/* set crtc port so that
600 	 * drm_of_find_possible_crtcs call works
601 	 */
602 	port = of_get_child_by_name(dev->dev->of_node, "port");
603 	if (!port) {
604 		DRM_ERROR("no port node found in %pOF\n", dev->dev->of_node);
605 		return -EINVAL;
606 	}
607 	of_node_put(port);
608 	crtc->port = port;
609 
610 	ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
611 					&ade_crtc_funcs, NULL);
612 	if (ret) {
613 		DRM_ERROR("failed to init crtc.\n");
614 		return ret;
615 	}
616 
617 	drm_crtc_helper_add(crtc, &ade_crtc_helper_funcs);
618 
619 	return 0;
620 }
621 
622 static void ade_rdma_set(void __iomem *base, struct drm_framebuffer *fb,
623 			 u32 ch, u32 y, u32 in_h, u32 fmt)
624 {
625 	struct drm_gem_cma_object *obj = drm_fb_cma_get_gem_obj(fb, 0);
626 	struct drm_format_name_buf format_name;
627 	u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en;
628 	u32 stride = fb->pitches[0];
629 	u32 addr = (u32)obj->paddr + y * stride;
630 
631 	DRM_DEBUG_DRIVER("rdma%d: (y=%d, height=%d), stride=%d, paddr=0x%x\n",
632 			 ch + 1, y, in_h, stride, (u32)obj->paddr);
633 	DRM_DEBUG_DRIVER("addr=0x%x, fb:%dx%d, pixel_format=%d(%s)\n",
634 			 addr, fb->width, fb->height, fmt,
635 			 drm_get_format_name(fb->format->format, &format_name));
636 
637 	/* get reg offset */
638 	reg_ctrl = RD_CH_CTRL(ch);
639 	reg_addr = RD_CH_ADDR(ch);
640 	reg_size = RD_CH_SIZE(ch);
641 	reg_stride = RD_CH_STRIDE(ch);
642 	reg_space = RD_CH_SPACE(ch);
643 	reg_en = RD_CH_EN(ch);
644 
645 	/*
646 	 * TODO: set rotation
647 	 */
648 	writel((fmt << 16) & 0x1f0000, base + reg_ctrl);
649 	writel(addr, base + reg_addr);
650 	writel((in_h << 16) | stride, base + reg_size);
651 	writel(stride, base + reg_stride);
652 	writel(in_h * stride, base + reg_space);
653 	writel(ADE_ENABLE, base + reg_en);
654 	ade_update_reload_bit(base, RDMA_OFST + ch, 0);
655 }
656 
657 static void ade_rdma_disable(void __iomem *base, u32 ch)
658 {
659 	u32 reg_en;
660 
661 	/* get reg offset */
662 	reg_en = RD_CH_EN(ch);
663 	writel(0, base + reg_en);
664 	ade_update_reload_bit(base, RDMA_OFST + ch, 1);
665 }
666 
667 static void ade_clip_set(void __iomem *base, u32 ch, u32 fb_w, u32 x,
668 			 u32 in_w, u32 in_h)
669 {
670 	u32 disable_val;
671 	u32 clip_left;
672 	u32 clip_right;
673 
674 	/*
675 	 * clip width, no need to clip height
676 	 */
677 	if (fb_w == in_w) { /* bypass */
678 		disable_val = 1;
679 		clip_left = 0;
680 		clip_right = 0;
681 	} else {
682 		disable_val = 0;
683 		clip_left = x;
684 		clip_right = fb_w - (x + in_w) - 1;
685 	}
686 
687 	DRM_DEBUG_DRIVER("clip%d: clip_left=%d, clip_right=%d\n",
688 			 ch + 1, clip_left, clip_right);
689 
690 	writel(disable_val, base + ADE_CLIP_DISABLE(ch));
691 	writel((fb_w - 1) << 16 | (in_h - 1), base + ADE_CLIP_SIZE0(ch));
692 	writel(clip_left << 16 | clip_right, base + ADE_CLIP_SIZE1(ch));
693 	ade_update_reload_bit(base, CLIP_OFST + ch, 0);
694 }
695 
696 static void ade_clip_disable(void __iomem *base, u32 ch)
697 {
698 	writel(1, base + ADE_CLIP_DISABLE(ch));
699 	ade_update_reload_bit(base, CLIP_OFST + ch, 1);
700 }
701 
702 static bool has_Alpha_channel(int format)
703 {
704 	switch (format) {
705 	case ADE_ARGB_8888:
706 	case ADE_ABGR_8888:
707 	case ADE_RGBA_8888:
708 	case ADE_BGRA_8888:
709 		return true;
710 	default:
711 		return false;
712 	}
713 }
714 
715 static void ade_get_blending_params(u32 fmt, u8 glb_alpha, u8 *alp_mode,
716 				    u8 *alp_sel, u8 *under_alp_sel)
717 {
718 	bool has_alpha = has_Alpha_channel(fmt);
719 
720 	/*
721 	 * get alp_mode
722 	 */
723 	if (has_alpha && glb_alpha < 255)
724 		*alp_mode = ADE_ALP_PIXEL_AND_GLB;
725 	else if (has_alpha)
726 		*alp_mode = ADE_ALP_PIXEL;
727 	else
728 		*alp_mode = ADE_ALP_GLOBAL;
729 
730 	/*
731 	 * get alp sel
732 	 */
733 	*alp_sel = ADE_ALP_MUL_COEFF_3; /* 1 */
734 	*under_alp_sel = ADE_ALP_MUL_COEFF_2; /* 0 */
735 }
736 
737 static void ade_compositor_routing_set(void __iomem *base, u8 ch,
738 				       u32 x0, u32 y0,
739 				       u32 in_w, u32 in_h, u32 fmt)
740 {
741 	u8 ovly_ch = 0; /* TODO: This is the zpos, only one plane now */
742 	u8 glb_alpha = 255;
743 	u32 x1 = x0 + in_w - 1;
744 	u32 y1 = y0 + in_h - 1;
745 	u32 val;
746 	u8 alp_sel;
747 	u8 under_alp_sel;
748 	u8 alp_mode;
749 
750 	ade_get_blending_params(fmt, glb_alpha, &alp_mode, &alp_sel,
751 				&under_alp_sel);
752 
753 	/* overlay routing setting
754 	 */
755 	writel(x0 << 16 | y0, base + ADE_OVLY_CH_XY0(ovly_ch));
756 	writel(x1 << 16 | y1, base + ADE_OVLY_CH_XY1(ovly_ch));
757 	val = (ch + 1) << CH_SEL_OFST | BIT(CH_EN_OFST) |
758 		alp_sel << CH_ALP_SEL_OFST |
759 		under_alp_sel << CH_UNDER_ALP_SEL_OFST |
760 		glb_alpha << CH_ALP_GBL_OFST |
761 		alp_mode << CH_ALP_MODE_OFST;
762 	writel(val, base + ADE_OVLY_CH_CTL(ovly_ch));
763 	/* connect this plane/channel to overlay2 compositor */
764 	ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch),
765 			CH_OVLY_SEL_MASK, CH_OVLY_SEL_VAL(OUT_OVLY));
766 }
767 
768 static void ade_compositor_routing_disable(void __iomem *base, u32 ch)
769 {
770 	u8 ovly_ch = 0; /* TODO: Only primary plane now */
771 
772 	/* disable this plane/channel */
773 	ade_update_bits(base + ADE_OVLY_CH_CTL(ovly_ch), CH_EN_OFST,
774 			MASK(1), 0);
775 	/* dis-connect this plane/channel of overlay2 compositor */
776 	ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch),
777 			CH_OVLY_SEL_MASK, 0);
778 }
779 
780 /*
781  * Typicaly, a channel looks like: DMA-->clip-->scale-->ctrans-->compositor
782  */
783 static void ade_update_channel(struct ade_plane *aplane,
784 			       struct drm_framebuffer *fb, int crtc_x,
785 			       int crtc_y, unsigned int crtc_w,
786 			       unsigned int crtc_h, u32 src_x,
787 			       u32 src_y, u32 src_w, u32 src_h)
788 {
789 	struct ade_hw_ctx *ctx = aplane->ctx;
790 	void __iomem *base = ctx->base;
791 	u32 fmt = ade_get_format(fb->format->format);
792 	u32 ch = aplane->ch;
793 	u32 in_w;
794 	u32 in_h;
795 
796 	DRM_DEBUG_DRIVER("channel%d: src:(%d, %d)-%dx%d, crtc:(%d, %d)-%dx%d",
797 			 ch + 1, src_x, src_y, src_w, src_h,
798 			 crtc_x, crtc_y, crtc_w, crtc_h);
799 
800 	/* 1) DMA setting */
801 	in_w = src_w;
802 	in_h = src_h;
803 	ade_rdma_set(base, fb, ch, src_y, in_h, fmt);
804 
805 	/* 2) clip setting */
806 	ade_clip_set(base, ch, fb->width, src_x, in_w, in_h);
807 
808 	/* 3) TODO: scale setting for overlay planes */
809 
810 	/* 4) TODO: ctran/csc setting for overlay planes */
811 
812 	/* 5) compositor routing setting */
813 	ade_compositor_routing_set(base, ch, crtc_x, crtc_y, in_w, in_h, fmt);
814 }
815 
816 static void ade_disable_channel(struct ade_plane *aplane)
817 {
818 	struct ade_hw_ctx *ctx = aplane->ctx;
819 	void __iomem *base = ctx->base;
820 	u32 ch = aplane->ch;
821 
822 	DRM_DEBUG_DRIVER("disable channel%d\n", ch + 1);
823 
824 	/* disable read DMA */
825 	ade_rdma_disable(base, ch);
826 
827 	/* disable clip */
828 	ade_clip_disable(base, ch);
829 
830 	/* disable compositor routing */
831 	ade_compositor_routing_disable(base, ch);
832 }
833 
834 static int ade_plane_atomic_check(struct drm_plane *plane,
835 				  struct drm_plane_state *state)
836 {
837 	struct drm_framebuffer *fb = state->fb;
838 	struct drm_crtc *crtc = state->crtc;
839 	struct drm_crtc_state *crtc_state;
840 	u32 src_x = state->src_x >> 16;
841 	u32 src_y = state->src_y >> 16;
842 	u32 src_w = state->src_w >> 16;
843 	u32 src_h = state->src_h >> 16;
844 	int crtc_x = state->crtc_x;
845 	int crtc_y = state->crtc_y;
846 	u32 crtc_w = state->crtc_w;
847 	u32 crtc_h = state->crtc_h;
848 	u32 fmt;
849 
850 	if (!crtc || !fb)
851 		return 0;
852 
853 	fmt = ade_get_format(fb->format->format);
854 	if (fmt == ADE_FORMAT_UNSUPPORT)
855 		return -EINVAL;
856 
857 	crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
858 	if (IS_ERR(crtc_state))
859 		return PTR_ERR(crtc_state);
860 
861 	if (src_w != crtc_w || src_h != crtc_h) {
862 		DRM_ERROR("Scale not support!!!\n");
863 		return -EINVAL;
864 	}
865 
866 	if (src_x + src_w > fb->width ||
867 	    src_y + src_h > fb->height)
868 		return -EINVAL;
869 
870 	if (crtc_x < 0 || crtc_y < 0)
871 		return -EINVAL;
872 
873 	if (crtc_x + crtc_w > crtc_state->adjusted_mode.hdisplay ||
874 	    crtc_y + crtc_h > crtc_state->adjusted_mode.vdisplay)
875 		return -EINVAL;
876 
877 	return 0;
878 }
879 
880 static void ade_plane_atomic_update(struct drm_plane *plane,
881 				    struct drm_plane_state *old_state)
882 {
883 	struct drm_plane_state	*state	= plane->state;
884 	struct ade_plane *aplane = to_ade_plane(plane);
885 
886 	ade_update_channel(aplane, state->fb, state->crtc_x, state->crtc_y,
887 			   state->crtc_w, state->crtc_h,
888 			   state->src_x >> 16, state->src_y >> 16,
889 			   state->src_w >> 16, state->src_h >> 16);
890 }
891 
892 static void ade_plane_atomic_disable(struct drm_plane *plane,
893 				     struct drm_plane_state *old_state)
894 {
895 	struct ade_plane *aplane = to_ade_plane(plane);
896 
897 	ade_disable_channel(aplane);
898 }
899 
900 static const struct drm_plane_helper_funcs ade_plane_helper_funcs = {
901 	.atomic_check = ade_plane_atomic_check,
902 	.atomic_update = ade_plane_atomic_update,
903 	.atomic_disable = ade_plane_atomic_disable,
904 };
905 
906 static struct drm_plane_funcs ade_plane_funcs = {
907 	.update_plane	= drm_atomic_helper_update_plane,
908 	.disable_plane	= drm_atomic_helper_disable_plane,
909 	.destroy = drm_plane_cleanup,
910 	.reset = drm_atomic_helper_plane_reset,
911 	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
912 	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
913 };
914 
915 static int ade_plane_init(struct drm_device *dev, struct ade_plane *aplane,
916 			  enum drm_plane_type type)
917 {
918 	const u32 *fmts;
919 	u32 fmts_cnt;
920 	int ret = 0;
921 
922 	/* get  properties */
923 	fmts_cnt = ade_get_channel_formats(aplane->ch, &fmts);
924 	if (ret)
925 		return ret;
926 
927 	ret = drm_universal_plane_init(dev, &aplane->base, 1, &ade_plane_funcs,
928 				       fmts, fmts_cnt, NULL, type, NULL);
929 	if (ret) {
930 		DRM_ERROR("fail to init plane, ch=%d\n", aplane->ch);
931 		return ret;
932 	}
933 
934 	drm_plane_helper_add(&aplane->base, &ade_plane_helper_funcs);
935 
936 	return 0;
937 }
938 
939 static int ade_dts_parse(struct platform_device *pdev, struct ade_hw_ctx *ctx)
940 {
941 	struct resource *res;
942 	struct device *dev = &pdev->dev;
943 	struct device_node *np = pdev->dev.of_node;
944 
945 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
946 	ctx->base = devm_ioremap_resource(dev, res);
947 	if (IS_ERR(ctx->base)) {
948 		DRM_ERROR("failed to remap ade io base\n");
949 		return  PTR_ERR(ctx->base);
950 	}
951 
952 	ctx->reset = devm_reset_control_get(dev, NULL);
953 	if (IS_ERR(ctx->reset))
954 		return PTR_ERR(ctx->reset);
955 
956 	ctx->noc_regmap =
957 		syscon_regmap_lookup_by_phandle(np, "hisilicon,noc-syscon");
958 	if (IS_ERR(ctx->noc_regmap)) {
959 		DRM_ERROR("failed to get noc regmap\n");
960 		return PTR_ERR(ctx->noc_regmap);
961 	}
962 
963 	ctx->irq = platform_get_irq(pdev, 0);
964 	if (ctx->irq < 0) {
965 		DRM_ERROR("failed to get irq\n");
966 		return -ENODEV;
967 	}
968 
969 	ctx->ade_core_clk = devm_clk_get(dev, "clk_ade_core");
970 	if (IS_ERR(ctx->ade_core_clk)) {
971 		DRM_ERROR("failed to parse clk ADE_CORE\n");
972 		return PTR_ERR(ctx->ade_core_clk);
973 	}
974 
975 	ctx->media_noc_clk = devm_clk_get(dev, "clk_codec_jpeg");
976 	if (IS_ERR(ctx->media_noc_clk)) {
977 		DRM_ERROR("failed to parse clk CODEC_JPEG\n");
978 		return PTR_ERR(ctx->media_noc_clk);
979 	}
980 
981 	ctx->ade_pix_clk = devm_clk_get(dev, "clk_ade_pix");
982 	if (IS_ERR(ctx->ade_pix_clk)) {
983 		DRM_ERROR("failed to parse clk ADE_PIX\n");
984 		return PTR_ERR(ctx->ade_pix_clk);
985 	}
986 
987 	return 0;
988 }
989 
990 static int ade_drm_init(struct platform_device *pdev)
991 {
992 	struct drm_device *dev = platform_get_drvdata(pdev);
993 	struct ade_data *ade;
994 	struct ade_hw_ctx *ctx;
995 	struct ade_crtc *acrtc;
996 	struct ade_plane *aplane;
997 	enum drm_plane_type type;
998 	int ret;
999 	int i;
1000 
1001 	ade = devm_kzalloc(dev->dev, sizeof(*ade), GFP_KERNEL);
1002 	if (!ade) {
1003 		DRM_ERROR("failed to alloc ade_data\n");
1004 		return -ENOMEM;
1005 	}
1006 	platform_set_drvdata(pdev, ade);
1007 
1008 	ctx = &ade->ctx;
1009 	acrtc = &ade->acrtc;
1010 	acrtc->ctx = ctx;
1011 	acrtc->out_format = LDI_OUT_RGB_888;
1012 
1013 	ret = ade_dts_parse(pdev, ctx);
1014 	if (ret)
1015 		return ret;
1016 
1017 	/*
1018 	 * plane init
1019 	 * TODO: Now only support primary plane, overlay planes
1020 	 * need to do.
1021 	 */
1022 	for (i = 0; i < ADE_CH_NUM; i++) {
1023 		aplane = &ade->aplane[i];
1024 		aplane->ch = i;
1025 		aplane->ctx = ctx;
1026 		type = i == PRIMARY_CH ? DRM_PLANE_TYPE_PRIMARY :
1027 			DRM_PLANE_TYPE_OVERLAY;
1028 
1029 		ret = ade_plane_init(dev, aplane, type);
1030 		if (ret)
1031 			return ret;
1032 	}
1033 
1034 	/* crtc init */
1035 	ret = ade_crtc_init(dev, &acrtc->base, &ade->aplane[PRIMARY_CH].base);
1036 	if (ret)
1037 		return ret;
1038 
1039 	/* vblank irq init */
1040 	ret = devm_request_irq(dev->dev, ctx->irq, ade_irq_handler,
1041 			       IRQF_SHARED, dev->driver->name, acrtc);
1042 	if (ret)
1043 		return ret;
1044 
1045 	return 0;
1046 }
1047 
1048 static void ade_drm_cleanup(struct platform_device *pdev)
1049 {
1050 }
1051 
1052 const struct kirin_dc_ops ade_dc_ops = {
1053 	.init = ade_drm_init,
1054 	.cleanup = ade_drm_cleanup
1055 };
1056