1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Hisilicon Hi6220 SoC ADE(Advanced Display Engine)'s crtc&plane driver 4 * 5 * Copyright (c) 2016 Linaro Limited. 6 * Copyright (c) 2014-2016 Hisilicon Limited. 7 * 8 * Author: 9 * Xinliang Liu <z.liuxinliang@hisilicon.com> 10 * Xinliang Liu <xinliang.liu@linaro.org> 11 * Xinwei Kong <kong.kongxinwei@hisilicon.com> 12 */ 13 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <video/display_timing.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/regmap.h> 19 #include <linux/reset.h> 20 21 #include <drm/drmP.h> 22 #include <drm/drm_atomic.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_crtc.h> 25 #include <drm/drm_fb_cma_helper.h> 26 #include <drm/drm_gem_cma_helper.h> 27 #include <drm/drm_plane_helper.h> 28 #include <drm/drm_probe_helper.h> 29 30 #include "kirin_drm_drv.h" 31 #include "kirin_ade_reg.h" 32 33 #define PRIMARY_CH ADE_CH1 /* primary plane */ 34 #define OUT_OVLY ADE_OVLY2 /* output overlay compositor */ 35 #define ADE_DEBUG 1 36 37 #define to_ade_crtc(crtc) \ 38 container_of(crtc, struct ade_crtc, base) 39 40 #define to_ade_plane(plane) \ 41 container_of(plane, struct ade_plane, base) 42 43 struct ade_hw_ctx { 44 void __iomem *base; 45 struct regmap *noc_regmap; 46 struct clk *ade_core_clk; 47 struct clk *media_noc_clk; 48 struct clk *ade_pix_clk; 49 struct reset_control *reset; 50 bool power_on; 51 int irq; 52 }; 53 54 struct ade_crtc { 55 struct drm_crtc base; 56 struct ade_hw_ctx *ctx; 57 bool enable; 58 u32 out_format; 59 }; 60 61 struct ade_plane { 62 struct drm_plane base; 63 void *ctx; 64 u8 ch; /* channel */ 65 }; 66 67 struct ade_data { 68 struct ade_crtc acrtc; 69 struct ade_plane aplane[ADE_CH_NUM]; 70 struct ade_hw_ctx ctx; 71 }; 72 73 /* ade-format info: */ 74 struct ade_format { 75 u32 pixel_format; 76 enum ade_fb_format ade_format; 77 }; 78 79 static const struct ade_format ade_formats[] = { 80 /* 16bpp RGB: */ 81 { DRM_FORMAT_RGB565, ADE_RGB_565 }, 82 { DRM_FORMAT_BGR565, ADE_BGR_565 }, 83 /* 24bpp RGB: */ 84 { DRM_FORMAT_RGB888, ADE_RGB_888 }, 85 { DRM_FORMAT_BGR888, ADE_BGR_888 }, 86 /* 32bpp [A]RGB: */ 87 { DRM_FORMAT_XRGB8888, ADE_XRGB_8888 }, 88 { DRM_FORMAT_XBGR8888, ADE_XBGR_8888 }, 89 { DRM_FORMAT_RGBA8888, ADE_RGBA_8888 }, 90 { DRM_FORMAT_BGRA8888, ADE_BGRA_8888 }, 91 { DRM_FORMAT_ARGB8888, ADE_ARGB_8888 }, 92 { DRM_FORMAT_ABGR8888, ADE_ABGR_8888 }, 93 }; 94 95 static const u32 channel_formats1[] = { 96 /* channel 1,2,3,4 */ 97 DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888, 98 DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, 99 DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888, 100 DRM_FORMAT_ABGR8888 101 }; 102 103 u32 ade_get_channel_formats(u8 ch, const u32 **formats) 104 { 105 switch (ch) { 106 case ADE_CH1: 107 *formats = channel_formats1; 108 return ARRAY_SIZE(channel_formats1); 109 default: 110 DRM_ERROR("no this channel %d\n", ch); 111 *formats = NULL; 112 return 0; 113 } 114 } 115 116 /* convert from fourcc format to ade format */ 117 static u32 ade_get_format(u32 pixel_format) 118 { 119 int i; 120 121 for (i = 0; i < ARRAY_SIZE(ade_formats); i++) 122 if (ade_formats[i].pixel_format == pixel_format) 123 return ade_formats[i].ade_format; 124 125 /* not found */ 126 DRM_ERROR("Not found pixel format!!fourcc_format= %d\n", 127 pixel_format); 128 return ADE_FORMAT_UNSUPPORT; 129 } 130 131 static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val) 132 { 133 u32 bit_ofst, reg_num; 134 135 bit_ofst = bit_num % 32; 136 reg_num = bit_num / 32; 137 138 ade_update_bits(base + ADE_RELOAD_DIS(reg_num), bit_ofst, 139 MASK(1), !!val); 140 } 141 142 static u32 ade_read_reload_bit(void __iomem *base, u32 bit_num) 143 { 144 u32 tmp, bit_ofst, reg_num; 145 146 bit_ofst = bit_num % 32; 147 reg_num = bit_num / 32; 148 149 tmp = readl(base + ADE_RELOAD_DIS(reg_num)); 150 return !!(BIT(bit_ofst) & tmp); 151 } 152 153 static void ade_init(struct ade_hw_ctx *ctx) 154 { 155 void __iomem *base = ctx->base; 156 157 /* enable clk gate */ 158 ade_update_bits(base + ADE_CTRL1, AUTO_CLK_GATE_EN_OFST, 159 AUTO_CLK_GATE_EN, ADE_ENABLE); 160 /* clear overlay */ 161 writel(0, base + ADE_OVLY1_TRANS_CFG); 162 writel(0, base + ADE_OVLY_CTL); 163 writel(0, base + ADE_OVLYX_CTL(OUT_OVLY)); 164 /* clear reset and reload regs */ 165 writel(MASK(32), base + ADE_SOFT_RST_SEL(0)); 166 writel(MASK(32), base + ADE_SOFT_RST_SEL(1)); 167 writel(MASK(32), base + ADE_RELOAD_DIS(0)); 168 writel(MASK(32), base + ADE_RELOAD_DIS(1)); 169 /* 170 * for video mode, all the ade registers should 171 * become effective at frame end. 172 */ 173 ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST, 174 FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND); 175 } 176 177 static bool ade_crtc_mode_fixup(struct drm_crtc *crtc, 178 const struct drm_display_mode *mode, 179 struct drm_display_mode *adjusted_mode) 180 { 181 struct ade_crtc *acrtc = to_ade_crtc(crtc); 182 struct ade_hw_ctx *ctx = acrtc->ctx; 183 184 adjusted_mode->clock = 185 clk_round_rate(ctx->ade_pix_clk, mode->clock * 1000) / 1000; 186 return true; 187 } 188 189 190 static void ade_set_pix_clk(struct ade_hw_ctx *ctx, 191 struct drm_display_mode *mode, 192 struct drm_display_mode *adj_mode) 193 { 194 u32 clk_Hz = mode->clock * 1000; 195 int ret; 196 197 /* 198 * Success should be guaranteed in mode_valid call back, 199 * so failure shouldn't happen here 200 */ 201 ret = clk_set_rate(ctx->ade_pix_clk, clk_Hz); 202 if (ret) 203 DRM_ERROR("failed to set pixel clk %dHz (%d)\n", clk_Hz, ret); 204 adj_mode->clock = clk_get_rate(ctx->ade_pix_clk) / 1000; 205 } 206 207 static void ade_ldi_set_mode(struct ade_crtc *acrtc, 208 struct drm_display_mode *mode, 209 struct drm_display_mode *adj_mode) 210 { 211 struct ade_hw_ctx *ctx = acrtc->ctx; 212 void __iomem *base = ctx->base; 213 u32 width = mode->hdisplay; 214 u32 height = mode->vdisplay; 215 u32 hfp, hbp, hsw, vfp, vbp, vsw; 216 u32 plr_flags; 217 218 plr_flags = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? FLAG_NVSYNC : 0; 219 plr_flags |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? FLAG_NHSYNC : 0; 220 hfp = mode->hsync_start - mode->hdisplay; 221 hbp = mode->htotal - mode->hsync_end; 222 hsw = mode->hsync_end - mode->hsync_start; 223 vfp = mode->vsync_start - mode->vdisplay; 224 vbp = mode->vtotal - mode->vsync_end; 225 vsw = mode->vsync_end - mode->vsync_start; 226 if (vsw > 15) { 227 DRM_DEBUG_DRIVER("vsw exceeded 15\n"); 228 vsw = 15; 229 } 230 231 writel((hbp << HBP_OFST) | hfp, base + LDI_HRZ_CTRL0); 232 /* the configured value is actual value - 1 */ 233 writel(hsw - 1, base + LDI_HRZ_CTRL1); 234 writel((vbp << VBP_OFST) | vfp, base + LDI_VRT_CTRL0); 235 /* the configured value is actual value - 1 */ 236 writel(vsw - 1, base + LDI_VRT_CTRL1); 237 /* the configured value is actual value - 1 */ 238 writel(((height - 1) << VSIZE_OFST) | (width - 1), 239 base + LDI_DSP_SIZE); 240 writel(plr_flags, base + LDI_PLR_CTRL); 241 242 /* set overlay compositor output size */ 243 writel(((width - 1) << OUTPUT_XSIZE_OFST) | (height - 1), 244 base + ADE_OVLY_OUTPUT_SIZE(OUT_OVLY)); 245 246 /* ctran6 setting */ 247 writel(CTRAN_BYPASS_ON, base + ADE_CTRAN_DIS(ADE_CTRAN6)); 248 /* the configured value is actual value - 1 */ 249 writel(width * height - 1, base + ADE_CTRAN_IMAGE_SIZE(ADE_CTRAN6)); 250 ade_update_reload_bit(base, CTRAN_OFST + ADE_CTRAN6, 0); 251 252 ade_set_pix_clk(ctx, mode, adj_mode); 253 254 DRM_DEBUG_DRIVER("set mode: %dx%d\n", width, height); 255 } 256 257 static int ade_power_up(struct ade_hw_ctx *ctx) 258 { 259 int ret; 260 261 ret = clk_prepare_enable(ctx->media_noc_clk); 262 if (ret) { 263 DRM_ERROR("failed to enable media_noc_clk (%d)\n", ret); 264 return ret; 265 } 266 267 ret = reset_control_deassert(ctx->reset); 268 if (ret) { 269 DRM_ERROR("failed to deassert reset\n"); 270 return ret; 271 } 272 273 ret = clk_prepare_enable(ctx->ade_core_clk); 274 if (ret) { 275 DRM_ERROR("failed to enable ade_core_clk (%d)\n", ret); 276 return ret; 277 } 278 279 ade_init(ctx); 280 ctx->power_on = true; 281 return 0; 282 } 283 284 static void ade_power_down(struct ade_hw_ctx *ctx) 285 { 286 void __iomem *base = ctx->base; 287 288 writel(ADE_DISABLE, base + LDI_CTRL); 289 /* dsi pixel off */ 290 writel(DSI_PCLK_OFF, base + LDI_HDMI_DSI_GT); 291 292 clk_disable_unprepare(ctx->ade_core_clk); 293 reset_control_assert(ctx->reset); 294 clk_disable_unprepare(ctx->media_noc_clk); 295 ctx->power_on = false; 296 } 297 298 static void ade_set_medianoc_qos(struct ade_crtc *acrtc) 299 { 300 struct ade_hw_ctx *ctx = acrtc->ctx; 301 struct regmap *map = ctx->noc_regmap; 302 303 regmap_update_bits(map, ADE0_QOSGENERATOR_MODE, 304 QOSGENERATOR_MODE_MASK, BYPASS_MODE); 305 regmap_update_bits(map, ADE0_QOSGENERATOR_EXTCONTROL, 306 SOCKET_QOS_EN, SOCKET_QOS_EN); 307 308 regmap_update_bits(map, ADE1_QOSGENERATOR_MODE, 309 QOSGENERATOR_MODE_MASK, BYPASS_MODE); 310 regmap_update_bits(map, ADE1_QOSGENERATOR_EXTCONTROL, 311 SOCKET_QOS_EN, SOCKET_QOS_EN); 312 } 313 314 static int ade_crtc_enable_vblank(struct drm_crtc *crtc) 315 { 316 struct ade_crtc *acrtc = to_ade_crtc(crtc); 317 struct ade_hw_ctx *ctx = acrtc->ctx; 318 void __iomem *base = ctx->base; 319 320 if (!ctx->power_on) 321 (void)ade_power_up(ctx); 322 323 ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST, 324 MASK(1), 1); 325 326 return 0; 327 } 328 329 static void ade_crtc_disable_vblank(struct drm_crtc *crtc) 330 { 331 struct ade_crtc *acrtc = to_ade_crtc(crtc); 332 struct ade_hw_ctx *ctx = acrtc->ctx; 333 void __iomem *base = ctx->base; 334 335 if (!ctx->power_on) { 336 DRM_ERROR("power is down! vblank disable fail\n"); 337 return; 338 } 339 340 ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST, 341 MASK(1), 0); 342 } 343 344 static irqreturn_t ade_irq_handler(int irq, void *data) 345 { 346 struct ade_crtc *acrtc = data; 347 struct ade_hw_ctx *ctx = acrtc->ctx; 348 struct drm_crtc *crtc = &acrtc->base; 349 void __iomem *base = ctx->base; 350 u32 status; 351 352 status = readl(base + LDI_MSK_INT); 353 DRM_DEBUG_VBL("LDI IRQ: status=0x%X\n", status); 354 355 /* vblank irq */ 356 if (status & BIT(FRAME_END_INT_EN_OFST)) { 357 ade_update_bits(base + LDI_INT_CLR, FRAME_END_INT_EN_OFST, 358 MASK(1), 1); 359 drm_crtc_handle_vblank(crtc); 360 } 361 362 return IRQ_HANDLED; 363 } 364 365 static void ade_display_enable(struct ade_crtc *acrtc) 366 { 367 struct ade_hw_ctx *ctx = acrtc->ctx; 368 void __iomem *base = ctx->base; 369 u32 out_fmt = acrtc->out_format; 370 371 /* enable output overlay compositor */ 372 writel(ADE_ENABLE, base + ADE_OVLYX_CTL(OUT_OVLY)); 373 ade_update_reload_bit(base, OVLY_OFST + OUT_OVLY, 0); 374 375 /* display source setting */ 376 writel(DISP_SRC_OVLY2, base + ADE_DISP_SRC_CFG); 377 378 /* enable ade */ 379 writel(ADE_ENABLE, base + ADE_EN); 380 /* enable ldi */ 381 writel(NORMAL_MODE, base + LDI_WORK_MODE); 382 writel((out_fmt << BPP_OFST) | DATA_GATE_EN | LDI_EN, 383 base + LDI_CTRL); 384 /* dsi pixel on */ 385 writel(DSI_PCLK_ON, base + LDI_HDMI_DSI_GT); 386 } 387 388 #if ADE_DEBUG 389 static void ade_rdma_dump_regs(void __iomem *base, u32 ch) 390 { 391 u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en; 392 u32 val; 393 394 reg_ctrl = RD_CH_CTRL(ch); 395 reg_addr = RD_CH_ADDR(ch); 396 reg_size = RD_CH_SIZE(ch); 397 reg_stride = RD_CH_STRIDE(ch); 398 reg_space = RD_CH_SPACE(ch); 399 reg_en = RD_CH_EN(ch); 400 401 val = ade_read_reload_bit(base, RDMA_OFST + ch); 402 DRM_DEBUG_DRIVER("[rdma%d]: reload(%d)\n", ch + 1, val); 403 val = readl(base + reg_ctrl); 404 DRM_DEBUG_DRIVER("[rdma%d]: reg_ctrl(0x%08x)\n", ch + 1, val); 405 val = readl(base + reg_addr); 406 DRM_DEBUG_DRIVER("[rdma%d]: reg_addr(0x%08x)\n", ch + 1, val); 407 val = readl(base + reg_size); 408 DRM_DEBUG_DRIVER("[rdma%d]: reg_size(0x%08x)\n", ch + 1, val); 409 val = readl(base + reg_stride); 410 DRM_DEBUG_DRIVER("[rdma%d]: reg_stride(0x%08x)\n", ch + 1, val); 411 val = readl(base + reg_space); 412 DRM_DEBUG_DRIVER("[rdma%d]: reg_space(0x%08x)\n", ch + 1, val); 413 val = readl(base + reg_en); 414 DRM_DEBUG_DRIVER("[rdma%d]: reg_en(0x%08x)\n", ch + 1, val); 415 } 416 417 static void ade_clip_dump_regs(void __iomem *base, u32 ch) 418 { 419 u32 val; 420 421 val = ade_read_reload_bit(base, CLIP_OFST + ch); 422 DRM_DEBUG_DRIVER("[clip%d]: reload(%d)\n", ch + 1, val); 423 val = readl(base + ADE_CLIP_DISABLE(ch)); 424 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_disable(0x%08x)\n", ch + 1, val); 425 val = readl(base + ADE_CLIP_SIZE0(ch)); 426 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size0(0x%08x)\n", ch + 1, val); 427 val = readl(base + ADE_CLIP_SIZE1(ch)); 428 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size1(0x%08x)\n", ch + 1, val); 429 } 430 431 static void ade_compositor_routing_dump_regs(void __iomem *base, u32 ch) 432 { 433 u8 ovly_ch = 0; /* TODO: Only primary plane now */ 434 u32 val; 435 436 val = readl(base + ADE_OVLY_CH_XY0(ovly_ch)); 437 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy0(0x%08x)\n", ovly_ch, val); 438 val = readl(base + ADE_OVLY_CH_XY1(ovly_ch)); 439 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy1(0x%08x)\n", ovly_ch, val); 440 val = readl(base + ADE_OVLY_CH_CTL(ovly_ch)); 441 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_ctl(0x%08x)\n", ovly_ch, val); 442 } 443 444 static void ade_dump_overlay_compositor_regs(void __iomem *base, u32 comp) 445 { 446 u32 val; 447 448 val = ade_read_reload_bit(base, OVLY_OFST + comp); 449 DRM_DEBUG_DRIVER("[overlay%d]: reload(%d)\n", comp + 1, val); 450 writel(ADE_ENABLE, base + ADE_OVLYX_CTL(comp)); 451 DRM_DEBUG_DRIVER("[overlay%d]: reg_ctl(0x%08x)\n", comp + 1, val); 452 val = readl(base + ADE_OVLY_CTL); 453 DRM_DEBUG_DRIVER("ovly_ctl(0x%08x)\n", val); 454 } 455 456 static void ade_dump_regs(void __iomem *base) 457 { 458 u32 i; 459 460 /* dump channel regs */ 461 for (i = 0; i < ADE_CH_NUM; i++) { 462 /* dump rdma regs */ 463 ade_rdma_dump_regs(base, i); 464 465 /* dump clip regs */ 466 ade_clip_dump_regs(base, i); 467 468 /* dump compositor routing regs */ 469 ade_compositor_routing_dump_regs(base, i); 470 } 471 472 /* dump overlay compositor regs */ 473 ade_dump_overlay_compositor_regs(base, OUT_OVLY); 474 } 475 #else 476 static void ade_dump_regs(void __iomem *base) { } 477 #endif 478 479 static void ade_crtc_atomic_enable(struct drm_crtc *crtc, 480 struct drm_crtc_state *old_state) 481 { 482 struct ade_crtc *acrtc = to_ade_crtc(crtc); 483 struct ade_hw_ctx *ctx = acrtc->ctx; 484 int ret; 485 486 if (acrtc->enable) 487 return; 488 489 if (!ctx->power_on) { 490 ret = ade_power_up(ctx); 491 if (ret) 492 return; 493 } 494 495 ade_set_medianoc_qos(acrtc); 496 ade_display_enable(acrtc); 497 ade_dump_regs(ctx->base); 498 drm_crtc_vblank_on(crtc); 499 acrtc->enable = true; 500 } 501 502 static void ade_crtc_atomic_disable(struct drm_crtc *crtc, 503 struct drm_crtc_state *old_state) 504 { 505 struct ade_crtc *acrtc = to_ade_crtc(crtc); 506 struct ade_hw_ctx *ctx = acrtc->ctx; 507 508 if (!acrtc->enable) 509 return; 510 511 drm_crtc_vblank_off(crtc); 512 ade_power_down(ctx); 513 acrtc->enable = false; 514 } 515 516 static void ade_crtc_mode_set_nofb(struct drm_crtc *crtc) 517 { 518 struct ade_crtc *acrtc = to_ade_crtc(crtc); 519 struct ade_hw_ctx *ctx = acrtc->ctx; 520 struct drm_display_mode *mode = &crtc->state->mode; 521 struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode; 522 523 if (!ctx->power_on) 524 (void)ade_power_up(ctx); 525 ade_ldi_set_mode(acrtc, mode, adj_mode); 526 } 527 528 static void ade_crtc_atomic_begin(struct drm_crtc *crtc, 529 struct drm_crtc_state *old_state) 530 { 531 struct ade_crtc *acrtc = to_ade_crtc(crtc); 532 struct ade_hw_ctx *ctx = acrtc->ctx; 533 struct drm_display_mode *mode = &crtc->state->mode; 534 struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode; 535 536 if (!ctx->power_on) 537 (void)ade_power_up(ctx); 538 ade_ldi_set_mode(acrtc, mode, adj_mode); 539 } 540 541 static void ade_crtc_atomic_flush(struct drm_crtc *crtc, 542 struct drm_crtc_state *old_state) 543 544 { 545 struct ade_crtc *acrtc = to_ade_crtc(crtc); 546 struct ade_hw_ctx *ctx = acrtc->ctx; 547 struct drm_pending_vblank_event *event = crtc->state->event; 548 void __iomem *base = ctx->base; 549 550 /* only crtc is enabled regs take effect */ 551 if (acrtc->enable) { 552 ade_dump_regs(base); 553 /* flush ade registers */ 554 writel(ADE_ENABLE, base + ADE_EN); 555 } 556 557 if (event) { 558 crtc->state->event = NULL; 559 560 spin_lock_irq(&crtc->dev->event_lock); 561 if (drm_crtc_vblank_get(crtc) == 0) 562 drm_crtc_arm_vblank_event(crtc, event); 563 else 564 drm_crtc_send_vblank_event(crtc, event); 565 spin_unlock_irq(&crtc->dev->event_lock); 566 } 567 } 568 569 static const struct drm_crtc_helper_funcs ade_crtc_helper_funcs = { 570 .mode_fixup = ade_crtc_mode_fixup, 571 .mode_set_nofb = ade_crtc_mode_set_nofb, 572 .atomic_begin = ade_crtc_atomic_begin, 573 .atomic_flush = ade_crtc_atomic_flush, 574 .atomic_enable = ade_crtc_atomic_enable, 575 .atomic_disable = ade_crtc_atomic_disable, 576 }; 577 578 static const struct drm_crtc_funcs ade_crtc_funcs = { 579 .destroy = drm_crtc_cleanup, 580 .set_config = drm_atomic_helper_set_config, 581 .page_flip = drm_atomic_helper_page_flip, 582 .reset = drm_atomic_helper_crtc_reset, 583 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 584 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 585 .enable_vblank = ade_crtc_enable_vblank, 586 .disable_vblank = ade_crtc_disable_vblank, 587 }; 588 589 static int ade_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, 590 struct drm_plane *plane) 591 { 592 struct device_node *port; 593 int ret; 594 595 /* set crtc port so that 596 * drm_of_find_possible_crtcs call works 597 */ 598 port = of_get_child_by_name(dev->dev->of_node, "port"); 599 if (!port) { 600 DRM_ERROR("no port node found in %pOF\n", dev->dev->of_node); 601 return -EINVAL; 602 } 603 of_node_put(port); 604 crtc->port = port; 605 606 ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL, 607 &ade_crtc_funcs, NULL); 608 if (ret) { 609 DRM_ERROR("failed to init crtc.\n"); 610 return ret; 611 } 612 613 drm_crtc_helper_add(crtc, &ade_crtc_helper_funcs); 614 615 return 0; 616 } 617 618 static void ade_rdma_set(void __iomem *base, struct drm_framebuffer *fb, 619 u32 ch, u32 y, u32 in_h, u32 fmt) 620 { 621 struct drm_gem_cma_object *obj = drm_fb_cma_get_gem_obj(fb, 0); 622 struct drm_format_name_buf format_name; 623 u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en; 624 u32 stride = fb->pitches[0]; 625 u32 addr = (u32)obj->paddr + y * stride; 626 627 DRM_DEBUG_DRIVER("rdma%d: (y=%d, height=%d), stride=%d, paddr=0x%x\n", 628 ch + 1, y, in_h, stride, (u32)obj->paddr); 629 DRM_DEBUG_DRIVER("addr=0x%x, fb:%dx%d, pixel_format=%d(%s)\n", 630 addr, fb->width, fb->height, fmt, 631 drm_get_format_name(fb->format->format, &format_name)); 632 633 /* get reg offset */ 634 reg_ctrl = RD_CH_CTRL(ch); 635 reg_addr = RD_CH_ADDR(ch); 636 reg_size = RD_CH_SIZE(ch); 637 reg_stride = RD_CH_STRIDE(ch); 638 reg_space = RD_CH_SPACE(ch); 639 reg_en = RD_CH_EN(ch); 640 641 /* 642 * TODO: set rotation 643 */ 644 writel((fmt << 16) & 0x1f0000, base + reg_ctrl); 645 writel(addr, base + reg_addr); 646 writel((in_h << 16) | stride, base + reg_size); 647 writel(stride, base + reg_stride); 648 writel(in_h * stride, base + reg_space); 649 writel(ADE_ENABLE, base + reg_en); 650 ade_update_reload_bit(base, RDMA_OFST + ch, 0); 651 } 652 653 static void ade_rdma_disable(void __iomem *base, u32 ch) 654 { 655 u32 reg_en; 656 657 /* get reg offset */ 658 reg_en = RD_CH_EN(ch); 659 writel(0, base + reg_en); 660 ade_update_reload_bit(base, RDMA_OFST + ch, 1); 661 } 662 663 static void ade_clip_set(void __iomem *base, u32 ch, u32 fb_w, u32 x, 664 u32 in_w, u32 in_h) 665 { 666 u32 disable_val; 667 u32 clip_left; 668 u32 clip_right; 669 670 /* 671 * clip width, no need to clip height 672 */ 673 if (fb_w == in_w) { /* bypass */ 674 disable_val = 1; 675 clip_left = 0; 676 clip_right = 0; 677 } else { 678 disable_val = 0; 679 clip_left = x; 680 clip_right = fb_w - (x + in_w) - 1; 681 } 682 683 DRM_DEBUG_DRIVER("clip%d: clip_left=%d, clip_right=%d\n", 684 ch + 1, clip_left, clip_right); 685 686 writel(disable_val, base + ADE_CLIP_DISABLE(ch)); 687 writel((fb_w - 1) << 16 | (in_h - 1), base + ADE_CLIP_SIZE0(ch)); 688 writel(clip_left << 16 | clip_right, base + ADE_CLIP_SIZE1(ch)); 689 ade_update_reload_bit(base, CLIP_OFST + ch, 0); 690 } 691 692 static void ade_clip_disable(void __iomem *base, u32 ch) 693 { 694 writel(1, base + ADE_CLIP_DISABLE(ch)); 695 ade_update_reload_bit(base, CLIP_OFST + ch, 1); 696 } 697 698 static bool has_Alpha_channel(int format) 699 { 700 switch (format) { 701 case ADE_ARGB_8888: 702 case ADE_ABGR_8888: 703 case ADE_RGBA_8888: 704 case ADE_BGRA_8888: 705 return true; 706 default: 707 return false; 708 } 709 } 710 711 static void ade_get_blending_params(u32 fmt, u8 glb_alpha, u8 *alp_mode, 712 u8 *alp_sel, u8 *under_alp_sel) 713 { 714 bool has_alpha = has_Alpha_channel(fmt); 715 716 /* 717 * get alp_mode 718 */ 719 if (has_alpha && glb_alpha < 255) 720 *alp_mode = ADE_ALP_PIXEL_AND_GLB; 721 else if (has_alpha) 722 *alp_mode = ADE_ALP_PIXEL; 723 else 724 *alp_mode = ADE_ALP_GLOBAL; 725 726 /* 727 * get alp sel 728 */ 729 *alp_sel = ADE_ALP_MUL_COEFF_3; /* 1 */ 730 *under_alp_sel = ADE_ALP_MUL_COEFF_2; /* 0 */ 731 } 732 733 static void ade_compositor_routing_set(void __iomem *base, u8 ch, 734 u32 x0, u32 y0, 735 u32 in_w, u32 in_h, u32 fmt) 736 { 737 u8 ovly_ch = 0; /* TODO: This is the zpos, only one plane now */ 738 u8 glb_alpha = 255; 739 u32 x1 = x0 + in_w - 1; 740 u32 y1 = y0 + in_h - 1; 741 u32 val; 742 u8 alp_sel; 743 u8 under_alp_sel; 744 u8 alp_mode; 745 746 ade_get_blending_params(fmt, glb_alpha, &alp_mode, &alp_sel, 747 &under_alp_sel); 748 749 /* overlay routing setting 750 */ 751 writel(x0 << 16 | y0, base + ADE_OVLY_CH_XY0(ovly_ch)); 752 writel(x1 << 16 | y1, base + ADE_OVLY_CH_XY1(ovly_ch)); 753 val = (ch + 1) << CH_SEL_OFST | BIT(CH_EN_OFST) | 754 alp_sel << CH_ALP_SEL_OFST | 755 under_alp_sel << CH_UNDER_ALP_SEL_OFST | 756 glb_alpha << CH_ALP_GBL_OFST | 757 alp_mode << CH_ALP_MODE_OFST; 758 writel(val, base + ADE_OVLY_CH_CTL(ovly_ch)); 759 /* connect this plane/channel to overlay2 compositor */ 760 ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch), 761 CH_OVLY_SEL_MASK, CH_OVLY_SEL_VAL(OUT_OVLY)); 762 } 763 764 static void ade_compositor_routing_disable(void __iomem *base, u32 ch) 765 { 766 u8 ovly_ch = 0; /* TODO: Only primary plane now */ 767 768 /* disable this plane/channel */ 769 ade_update_bits(base + ADE_OVLY_CH_CTL(ovly_ch), CH_EN_OFST, 770 MASK(1), 0); 771 /* dis-connect this plane/channel of overlay2 compositor */ 772 ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch), 773 CH_OVLY_SEL_MASK, 0); 774 } 775 776 /* 777 * Typicaly, a channel looks like: DMA-->clip-->scale-->ctrans-->compositor 778 */ 779 static void ade_update_channel(struct ade_plane *aplane, 780 struct drm_framebuffer *fb, int crtc_x, 781 int crtc_y, unsigned int crtc_w, 782 unsigned int crtc_h, u32 src_x, 783 u32 src_y, u32 src_w, u32 src_h) 784 { 785 struct ade_hw_ctx *ctx = aplane->ctx; 786 void __iomem *base = ctx->base; 787 u32 fmt = ade_get_format(fb->format->format); 788 u32 ch = aplane->ch; 789 u32 in_w; 790 u32 in_h; 791 792 DRM_DEBUG_DRIVER("channel%d: src:(%d, %d)-%dx%d, crtc:(%d, %d)-%dx%d", 793 ch + 1, src_x, src_y, src_w, src_h, 794 crtc_x, crtc_y, crtc_w, crtc_h); 795 796 /* 1) DMA setting */ 797 in_w = src_w; 798 in_h = src_h; 799 ade_rdma_set(base, fb, ch, src_y, in_h, fmt); 800 801 /* 2) clip setting */ 802 ade_clip_set(base, ch, fb->width, src_x, in_w, in_h); 803 804 /* 3) TODO: scale setting for overlay planes */ 805 806 /* 4) TODO: ctran/csc setting for overlay planes */ 807 808 /* 5) compositor routing setting */ 809 ade_compositor_routing_set(base, ch, crtc_x, crtc_y, in_w, in_h, fmt); 810 } 811 812 static void ade_disable_channel(struct ade_plane *aplane) 813 { 814 struct ade_hw_ctx *ctx = aplane->ctx; 815 void __iomem *base = ctx->base; 816 u32 ch = aplane->ch; 817 818 DRM_DEBUG_DRIVER("disable channel%d\n", ch + 1); 819 820 /* disable read DMA */ 821 ade_rdma_disable(base, ch); 822 823 /* disable clip */ 824 ade_clip_disable(base, ch); 825 826 /* disable compositor routing */ 827 ade_compositor_routing_disable(base, ch); 828 } 829 830 static int ade_plane_atomic_check(struct drm_plane *plane, 831 struct drm_plane_state *state) 832 { 833 struct drm_framebuffer *fb = state->fb; 834 struct drm_crtc *crtc = state->crtc; 835 struct drm_crtc_state *crtc_state; 836 u32 src_x = state->src_x >> 16; 837 u32 src_y = state->src_y >> 16; 838 u32 src_w = state->src_w >> 16; 839 u32 src_h = state->src_h >> 16; 840 int crtc_x = state->crtc_x; 841 int crtc_y = state->crtc_y; 842 u32 crtc_w = state->crtc_w; 843 u32 crtc_h = state->crtc_h; 844 u32 fmt; 845 846 if (!crtc || !fb) 847 return 0; 848 849 fmt = ade_get_format(fb->format->format); 850 if (fmt == ADE_FORMAT_UNSUPPORT) 851 return -EINVAL; 852 853 crtc_state = drm_atomic_get_crtc_state(state->state, crtc); 854 if (IS_ERR(crtc_state)) 855 return PTR_ERR(crtc_state); 856 857 if (src_w != crtc_w || src_h != crtc_h) { 858 return -EINVAL; 859 } 860 861 if (src_x + src_w > fb->width || 862 src_y + src_h > fb->height) 863 return -EINVAL; 864 865 if (crtc_x < 0 || crtc_y < 0) 866 return -EINVAL; 867 868 if (crtc_x + crtc_w > crtc_state->adjusted_mode.hdisplay || 869 crtc_y + crtc_h > crtc_state->adjusted_mode.vdisplay) 870 return -EINVAL; 871 872 return 0; 873 } 874 875 static void ade_plane_atomic_update(struct drm_plane *plane, 876 struct drm_plane_state *old_state) 877 { 878 struct drm_plane_state *state = plane->state; 879 struct ade_plane *aplane = to_ade_plane(plane); 880 881 ade_update_channel(aplane, state->fb, state->crtc_x, state->crtc_y, 882 state->crtc_w, state->crtc_h, 883 state->src_x >> 16, state->src_y >> 16, 884 state->src_w >> 16, state->src_h >> 16); 885 } 886 887 static void ade_plane_atomic_disable(struct drm_plane *plane, 888 struct drm_plane_state *old_state) 889 { 890 struct ade_plane *aplane = to_ade_plane(plane); 891 892 ade_disable_channel(aplane); 893 } 894 895 static const struct drm_plane_helper_funcs ade_plane_helper_funcs = { 896 .atomic_check = ade_plane_atomic_check, 897 .atomic_update = ade_plane_atomic_update, 898 .atomic_disable = ade_plane_atomic_disable, 899 }; 900 901 static struct drm_plane_funcs ade_plane_funcs = { 902 .update_plane = drm_atomic_helper_update_plane, 903 .disable_plane = drm_atomic_helper_disable_plane, 904 .destroy = drm_plane_cleanup, 905 .reset = drm_atomic_helper_plane_reset, 906 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 907 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 908 }; 909 910 static int ade_plane_init(struct drm_device *dev, struct ade_plane *aplane, 911 enum drm_plane_type type) 912 { 913 const u32 *fmts; 914 u32 fmts_cnt; 915 int ret = 0; 916 917 /* get properties */ 918 fmts_cnt = ade_get_channel_formats(aplane->ch, &fmts); 919 if (ret) 920 return ret; 921 922 ret = drm_universal_plane_init(dev, &aplane->base, 1, &ade_plane_funcs, 923 fmts, fmts_cnt, NULL, type, NULL); 924 if (ret) { 925 DRM_ERROR("fail to init plane, ch=%d\n", aplane->ch); 926 return ret; 927 } 928 929 drm_plane_helper_add(&aplane->base, &ade_plane_helper_funcs); 930 931 return 0; 932 } 933 934 static int ade_dts_parse(struct platform_device *pdev, struct ade_hw_ctx *ctx) 935 { 936 struct resource *res; 937 struct device *dev = &pdev->dev; 938 struct device_node *np = pdev->dev.of_node; 939 940 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 941 ctx->base = devm_ioremap_resource(dev, res); 942 if (IS_ERR(ctx->base)) { 943 DRM_ERROR("failed to remap ade io base\n"); 944 return PTR_ERR(ctx->base); 945 } 946 947 ctx->reset = devm_reset_control_get(dev, NULL); 948 if (IS_ERR(ctx->reset)) 949 return PTR_ERR(ctx->reset); 950 951 ctx->noc_regmap = 952 syscon_regmap_lookup_by_phandle(np, "hisilicon,noc-syscon"); 953 if (IS_ERR(ctx->noc_regmap)) { 954 DRM_ERROR("failed to get noc regmap\n"); 955 return PTR_ERR(ctx->noc_regmap); 956 } 957 958 ctx->irq = platform_get_irq(pdev, 0); 959 if (ctx->irq < 0) { 960 DRM_ERROR("failed to get irq\n"); 961 return -ENODEV; 962 } 963 964 ctx->ade_core_clk = devm_clk_get(dev, "clk_ade_core"); 965 if (IS_ERR(ctx->ade_core_clk)) { 966 DRM_ERROR("failed to parse clk ADE_CORE\n"); 967 return PTR_ERR(ctx->ade_core_clk); 968 } 969 970 ctx->media_noc_clk = devm_clk_get(dev, "clk_codec_jpeg"); 971 if (IS_ERR(ctx->media_noc_clk)) { 972 DRM_ERROR("failed to parse clk CODEC_JPEG\n"); 973 return PTR_ERR(ctx->media_noc_clk); 974 } 975 976 ctx->ade_pix_clk = devm_clk_get(dev, "clk_ade_pix"); 977 if (IS_ERR(ctx->ade_pix_clk)) { 978 DRM_ERROR("failed to parse clk ADE_PIX\n"); 979 return PTR_ERR(ctx->ade_pix_clk); 980 } 981 982 return 0; 983 } 984 985 static int ade_drm_init(struct platform_device *pdev) 986 { 987 struct drm_device *dev = platform_get_drvdata(pdev); 988 struct ade_data *ade; 989 struct ade_hw_ctx *ctx; 990 struct ade_crtc *acrtc; 991 struct ade_plane *aplane; 992 enum drm_plane_type type; 993 int ret; 994 int i; 995 996 ade = devm_kzalloc(dev->dev, sizeof(*ade), GFP_KERNEL); 997 if (!ade) { 998 DRM_ERROR("failed to alloc ade_data\n"); 999 return -ENOMEM; 1000 } 1001 platform_set_drvdata(pdev, ade); 1002 1003 ctx = &ade->ctx; 1004 acrtc = &ade->acrtc; 1005 acrtc->ctx = ctx; 1006 acrtc->out_format = LDI_OUT_RGB_888; 1007 1008 ret = ade_dts_parse(pdev, ctx); 1009 if (ret) 1010 return ret; 1011 1012 /* 1013 * plane init 1014 * TODO: Now only support primary plane, overlay planes 1015 * need to do. 1016 */ 1017 for (i = 0; i < ADE_CH_NUM; i++) { 1018 aplane = &ade->aplane[i]; 1019 aplane->ch = i; 1020 aplane->ctx = ctx; 1021 type = i == PRIMARY_CH ? DRM_PLANE_TYPE_PRIMARY : 1022 DRM_PLANE_TYPE_OVERLAY; 1023 1024 ret = ade_plane_init(dev, aplane, type); 1025 if (ret) 1026 return ret; 1027 } 1028 1029 /* crtc init */ 1030 ret = ade_crtc_init(dev, &acrtc->base, &ade->aplane[PRIMARY_CH].base); 1031 if (ret) 1032 return ret; 1033 1034 /* vblank irq init */ 1035 ret = devm_request_irq(dev->dev, ctx->irq, ade_irq_handler, 1036 IRQF_SHARED, dev->driver->name, acrtc); 1037 if (ret) 1038 return ret; 1039 1040 return 0; 1041 } 1042 1043 static void ade_drm_cleanup(struct platform_device *pdev) 1044 { 1045 } 1046 1047 const struct kirin_dc_ops ade_dc_ops = { 1048 .init = ade_drm_init, 1049 .cleanup = ade_drm_cleanup 1050 }; 1051