1 /* 2 * Hisilicon Hi6220 SoC ADE(Advanced Display Engine)'s crtc&plane driver 3 * 4 * Copyright (c) 2016 Linaro Limited. 5 * Copyright (c) 2014-2016 Hisilicon Limited. 6 * 7 * Author: 8 * Xinliang Liu <z.liuxinliang@hisilicon.com> 9 * Xinliang Liu <xinliang.liu@linaro.org> 10 * Xinwei Kong <kong.kongxinwei@hisilicon.com> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 * 16 */ 17 18 #include <linux/bitops.h> 19 #include <linux/clk.h> 20 #include <video/display_timing.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/regmap.h> 23 #include <linux/reset.h> 24 25 #include <drm/drmP.h> 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_plane_helper.h> 31 #include <drm/drm_gem_cma_helper.h> 32 #include <drm/drm_fb_cma_helper.h> 33 34 #include "kirin_drm_drv.h" 35 #include "kirin_ade_reg.h" 36 37 #define PRIMARY_CH ADE_CH1 /* primary plane */ 38 #define OUT_OVLY ADE_OVLY2 /* output overlay compositor */ 39 #define ADE_DEBUG 1 40 41 #define to_ade_crtc(crtc) \ 42 container_of(crtc, struct ade_crtc, base) 43 44 #define to_ade_plane(plane) \ 45 container_of(plane, struct ade_plane, base) 46 47 struct ade_hw_ctx { 48 void __iomem *base; 49 struct regmap *noc_regmap; 50 struct clk *ade_core_clk; 51 struct clk *media_noc_clk; 52 struct clk *ade_pix_clk; 53 struct reset_control *reset; 54 bool power_on; 55 int irq; 56 }; 57 58 struct ade_crtc { 59 struct drm_crtc base; 60 struct ade_hw_ctx *ctx; 61 bool enable; 62 u32 out_format; 63 }; 64 65 struct ade_plane { 66 struct drm_plane base; 67 void *ctx; 68 u8 ch; /* channel */ 69 }; 70 71 struct ade_data { 72 struct ade_crtc acrtc; 73 struct ade_plane aplane[ADE_CH_NUM]; 74 struct ade_hw_ctx ctx; 75 }; 76 77 /* ade-format info: */ 78 struct ade_format { 79 u32 pixel_format; 80 enum ade_fb_format ade_format; 81 }; 82 83 static const struct ade_format ade_formats[] = { 84 /* 16bpp RGB: */ 85 { DRM_FORMAT_RGB565, ADE_RGB_565 }, 86 { DRM_FORMAT_BGR565, ADE_BGR_565 }, 87 /* 24bpp RGB: */ 88 { DRM_FORMAT_RGB888, ADE_RGB_888 }, 89 { DRM_FORMAT_BGR888, ADE_BGR_888 }, 90 /* 32bpp [A]RGB: */ 91 { DRM_FORMAT_XRGB8888, ADE_XRGB_8888 }, 92 { DRM_FORMAT_XBGR8888, ADE_XBGR_8888 }, 93 { DRM_FORMAT_RGBA8888, ADE_RGBA_8888 }, 94 { DRM_FORMAT_BGRA8888, ADE_BGRA_8888 }, 95 { DRM_FORMAT_ARGB8888, ADE_ARGB_8888 }, 96 { DRM_FORMAT_ABGR8888, ADE_ABGR_8888 }, 97 }; 98 99 static const u32 channel_formats1[] = { 100 /* channel 1,2,3,4 */ 101 DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888, 102 DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, 103 DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888, 104 DRM_FORMAT_ABGR8888 105 }; 106 107 u32 ade_get_channel_formats(u8 ch, const u32 **formats) 108 { 109 switch (ch) { 110 case ADE_CH1: 111 *formats = channel_formats1; 112 return ARRAY_SIZE(channel_formats1); 113 default: 114 DRM_ERROR("no this channel %d\n", ch); 115 *formats = NULL; 116 return 0; 117 } 118 } 119 120 /* convert from fourcc format to ade format */ 121 static u32 ade_get_format(u32 pixel_format) 122 { 123 int i; 124 125 for (i = 0; i < ARRAY_SIZE(ade_formats); i++) 126 if (ade_formats[i].pixel_format == pixel_format) 127 return ade_formats[i].ade_format; 128 129 /* not found */ 130 DRM_ERROR("Not found pixel format!!fourcc_format= %d\n", 131 pixel_format); 132 return ADE_FORMAT_UNSUPPORT; 133 } 134 135 static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val) 136 { 137 u32 bit_ofst, reg_num; 138 139 bit_ofst = bit_num % 32; 140 reg_num = bit_num / 32; 141 142 ade_update_bits(base + ADE_RELOAD_DIS(reg_num), bit_ofst, 143 MASK(1), !!val); 144 } 145 146 static u32 ade_read_reload_bit(void __iomem *base, u32 bit_num) 147 { 148 u32 tmp, bit_ofst, reg_num; 149 150 bit_ofst = bit_num % 32; 151 reg_num = bit_num / 32; 152 153 tmp = readl(base + ADE_RELOAD_DIS(reg_num)); 154 return !!(BIT(bit_ofst) & tmp); 155 } 156 157 static void ade_init(struct ade_hw_ctx *ctx) 158 { 159 void __iomem *base = ctx->base; 160 161 /* enable clk gate */ 162 ade_update_bits(base + ADE_CTRL1, AUTO_CLK_GATE_EN_OFST, 163 AUTO_CLK_GATE_EN, ADE_ENABLE); 164 /* clear overlay */ 165 writel(0, base + ADE_OVLY1_TRANS_CFG); 166 writel(0, base + ADE_OVLY_CTL); 167 writel(0, base + ADE_OVLYX_CTL(OUT_OVLY)); 168 /* clear reset and reload regs */ 169 writel(MASK(32), base + ADE_SOFT_RST_SEL(0)); 170 writel(MASK(32), base + ADE_SOFT_RST_SEL(1)); 171 writel(MASK(32), base + ADE_RELOAD_DIS(0)); 172 writel(MASK(32), base + ADE_RELOAD_DIS(1)); 173 /* 174 * for video mode, all the ade registers should 175 * become effective at frame end. 176 */ 177 ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST, 178 FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND); 179 } 180 181 static bool ade_crtc_mode_fixup(struct drm_crtc *crtc, 182 const struct drm_display_mode *mode, 183 struct drm_display_mode *adjusted_mode) 184 { 185 struct ade_crtc *acrtc = to_ade_crtc(crtc); 186 struct ade_hw_ctx *ctx = acrtc->ctx; 187 188 adjusted_mode->clock = 189 clk_round_rate(ctx->ade_pix_clk, mode->clock * 1000) / 1000; 190 return true; 191 } 192 193 194 static void ade_set_pix_clk(struct ade_hw_ctx *ctx, 195 struct drm_display_mode *mode, 196 struct drm_display_mode *adj_mode) 197 { 198 u32 clk_Hz = mode->clock * 1000; 199 int ret; 200 201 /* 202 * Success should be guaranteed in mode_valid call back, 203 * so failure shouldn't happen here 204 */ 205 ret = clk_set_rate(ctx->ade_pix_clk, clk_Hz); 206 if (ret) 207 DRM_ERROR("failed to set pixel clk %dHz (%d)\n", clk_Hz, ret); 208 adj_mode->clock = clk_get_rate(ctx->ade_pix_clk) / 1000; 209 } 210 211 static void ade_ldi_set_mode(struct ade_crtc *acrtc, 212 struct drm_display_mode *mode, 213 struct drm_display_mode *adj_mode) 214 { 215 struct ade_hw_ctx *ctx = acrtc->ctx; 216 void __iomem *base = ctx->base; 217 u32 width = mode->hdisplay; 218 u32 height = mode->vdisplay; 219 u32 hfp, hbp, hsw, vfp, vbp, vsw; 220 u32 plr_flags; 221 222 plr_flags = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? FLAG_NVSYNC : 0; 223 plr_flags |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? FLAG_NHSYNC : 0; 224 hfp = mode->hsync_start - mode->hdisplay; 225 hbp = mode->htotal - mode->hsync_end; 226 hsw = mode->hsync_end - mode->hsync_start; 227 vfp = mode->vsync_start - mode->vdisplay; 228 vbp = mode->vtotal - mode->vsync_end; 229 vsw = mode->vsync_end - mode->vsync_start; 230 if (vsw > 15) { 231 DRM_DEBUG_DRIVER("vsw exceeded 15\n"); 232 vsw = 15; 233 } 234 235 writel((hbp << HBP_OFST) | hfp, base + LDI_HRZ_CTRL0); 236 /* the configured value is actual value - 1 */ 237 writel(hsw - 1, base + LDI_HRZ_CTRL1); 238 writel((vbp << VBP_OFST) | vfp, base + LDI_VRT_CTRL0); 239 /* the configured value is actual value - 1 */ 240 writel(vsw - 1, base + LDI_VRT_CTRL1); 241 /* the configured value is actual value - 1 */ 242 writel(((height - 1) << VSIZE_OFST) | (width - 1), 243 base + LDI_DSP_SIZE); 244 writel(plr_flags, base + LDI_PLR_CTRL); 245 246 /* set overlay compositor output size */ 247 writel(((width - 1) << OUTPUT_XSIZE_OFST) | (height - 1), 248 base + ADE_OVLY_OUTPUT_SIZE(OUT_OVLY)); 249 250 /* ctran6 setting */ 251 writel(CTRAN_BYPASS_ON, base + ADE_CTRAN_DIS(ADE_CTRAN6)); 252 /* the configured value is actual value - 1 */ 253 writel(width * height - 1, base + ADE_CTRAN_IMAGE_SIZE(ADE_CTRAN6)); 254 ade_update_reload_bit(base, CTRAN_OFST + ADE_CTRAN6, 0); 255 256 ade_set_pix_clk(ctx, mode, adj_mode); 257 258 DRM_DEBUG_DRIVER("set mode: %dx%d\n", width, height); 259 } 260 261 static int ade_power_up(struct ade_hw_ctx *ctx) 262 { 263 int ret; 264 265 ret = clk_prepare_enable(ctx->media_noc_clk); 266 if (ret) { 267 DRM_ERROR("failed to enable media_noc_clk (%d)\n", ret); 268 return ret; 269 } 270 271 ret = reset_control_deassert(ctx->reset); 272 if (ret) { 273 DRM_ERROR("failed to deassert reset\n"); 274 return ret; 275 } 276 277 ret = clk_prepare_enable(ctx->ade_core_clk); 278 if (ret) { 279 DRM_ERROR("failed to enable ade_core_clk (%d)\n", ret); 280 return ret; 281 } 282 283 ade_init(ctx); 284 ctx->power_on = true; 285 return 0; 286 } 287 288 static void ade_power_down(struct ade_hw_ctx *ctx) 289 { 290 void __iomem *base = ctx->base; 291 292 writel(ADE_DISABLE, base + LDI_CTRL); 293 /* dsi pixel off */ 294 writel(DSI_PCLK_OFF, base + LDI_HDMI_DSI_GT); 295 296 clk_disable_unprepare(ctx->ade_core_clk); 297 reset_control_assert(ctx->reset); 298 clk_disable_unprepare(ctx->media_noc_clk); 299 ctx->power_on = false; 300 } 301 302 static void ade_set_medianoc_qos(struct ade_crtc *acrtc) 303 { 304 struct ade_hw_ctx *ctx = acrtc->ctx; 305 struct regmap *map = ctx->noc_regmap; 306 307 regmap_update_bits(map, ADE0_QOSGENERATOR_MODE, 308 QOSGENERATOR_MODE_MASK, BYPASS_MODE); 309 regmap_update_bits(map, ADE0_QOSGENERATOR_EXTCONTROL, 310 SOCKET_QOS_EN, SOCKET_QOS_EN); 311 312 regmap_update_bits(map, ADE1_QOSGENERATOR_MODE, 313 QOSGENERATOR_MODE_MASK, BYPASS_MODE); 314 regmap_update_bits(map, ADE1_QOSGENERATOR_EXTCONTROL, 315 SOCKET_QOS_EN, SOCKET_QOS_EN); 316 } 317 318 static int ade_crtc_enable_vblank(struct drm_crtc *crtc) 319 { 320 struct ade_crtc *acrtc = to_ade_crtc(crtc); 321 struct ade_hw_ctx *ctx = acrtc->ctx; 322 void __iomem *base = ctx->base; 323 324 if (!ctx->power_on) 325 (void)ade_power_up(ctx); 326 327 ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST, 328 MASK(1), 1); 329 330 return 0; 331 } 332 333 static void ade_crtc_disable_vblank(struct drm_crtc *crtc) 334 { 335 struct ade_crtc *acrtc = to_ade_crtc(crtc); 336 struct ade_hw_ctx *ctx = acrtc->ctx; 337 void __iomem *base = ctx->base; 338 339 if (!ctx->power_on) { 340 DRM_ERROR("power is down! vblank disable fail\n"); 341 return; 342 } 343 344 ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST, 345 MASK(1), 0); 346 } 347 348 static irqreturn_t ade_irq_handler(int irq, void *data) 349 { 350 struct ade_crtc *acrtc = data; 351 struct ade_hw_ctx *ctx = acrtc->ctx; 352 struct drm_crtc *crtc = &acrtc->base; 353 void __iomem *base = ctx->base; 354 u32 status; 355 356 status = readl(base + LDI_MSK_INT); 357 DRM_DEBUG_VBL("LDI IRQ: status=0x%X\n", status); 358 359 /* vblank irq */ 360 if (status & BIT(FRAME_END_INT_EN_OFST)) { 361 ade_update_bits(base + LDI_INT_CLR, FRAME_END_INT_EN_OFST, 362 MASK(1), 1); 363 drm_crtc_handle_vblank(crtc); 364 } 365 366 return IRQ_HANDLED; 367 } 368 369 static void ade_display_enable(struct ade_crtc *acrtc) 370 { 371 struct ade_hw_ctx *ctx = acrtc->ctx; 372 void __iomem *base = ctx->base; 373 u32 out_fmt = acrtc->out_format; 374 375 /* enable output overlay compositor */ 376 writel(ADE_ENABLE, base + ADE_OVLYX_CTL(OUT_OVLY)); 377 ade_update_reload_bit(base, OVLY_OFST + OUT_OVLY, 0); 378 379 /* display source setting */ 380 writel(DISP_SRC_OVLY2, base + ADE_DISP_SRC_CFG); 381 382 /* enable ade */ 383 writel(ADE_ENABLE, base + ADE_EN); 384 /* enable ldi */ 385 writel(NORMAL_MODE, base + LDI_WORK_MODE); 386 writel((out_fmt << BPP_OFST) | DATA_GATE_EN | LDI_EN, 387 base + LDI_CTRL); 388 /* dsi pixel on */ 389 writel(DSI_PCLK_ON, base + LDI_HDMI_DSI_GT); 390 } 391 392 #if ADE_DEBUG 393 static void ade_rdma_dump_regs(void __iomem *base, u32 ch) 394 { 395 u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en; 396 u32 val; 397 398 reg_ctrl = RD_CH_CTRL(ch); 399 reg_addr = RD_CH_ADDR(ch); 400 reg_size = RD_CH_SIZE(ch); 401 reg_stride = RD_CH_STRIDE(ch); 402 reg_space = RD_CH_SPACE(ch); 403 reg_en = RD_CH_EN(ch); 404 405 val = ade_read_reload_bit(base, RDMA_OFST + ch); 406 DRM_DEBUG_DRIVER("[rdma%d]: reload(%d)\n", ch + 1, val); 407 val = readl(base + reg_ctrl); 408 DRM_DEBUG_DRIVER("[rdma%d]: reg_ctrl(0x%08x)\n", ch + 1, val); 409 val = readl(base + reg_addr); 410 DRM_DEBUG_DRIVER("[rdma%d]: reg_addr(0x%08x)\n", ch + 1, val); 411 val = readl(base + reg_size); 412 DRM_DEBUG_DRIVER("[rdma%d]: reg_size(0x%08x)\n", ch + 1, val); 413 val = readl(base + reg_stride); 414 DRM_DEBUG_DRIVER("[rdma%d]: reg_stride(0x%08x)\n", ch + 1, val); 415 val = readl(base + reg_space); 416 DRM_DEBUG_DRIVER("[rdma%d]: reg_space(0x%08x)\n", ch + 1, val); 417 val = readl(base + reg_en); 418 DRM_DEBUG_DRIVER("[rdma%d]: reg_en(0x%08x)\n", ch + 1, val); 419 } 420 421 static void ade_clip_dump_regs(void __iomem *base, u32 ch) 422 { 423 u32 val; 424 425 val = ade_read_reload_bit(base, CLIP_OFST + ch); 426 DRM_DEBUG_DRIVER("[clip%d]: reload(%d)\n", ch + 1, val); 427 val = readl(base + ADE_CLIP_DISABLE(ch)); 428 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_disable(0x%08x)\n", ch + 1, val); 429 val = readl(base + ADE_CLIP_SIZE0(ch)); 430 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size0(0x%08x)\n", ch + 1, val); 431 val = readl(base + ADE_CLIP_SIZE1(ch)); 432 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size1(0x%08x)\n", ch + 1, val); 433 } 434 435 static void ade_compositor_routing_dump_regs(void __iomem *base, u32 ch) 436 { 437 u8 ovly_ch = 0; /* TODO: Only primary plane now */ 438 u32 val; 439 440 val = readl(base + ADE_OVLY_CH_XY0(ovly_ch)); 441 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy0(0x%08x)\n", ovly_ch, val); 442 val = readl(base + ADE_OVLY_CH_XY1(ovly_ch)); 443 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy1(0x%08x)\n", ovly_ch, val); 444 val = readl(base + ADE_OVLY_CH_CTL(ovly_ch)); 445 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_ctl(0x%08x)\n", ovly_ch, val); 446 } 447 448 static void ade_dump_overlay_compositor_regs(void __iomem *base, u32 comp) 449 { 450 u32 val; 451 452 val = ade_read_reload_bit(base, OVLY_OFST + comp); 453 DRM_DEBUG_DRIVER("[overlay%d]: reload(%d)\n", comp + 1, val); 454 writel(ADE_ENABLE, base + ADE_OVLYX_CTL(comp)); 455 DRM_DEBUG_DRIVER("[overlay%d]: reg_ctl(0x%08x)\n", comp + 1, val); 456 val = readl(base + ADE_OVLY_CTL); 457 DRM_DEBUG_DRIVER("ovly_ctl(0x%08x)\n", val); 458 } 459 460 static void ade_dump_regs(void __iomem *base) 461 { 462 u32 i; 463 464 /* dump channel regs */ 465 for (i = 0; i < ADE_CH_NUM; i++) { 466 /* dump rdma regs */ 467 ade_rdma_dump_regs(base, i); 468 469 /* dump clip regs */ 470 ade_clip_dump_regs(base, i); 471 472 /* dump compositor routing regs */ 473 ade_compositor_routing_dump_regs(base, i); 474 } 475 476 /* dump overlay compositor regs */ 477 ade_dump_overlay_compositor_regs(base, OUT_OVLY); 478 } 479 #else 480 static void ade_dump_regs(void __iomem *base) { } 481 #endif 482 483 static void ade_crtc_atomic_enable(struct drm_crtc *crtc, 484 struct drm_crtc_state *old_state) 485 { 486 struct ade_crtc *acrtc = to_ade_crtc(crtc); 487 struct ade_hw_ctx *ctx = acrtc->ctx; 488 int ret; 489 490 if (acrtc->enable) 491 return; 492 493 if (!ctx->power_on) { 494 ret = ade_power_up(ctx); 495 if (ret) 496 return; 497 } 498 499 ade_set_medianoc_qos(acrtc); 500 ade_display_enable(acrtc); 501 ade_dump_regs(ctx->base); 502 drm_crtc_vblank_on(crtc); 503 acrtc->enable = true; 504 } 505 506 static void ade_crtc_atomic_disable(struct drm_crtc *crtc, 507 struct drm_crtc_state *old_state) 508 { 509 struct ade_crtc *acrtc = to_ade_crtc(crtc); 510 struct ade_hw_ctx *ctx = acrtc->ctx; 511 512 if (!acrtc->enable) 513 return; 514 515 drm_crtc_vblank_off(crtc); 516 ade_power_down(ctx); 517 acrtc->enable = false; 518 } 519 520 static void ade_crtc_mode_set_nofb(struct drm_crtc *crtc) 521 { 522 struct ade_crtc *acrtc = to_ade_crtc(crtc); 523 struct ade_hw_ctx *ctx = acrtc->ctx; 524 struct drm_display_mode *mode = &crtc->state->mode; 525 struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode; 526 527 if (!ctx->power_on) 528 (void)ade_power_up(ctx); 529 ade_ldi_set_mode(acrtc, mode, adj_mode); 530 } 531 532 static void ade_crtc_atomic_begin(struct drm_crtc *crtc, 533 struct drm_crtc_state *old_state) 534 { 535 struct ade_crtc *acrtc = to_ade_crtc(crtc); 536 struct ade_hw_ctx *ctx = acrtc->ctx; 537 538 if (!ctx->power_on) 539 (void)ade_power_up(ctx); 540 } 541 542 static void ade_crtc_atomic_flush(struct drm_crtc *crtc, 543 struct drm_crtc_state *old_state) 544 545 { 546 struct ade_crtc *acrtc = to_ade_crtc(crtc); 547 struct ade_hw_ctx *ctx = acrtc->ctx; 548 struct drm_pending_vblank_event *event = crtc->state->event; 549 void __iomem *base = ctx->base; 550 551 /* only crtc is enabled regs take effect */ 552 if (acrtc->enable) { 553 ade_dump_regs(base); 554 /* flush ade registers */ 555 writel(ADE_ENABLE, base + ADE_EN); 556 } 557 558 if (event) { 559 crtc->state->event = NULL; 560 561 spin_lock_irq(&crtc->dev->event_lock); 562 if (drm_crtc_vblank_get(crtc) == 0) 563 drm_crtc_arm_vblank_event(crtc, event); 564 else 565 drm_crtc_send_vblank_event(crtc, event); 566 spin_unlock_irq(&crtc->dev->event_lock); 567 } 568 } 569 570 static const struct drm_crtc_helper_funcs ade_crtc_helper_funcs = { 571 .mode_fixup = ade_crtc_mode_fixup, 572 .mode_set_nofb = ade_crtc_mode_set_nofb, 573 .atomic_begin = ade_crtc_atomic_begin, 574 .atomic_flush = ade_crtc_atomic_flush, 575 .atomic_enable = ade_crtc_atomic_enable, 576 .atomic_disable = ade_crtc_atomic_disable, 577 }; 578 579 static const struct drm_crtc_funcs ade_crtc_funcs = { 580 .destroy = drm_crtc_cleanup, 581 .set_config = drm_atomic_helper_set_config, 582 .page_flip = drm_atomic_helper_page_flip, 583 .reset = drm_atomic_helper_crtc_reset, 584 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 585 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 586 .enable_vblank = ade_crtc_enable_vblank, 587 .disable_vblank = ade_crtc_disable_vblank, 588 }; 589 590 static int ade_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, 591 struct drm_plane *plane) 592 { 593 struct device_node *port; 594 int ret; 595 596 /* set crtc port so that 597 * drm_of_find_possible_crtcs call works 598 */ 599 port = of_get_child_by_name(dev->dev->of_node, "port"); 600 if (!port) { 601 DRM_ERROR("no port node found in %pOF\n", dev->dev->of_node); 602 return -EINVAL; 603 } 604 of_node_put(port); 605 crtc->port = port; 606 607 ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL, 608 &ade_crtc_funcs, NULL); 609 if (ret) { 610 DRM_ERROR("failed to init crtc.\n"); 611 return ret; 612 } 613 614 drm_crtc_helper_add(crtc, &ade_crtc_helper_funcs); 615 616 return 0; 617 } 618 619 static void ade_rdma_set(void __iomem *base, struct drm_framebuffer *fb, 620 u32 ch, u32 y, u32 in_h, u32 fmt) 621 { 622 struct drm_gem_cma_object *obj = drm_fb_cma_get_gem_obj(fb, 0); 623 struct drm_format_name_buf format_name; 624 u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en; 625 u32 stride = fb->pitches[0]; 626 u32 addr = (u32)obj->paddr + y * stride; 627 628 DRM_DEBUG_DRIVER("rdma%d: (y=%d, height=%d), stride=%d, paddr=0x%x\n", 629 ch + 1, y, in_h, stride, (u32)obj->paddr); 630 DRM_DEBUG_DRIVER("addr=0x%x, fb:%dx%d, pixel_format=%d(%s)\n", 631 addr, fb->width, fb->height, fmt, 632 drm_get_format_name(fb->format->format, &format_name)); 633 634 /* get reg offset */ 635 reg_ctrl = RD_CH_CTRL(ch); 636 reg_addr = RD_CH_ADDR(ch); 637 reg_size = RD_CH_SIZE(ch); 638 reg_stride = RD_CH_STRIDE(ch); 639 reg_space = RD_CH_SPACE(ch); 640 reg_en = RD_CH_EN(ch); 641 642 /* 643 * TODO: set rotation 644 */ 645 writel((fmt << 16) & 0x1f0000, base + reg_ctrl); 646 writel(addr, base + reg_addr); 647 writel((in_h << 16) | stride, base + reg_size); 648 writel(stride, base + reg_stride); 649 writel(in_h * stride, base + reg_space); 650 writel(ADE_ENABLE, base + reg_en); 651 ade_update_reload_bit(base, RDMA_OFST + ch, 0); 652 } 653 654 static void ade_rdma_disable(void __iomem *base, u32 ch) 655 { 656 u32 reg_en; 657 658 /* get reg offset */ 659 reg_en = RD_CH_EN(ch); 660 writel(0, base + reg_en); 661 ade_update_reload_bit(base, RDMA_OFST + ch, 1); 662 } 663 664 static void ade_clip_set(void __iomem *base, u32 ch, u32 fb_w, u32 x, 665 u32 in_w, u32 in_h) 666 { 667 u32 disable_val; 668 u32 clip_left; 669 u32 clip_right; 670 671 /* 672 * clip width, no need to clip height 673 */ 674 if (fb_w == in_w) { /* bypass */ 675 disable_val = 1; 676 clip_left = 0; 677 clip_right = 0; 678 } else { 679 disable_val = 0; 680 clip_left = x; 681 clip_right = fb_w - (x + in_w) - 1; 682 } 683 684 DRM_DEBUG_DRIVER("clip%d: clip_left=%d, clip_right=%d\n", 685 ch + 1, clip_left, clip_right); 686 687 writel(disable_val, base + ADE_CLIP_DISABLE(ch)); 688 writel((fb_w - 1) << 16 | (in_h - 1), base + ADE_CLIP_SIZE0(ch)); 689 writel(clip_left << 16 | clip_right, base + ADE_CLIP_SIZE1(ch)); 690 ade_update_reload_bit(base, CLIP_OFST + ch, 0); 691 } 692 693 static void ade_clip_disable(void __iomem *base, u32 ch) 694 { 695 writel(1, base + ADE_CLIP_DISABLE(ch)); 696 ade_update_reload_bit(base, CLIP_OFST + ch, 1); 697 } 698 699 static bool has_Alpha_channel(int format) 700 { 701 switch (format) { 702 case ADE_ARGB_8888: 703 case ADE_ABGR_8888: 704 case ADE_RGBA_8888: 705 case ADE_BGRA_8888: 706 return true; 707 default: 708 return false; 709 } 710 } 711 712 static void ade_get_blending_params(u32 fmt, u8 glb_alpha, u8 *alp_mode, 713 u8 *alp_sel, u8 *under_alp_sel) 714 { 715 bool has_alpha = has_Alpha_channel(fmt); 716 717 /* 718 * get alp_mode 719 */ 720 if (has_alpha && glb_alpha < 255) 721 *alp_mode = ADE_ALP_PIXEL_AND_GLB; 722 else if (has_alpha) 723 *alp_mode = ADE_ALP_PIXEL; 724 else 725 *alp_mode = ADE_ALP_GLOBAL; 726 727 /* 728 * get alp sel 729 */ 730 *alp_sel = ADE_ALP_MUL_COEFF_3; /* 1 */ 731 *under_alp_sel = ADE_ALP_MUL_COEFF_2; /* 0 */ 732 } 733 734 static void ade_compositor_routing_set(void __iomem *base, u8 ch, 735 u32 x0, u32 y0, 736 u32 in_w, u32 in_h, u32 fmt) 737 { 738 u8 ovly_ch = 0; /* TODO: This is the zpos, only one plane now */ 739 u8 glb_alpha = 255; 740 u32 x1 = x0 + in_w - 1; 741 u32 y1 = y0 + in_h - 1; 742 u32 val; 743 u8 alp_sel; 744 u8 under_alp_sel; 745 u8 alp_mode; 746 747 ade_get_blending_params(fmt, glb_alpha, &alp_mode, &alp_sel, 748 &under_alp_sel); 749 750 /* overlay routing setting 751 */ 752 writel(x0 << 16 | y0, base + ADE_OVLY_CH_XY0(ovly_ch)); 753 writel(x1 << 16 | y1, base + ADE_OVLY_CH_XY1(ovly_ch)); 754 val = (ch + 1) << CH_SEL_OFST | BIT(CH_EN_OFST) | 755 alp_sel << CH_ALP_SEL_OFST | 756 under_alp_sel << CH_UNDER_ALP_SEL_OFST | 757 glb_alpha << CH_ALP_GBL_OFST | 758 alp_mode << CH_ALP_MODE_OFST; 759 writel(val, base + ADE_OVLY_CH_CTL(ovly_ch)); 760 /* connect this plane/channel to overlay2 compositor */ 761 ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch), 762 CH_OVLY_SEL_MASK, CH_OVLY_SEL_VAL(OUT_OVLY)); 763 } 764 765 static void ade_compositor_routing_disable(void __iomem *base, u32 ch) 766 { 767 u8 ovly_ch = 0; /* TODO: Only primary plane now */ 768 769 /* disable this plane/channel */ 770 ade_update_bits(base + ADE_OVLY_CH_CTL(ovly_ch), CH_EN_OFST, 771 MASK(1), 0); 772 /* dis-connect this plane/channel of overlay2 compositor */ 773 ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch), 774 CH_OVLY_SEL_MASK, 0); 775 } 776 777 /* 778 * Typicaly, a channel looks like: DMA-->clip-->scale-->ctrans-->compositor 779 */ 780 static void ade_update_channel(struct ade_plane *aplane, 781 struct drm_framebuffer *fb, int crtc_x, 782 int crtc_y, unsigned int crtc_w, 783 unsigned int crtc_h, u32 src_x, 784 u32 src_y, u32 src_w, u32 src_h) 785 { 786 struct ade_hw_ctx *ctx = aplane->ctx; 787 void __iomem *base = ctx->base; 788 u32 fmt = ade_get_format(fb->format->format); 789 u32 ch = aplane->ch; 790 u32 in_w; 791 u32 in_h; 792 793 DRM_DEBUG_DRIVER("channel%d: src:(%d, %d)-%dx%d, crtc:(%d, %d)-%dx%d", 794 ch + 1, src_x, src_y, src_w, src_h, 795 crtc_x, crtc_y, crtc_w, crtc_h); 796 797 /* 1) DMA setting */ 798 in_w = src_w; 799 in_h = src_h; 800 ade_rdma_set(base, fb, ch, src_y, in_h, fmt); 801 802 /* 2) clip setting */ 803 ade_clip_set(base, ch, fb->width, src_x, in_w, in_h); 804 805 /* 3) TODO: scale setting for overlay planes */ 806 807 /* 4) TODO: ctran/csc setting for overlay planes */ 808 809 /* 5) compositor routing setting */ 810 ade_compositor_routing_set(base, ch, crtc_x, crtc_y, in_w, in_h, fmt); 811 } 812 813 static void ade_disable_channel(struct ade_plane *aplane) 814 { 815 struct ade_hw_ctx *ctx = aplane->ctx; 816 void __iomem *base = ctx->base; 817 u32 ch = aplane->ch; 818 819 DRM_DEBUG_DRIVER("disable channel%d\n", ch + 1); 820 821 /* disable read DMA */ 822 ade_rdma_disable(base, ch); 823 824 /* disable clip */ 825 ade_clip_disable(base, ch); 826 827 /* disable compositor routing */ 828 ade_compositor_routing_disable(base, ch); 829 } 830 831 static int ade_plane_atomic_check(struct drm_plane *plane, 832 struct drm_plane_state *state) 833 { 834 struct drm_framebuffer *fb = state->fb; 835 struct drm_crtc *crtc = state->crtc; 836 struct drm_crtc_state *crtc_state; 837 u32 src_x = state->src_x >> 16; 838 u32 src_y = state->src_y >> 16; 839 u32 src_w = state->src_w >> 16; 840 u32 src_h = state->src_h >> 16; 841 int crtc_x = state->crtc_x; 842 int crtc_y = state->crtc_y; 843 u32 crtc_w = state->crtc_w; 844 u32 crtc_h = state->crtc_h; 845 u32 fmt; 846 847 if (!crtc || !fb) 848 return 0; 849 850 fmt = ade_get_format(fb->format->format); 851 if (fmt == ADE_FORMAT_UNSUPPORT) 852 return -EINVAL; 853 854 crtc_state = drm_atomic_get_crtc_state(state->state, crtc); 855 if (IS_ERR(crtc_state)) 856 return PTR_ERR(crtc_state); 857 858 if (src_w != crtc_w || src_h != crtc_h) { 859 DRM_ERROR("Scale not support!!!\n"); 860 return -EINVAL; 861 } 862 863 if (src_x + src_w > fb->width || 864 src_y + src_h > fb->height) 865 return -EINVAL; 866 867 if (crtc_x < 0 || crtc_y < 0) 868 return -EINVAL; 869 870 if (crtc_x + crtc_w > crtc_state->adjusted_mode.hdisplay || 871 crtc_y + crtc_h > crtc_state->adjusted_mode.vdisplay) 872 return -EINVAL; 873 874 return 0; 875 } 876 877 static void ade_plane_atomic_update(struct drm_plane *plane, 878 struct drm_plane_state *old_state) 879 { 880 struct drm_plane_state *state = plane->state; 881 struct ade_plane *aplane = to_ade_plane(plane); 882 883 ade_update_channel(aplane, state->fb, state->crtc_x, state->crtc_y, 884 state->crtc_w, state->crtc_h, 885 state->src_x >> 16, state->src_y >> 16, 886 state->src_w >> 16, state->src_h >> 16); 887 } 888 889 static void ade_plane_atomic_disable(struct drm_plane *plane, 890 struct drm_plane_state *old_state) 891 { 892 struct ade_plane *aplane = to_ade_plane(plane); 893 894 ade_disable_channel(aplane); 895 } 896 897 static const struct drm_plane_helper_funcs ade_plane_helper_funcs = { 898 .atomic_check = ade_plane_atomic_check, 899 .atomic_update = ade_plane_atomic_update, 900 .atomic_disable = ade_plane_atomic_disable, 901 }; 902 903 static struct drm_plane_funcs ade_plane_funcs = { 904 .update_plane = drm_atomic_helper_update_plane, 905 .disable_plane = drm_atomic_helper_disable_plane, 906 .destroy = drm_plane_cleanup, 907 .reset = drm_atomic_helper_plane_reset, 908 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 909 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 910 }; 911 912 static int ade_plane_init(struct drm_device *dev, struct ade_plane *aplane, 913 enum drm_plane_type type) 914 { 915 const u32 *fmts; 916 u32 fmts_cnt; 917 int ret = 0; 918 919 /* get properties */ 920 fmts_cnt = ade_get_channel_formats(aplane->ch, &fmts); 921 if (ret) 922 return ret; 923 924 ret = drm_universal_plane_init(dev, &aplane->base, 1, &ade_plane_funcs, 925 fmts, fmts_cnt, NULL, type, NULL); 926 if (ret) { 927 DRM_ERROR("fail to init plane, ch=%d\n", aplane->ch); 928 return ret; 929 } 930 931 drm_plane_helper_add(&aplane->base, &ade_plane_helper_funcs); 932 933 return 0; 934 } 935 936 static int ade_dts_parse(struct platform_device *pdev, struct ade_hw_ctx *ctx) 937 { 938 struct resource *res; 939 struct device *dev = &pdev->dev; 940 struct device_node *np = pdev->dev.of_node; 941 942 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 943 ctx->base = devm_ioremap_resource(dev, res); 944 if (IS_ERR(ctx->base)) { 945 DRM_ERROR("failed to remap ade io base\n"); 946 return PTR_ERR(ctx->base); 947 } 948 949 ctx->reset = devm_reset_control_get(dev, NULL); 950 if (IS_ERR(ctx->reset)) 951 return PTR_ERR(ctx->reset); 952 953 ctx->noc_regmap = 954 syscon_regmap_lookup_by_phandle(np, "hisilicon,noc-syscon"); 955 if (IS_ERR(ctx->noc_regmap)) { 956 DRM_ERROR("failed to get noc regmap\n"); 957 return PTR_ERR(ctx->noc_regmap); 958 } 959 960 ctx->irq = platform_get_irq(pdev, 0); 961 if (ctx->irq < 0) { 962 DRM_ERROR("failed to get irq\n"); 963 return -ENODEV; 964 } 965 966 ctx->ade_core_clk = devm_clk_get(dev, "clk_ade_core"); 967 if (IS_ERR(ctx->ade_core_clk)) { 968 DRM_ERROR("failed to parse clk ADE_CORE\n"); 969 return PTR_ERR(ctx->ade_core_clk); 970 } 971 972 ctx->media_noc_clk = devm_clk_get(dev, "clk_codec_jpeg"); 973 if (IS_ERR(ctx->media_noc_clk)) { 974 DRM_ERROR("failed to parse clk CODEC_JPEG\n"); 975 return PTR_ERR(ctx->media_noc_clk); 976 } 977 978 ctx->ade_pix_clk = devm_clk_get(dev, "clk_ade_pix"); 979 if (IS_ERR(ctx->ade_pix_clk)) { 980 DRM_ERROR("failed to parse clk ADE_PIX\n"); 981 return PTR_ERR(ctx->ade_pix_clk); 982 } 983 984 return 0; 985 } 986 987 static int ade_drm_init(struct platform_device *pdev) 988 { 989 struct drm_device *dev = platform_get_drvdata(pdev); 990 struct ade_data *ade; 991 struct ade_hw_ctx *ctx; 992 struct ade_crtc *acrtc; 993 struct ade_plane *aplane; 994 enum drm_plane_type type; 995 int ret; 996 int i; 997 998 ade = devm_kzalloc(dev->dev, sizeof(*ade), GFP_KERNEL); 999 if (!ade) { 1000 DRM_ERROR("failed to alloc ade_data\n"); 1001 return -ENOMEM; 1002 } 1003 platform_set_drvdata(pdev, ade); 1004 1005 ctx = &ade->ctx; 1006 acrtc = &ade->acrtc; 1007 acrtc->ctx = ctx; 1008 acrtc->out_format = LDI_OUT_RGB_888; 1009 1010 ret = ade_dts_parse(pdev, ctx); 1011 if (ret) 1012 return ret; 1013 1014 /* 1015 * plane init 1016 * TODO: Now only support primary plane, overlay planes 1017 * need to do. 1018 */ 1019 for (i = 0; i < ADE_CH_NUM; i++) { 1020 aplane = &ade->aplane[i]; 1021 aplane->ch = i; 1022 aplane->ctx = ctx; 1023 type = i == PRIMARY_CH ? DRM_PLANE_TYPE_PRIMARY : 1024 DRM_PLANE_TYPE_OVERLAY; 1025 1026 ret = ade_plane_init(dev, aplane, type); 1027 if (ret) 1028 return ret; 1029 } 1030 1031 /* crtc init */ 1032 ret = ade_crtc_init(dev, &acrtc->base, &ade->aplane[PRIMARY_CH].base); 1033 if (ret) 1034 return ret; 1035 1036 /* vblank irq init */ 1037 ret = devm_request_irq(dev->dev, ctx->irq, ade_irq_handler, 1038 IRQF_SHARED, dev->driver->name, acrtc); 1039 if (ret) 1040 return ret; 1041 1042 return 0; 1043 } 1044 1045 static void ade_drm_cleanup(struct platform_device *pdev) 1046 { 1047 } 1048 1049 const struct kirin_dc_ops ade_dc_ops = { 1050 .init = ade_drm_init, 1051 .cleanup = ade_drm_cleanup 1052 }; 1053