1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Hisilicon Hi6220 SoC ADE(Advanced Display Engine)'s crtc&plane driver 4 * 5 * Copyright (c) 2016 Linaro Limited. 6 * Copyright (c) 2014-2016 HiSilicon Limited. 7 * 8 * Author: 9 * Xinliang Liu <z.liuxinliang@hisilicon.com> 10 * Xinliang Liu <xinliang.liu@linaro.org> 11 * Xinwei Kong <kong.kongxinwei@hisilicon.com> 12 */ 13 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/platform_device.h> 18 #include <linux/regmap.h> 19 #include <linux/reset.h> 20 21 #include <video/display_timing.h> 22 23 #include <drm/drm_atomic.h> 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_crtc.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fb_cma_helper.h> 28 #include <drm/drm_fourcc.h> 29 #include <drm/drm_framebuffer.h> 30 #include <drm/drm_gem_cma_helper.h> 31 #include <drm/drm_plane_helper.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 #include <drm/drm_gem_framebuffer_helper.h> 35 36 #include "kirin_drm_drv.h" 37 #include "kirin_ade_reg.h" 38 39 #define OUT_OVLY ADE_OVLY2 /* output overlay compositor */ 40 #define ADE_DEBUG 1 41 42 43 struct ade_hw_ctx { 44 void __iomem *base; 45 struct regmap *noc_regmap; 46 struct clk *ade_core_clk; 47 struct clk *media_noc_clk; 48 struct clk *ade_pix_clk; 49 struct reset_control *reset; 50 bool power_on; 51 int irq; 52 53 struct drm_crtc *crtc; 54 }; 55 56 static const struct kirin_format ade_formats[] = { 57 /* 16bpp RGB: */ 58 { DRM_FORMAT_RGB565, ADE_RGB_565 }, 59 { DRM_FORMAT_BGR565, ADE_BGR_565 }, 60 /* 24bpp RGB: */ 61 { DRM_FORMAT_RGB888, ADE_RGB_888 }, 62 { DRM_FORMAT_BGR888, ADE_BGR_888 }, 63 /* 32bpp [A]RGB: */ 64 { DRM_FORMAT_XRGB8888, ADE_XRGB_8888 }, 65 { DRM_FORMAT_XBGR8888, ADE_XBGR_8888 }, 66 { DRM_FORMAT_RGBA8888, ADE_RGBA_8888 }, 67 { DRM_FORMAT_BGRA8888, ADE_BGRA_8888 }, 68 { DRM_FORMAT_ARGB8888, ADE_ARGB_8888 }, 69 { DRM_FORMAT_ABGR8888, ADE_ABGR_8888 }, 70 }; 71 72 static const u32 channel_formats[] = { 73 /* channel 1,2,3,4 */ 74 DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888, 75 DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, 76 DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888, 77 DRM_FORMAT_ABGR8888 78 }; 79 80 /* convert from fourcc format to ade format */ 81 static u32 ade_get_format(u32 pixel_format) 82 { 83 int i; 84 85 for (i = 0; i < ARRAY_SIZE(ade_formats); i++) 86 if (ade_formats[i].pixel_format == pixel_format) 87 return ade_formats[i].hw_format; 88 89 /* not found */ 90 DRM_ERROR("Not found pixel format!!fourcc_format= %d\n", 91 pixel_format); 92 return ADE_FORMAT_UNSUPPORT; 93 } 94 95 static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val) 96 { 97 u32 bit_ofst, reg_num; 98 99 bit_ofst = bit_num % 32; 100 reg_num = bit_num / 32; 101 102 ade_update_bits(base + ADE_RELOAD_DIS(reg_num), bit_ofst, 103 MASK(1), !!val); 104 } 105 106 static u32 ade_read_reload_bit(void __iomem *base, u32 bit_num) 107 { 108 u32 tmp, bit_ofst, reg_num; 109 110 bit_ofst = bit_num % 32; 111 reg_num = bit_num / 32; 112 113 tmp = readl(base + ADE_RELOAD_DIS(reg_num)); 114 return !!(BIT(bit_ofst) & tmp); 115 } 116 117 static void ade_init(struct ade_hw_ctx *ctx) 118 { 119 void __iomem *base = ctx->base; 120 121 /* enable clk gate */ 122 ade_update_bits(base + ADE_CTRL1, AUTO_CLK_GATE_EN_OFST, 123 AUTO_CLK_GATE_EN, ADE_ENABLE); 124 /* clear overlay */ 125 writel(0, base + ADE_OVLY1_TRANS_CFG); 126 writel(0, base + ADE_OVLY_CTL); 127 writel(0, base + ADE_OVLYX_CTL(OUT_OVLY)); 128 /* clear reset and reload regs */ 129 writel(MASK(32), base + ADE_SOFT_RST_SEL(0)); 130 writel(MASK(32), base + ADE_SOFT_RST_SEL(1)); 131 writel(MASK(32), base + ADE_RELOAD_DIS(0)); 132 writel(MASK(32), base + ADE_RELOAD_DIS(1)); 133 /* 134 * for video mode, all the ade registers should 135 * become effective at frame end. 136 */ 137 ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST, 138 FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND); 139 } 140 141 static bool ade_crtc_mode_fixup(struct drm_crtc *crtc, 142 const struct drm_display_mode *mode, 143 struct drm_display_mode *adjusted_mode) 144 { 145 struct kirin_crtc *kcrtc = to_kirin_crtc(crtc); 146 struct ade_hw_ctx *ctx = kcrtc->hw_ctx; 147 148 adjusted_mode->clock = 149 clk_round_rate(ctx->ade_pix_clk, mode->clock * 1000) / 1000; 150 return true; 151 } 152 153 154 static void ade_set_pix_clk(struct ade_hw_ctx *ctx, 155 struct drm_display_mode *mode, 156 struct drm_display_mode *adj_mode) 157 { 158 u32 clk_Hz = mode->clock * 1000; 159 int ret; 160 161 /* 162 * Success should be guaranteed in mode_valid call back, 163 * so failure shouldn't happen here 164 */ 165 ret = clk_set_rate(ctx->ade_pix_clk, clk_Hz); 166 if (ret) 167 DRM_ERROR("failed to set pixel clk %dHz (%d)\n", clk_Hz, ret); 168 adj_mode->clock = clk_get_rate(ctx->ade_pix_clk) / 1000; 169 } 170 171 static void ade_ldi_set_mode(struct ade_hw_ctx *ctx, 172 struct drm_display_mode *mode, 173 struct drm_display_mode *adj_mode) 174 { 175 void __iomem *base = ctx->base; 176 u32 width = mode->hdisplay; 177 u32 height = mode->vdisplay; 178 u32 hfp, hbp, hsw, vfp, vbp, vsw; 179 u32 plr_flags; 180 181 plr_flags = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? FLAG_NVSYNC : 0; 182 plr_flags |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? FLAG_NHSYNC : 0; 183 hfp = mode->hsync_start - mode->hdisplay; 184 hbp = mode->htotal - mode->hsync_end; 185 hsw = mode->hsync_end - mode->hsync_start; 186 vfp = mode->vsync_start - mode->vdisplay; 187 vbp = mode->vtotal - mode->vsync_end; 188 vsw = mode->vsync_end - mode->vsync_start; 189 if (vsw > 15) { 190 DRM_DEBUG_DRIVER("vsw exceeded 15\n"); 191 vsw = 15; 192 } 193 194 writel((hbp << HBP_OFST) | hfp, base + LDI_HRZ_CTRL0); 195 /* the configured value is actual value - 1 */ 196 writel(hsw - 1, base + LDI_HRZ_CTRL1); 197 writel((vbp << VBP_OFST) | vfp, base + LDI_VRT_CTRL0); 198 /* the configured value is actual value - 1 */ 199 writel(vsw - 1, base + LDI_VRT_CTRL1); 200 /* the configured value is actual value - 1 */ 201 writel(((height - 1) << VSIZE_OFST) | (width - 1), 202 base + LDI_DSP_SIZE); 203 writel(plr_flags, base + LDI_PLR_CTRL); 204 205 /* set overlay compositor output size */ 206 writel(((width - 1) << OUTPUT_XSIZE_OFST) | (height - 1), 207 base + ADE_OVLY_OUTPUT_SIZE(OUT_OVLY)); 208 209 /* ctran6 setting */ 210 writel(CTRAN_BYPASS_ON, base + ADE_CTRAN_DIS(ADE_CTRAN6)); 211 /* the configured value is actual value - 1 */ 212 writel(width * height - 1, base + ADE_CTRAN_IMAGE_SIZE(ADE_CTRAN6)); 213 ade_update_reload_bit(base, CTRAN_OFST + ADE_CTRAN6, 0); 214 215 ade_set_pix_clk(ctx, mode, adj_mode); 216 217 DRM_DEBUG_DRIVER("set mode: %dx%d\n", width, height); 218 } 219 220 static int ade_power_up(struct ade_hw_ctx *ctx) 221 { 222 int ret; 223 224 ret = clk_prepare_enable(ctx->media_noc_clk); 225 if (ret) { 226 DRM_ERROR("failed to enable media_noc_clk (%d)\n", ret); 227 return ret; 228 } 229 230 ret = reset_control_deassert(ctx->reset); 231 if (ret) { 232 DRM_ERROR("failed to deassert reset\n"); 233 return ret; 234 } 235 236 ret = clk_prepare_enable(ctx->ade_core_clk); 237 if (ret) { 238 DRM_ERROR("failed to enable ade_core_clk (%d)\n", ret); 239 return ret; 240 } 241 242 ade_init(ctx); 243 ctx->power_on = true; 244 return 0; 245 } 246 247 static void ade_power_down(struct ade_hw_ctx *ctx) 248 { 249 void __iomem *base = ctx->base; 250 251 writel(ADE_DISABLE, base + LDI_CTRL); 252 /* dsi pixel off */ 253 writel(DSI_PCLK_OFF, base + LDI_HDMI_DSI_GT); 254 255 clk_disable_unprepare(ctx->ade_core_clk); 256 reset_control_assert(ctx->reset); 257 clk_disable_unprepare(ctx->media_noc_clk); 258 ctx->power_on = false; 259 } 260 261 static void ade_set_medianoc_qos(struct ade_hw_ctx *ctx) 262 { 263 struct regmap *map = ctx->noc_regmap; 264 265 regmap_update_bits(map, ADE0_QOSGENERATOR_MODE, 266 QOSGENERATOR_MODE_MASK, BYPASS_MODE); 267 regmap_update_bits(map, ADE0_QOSGENERATOR_EXTCONTROL, 268 SOCKET_QOS_EN, SOCKET_QOS_EN); 269 270 regmap_update_bits(map, ADE1_QOSGENERATOR_MODE, 271 QOSGENERATOR_MODE_MASK, BYPASS_MODE); 272 regmap_update_bits(map, ADE1_QOSGENERATOR_EXTCONTROL, 273 SOCKET_QOS_EN, SOCKET_QOS_EN); 274 } 275 276 static int ade_crtc_enable_vblank(struct drm_crtc *crtc) 277 { 278 struct kirin_crtc *kcrtc = to_kirin_crtc(crtc); 279 struct ade_hw_ctx *ctx = kcrtc->hw_ctx; 280 void __iomem *base = ctx->base; 281 282 if (!ctx->power_on) 283 (void)ade_power_up(ctx); 284 285 ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST, 286 MASK(1), 1); 287 288 return 0; 289 } 290 291 static void ade_crtc_disable_vblank(struct drm_crtc *crtc) 292 { 293 struct kirin_crtc *kcrtc = to_kirin_crtc(crtc); 294 struct ade_hw_ctx *ctx = kcrtc->hw_ctx; 295 void __iomem *base = ctx->base; 296 297 if (!ctx->power_on) { 298 DRM_ERROR("power is down! vblank disable fail\n"); 299 return; 300 } 301 302 ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST, 303 MASK(1), 0); 304 } 305 306 static irqreturn_t ade_irq_handler(int irq, void *data) 307 { 308 struct ade_hw_ctx *ctx = data; 309 struct drm_crtc *crtc = ctx->crtc; 310 void __iomem *base = ctx->base; 311 u32 status; 312 313 status = readl(base + LDI_MSK_INT); 314 DRM_DEBUG_VBL("LDI IRQ: status=0x%X\n", status); 315 316 /* vblank irq */ 317 if (status & BIT(FRAME_END_INT_EN_OFST)) { 318 ade_update_bits(base + LDI_INT_CLR, FRAME_END_INT_EN_OFST, 319 MASK(1), 1); 320 drm_crtc_handle_vblank(crtc); 321 } 322 323 return IRQ_HANDLED; 324 } 325 326 static void ade_display_enable(struct ade_hw_ctx *ctx) 327 { 328 void __iomem *base = ctx->base; 329 u32 out_fmt = LDI_OUT_RGB_888; 330 331 /* enable output overlay compositor */ 332 writel(ADE_ENABLE, base + ADE_OVLYX_CTL(OUT_OVLY)); 333 ade_update_reload_bit(base, OVLY_OFST + OUT_OVLY, 0); 334 335 /* display source setting */ 336 writel(DISP_SRC_OVLY2, base + ADE_DISP_SRC_CFG); 337 338 /* enable ade */ 339 writel(ADE_ENABLE, base + ADE_EN); 340 /* enable ldi */ 341 writel(NORMAL_MODE, base + LDI_WORK_MODE); 342 writel((out_fmt << BPP_OFST) | DATA_GATE_EN | LDI_EN, 343 base + LDI_CTRL); 344 /* dsi pixel on */ 345 writel(DSI_PCLK_ON, base + LDI_HDMI_DSI_GT); 346 } 347 348 #if ADE_DEBUG 349 static void ade_rdma_dump_regs(void __iomem *base, u32 ch) 350 { 351 u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en; 352 u32 val; 353 354 reg_ctrl = RD_CH_CTRL(ch); 355 reg_addr = RD_CH_ADDR(ch); 356 reg_size = RD_CH_SIZE(ch); 357 reg_stride = RD_CH_STRIDE(ch); 358 reg_space = RD_CH_SPACE(ch); 359 reg_en = RD_CH_EN(ch); 360 361 val = ade_read_reload_bit(base, RDMA_OFST + ch); 362 DRM_DEBUG_DRIVER("[rdma%d]: reload(%d)\n", ch + 1, val); 363 val = readl(base + reg_ctrl); 364 DRM_DEBUG_DRIVER("[rdma%d]: reg_ctrl(0x%08x)\n", ch + 1, val); 365 val = readl(base + reg_addr); 366 DRM_DEBUG_DRIVER("[rdma%d]: reg_addr(0x%08x)\n", ch + 1, val); 367 val = readl(base + reg_size); 368 DRM_DEBUG_DRIVER("[rdma%d]: reg_size(0x%08x)\n", ch + 1, val); 369 val = readl(base + reg_stride); 370 DRM_DEBUG_DRIVER("[rdma%d]: reg_stride(0x%08x)\n", ch + 1, val); 371 val = readl(base + reg_space); 372 DRM_DEBUG_DRIVER("[rdma%d]: reg_space(0x%08x)\n", ch + 1, val); 373 val = readl(base + reg_en); 374 DRM_DEBUG_DRIVER("[rdma%d]: reg_en(0x%08x)\n", ch + 1, val); 375 } 376 377 static void ade_clip_dump_regs(void __iomem *base, u32 ch) 378 { 379 u32 val; 380 381 val = ade_read_reload_bit(base, CLIP_OFST + ch); 382 DRM_DEBUG_DRIVER("[clip%d]: reload(%d)\n", ch + 1, val); 383 val = readl(base + ADE_CLIP_DISABLE(ch)); 384 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_disable(0x%08x)\n", ch + 1, val); 385 val = readl(base + ADE_CLIP_SIZE0(ch)); 386 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size0(0x%08x)\n", ch + 1, val); 387 val = readl(base + ADE_CLIP_SIZE1(ch)); 388 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size1(0x%08x)\n", ch + 1, val); 389 } 390 391 static void ade_compositor_routing_dump_regs(void __iomem *base, u32 ch) 392 { 393 u8 ovly_ch = 0; /* TODO: Only primary plane now */ 394 u32 val; 395 396 val = readl(base + ADE_OVLY_CH_XY0(ovly_ch)); 397 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy0(0x%08x)\n", ovly_ch, val); 398 val = readl(base + ADE_OVLY_CH_XY1(ovly_ch)); 399 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy1(0x%08x)\n", ovly_ch, val); 400 val = readl(base + ADE_OVLY_CH_CTL(ovly_ch)); 401 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_ctl(0x%08x)\n", ovly_ch, val); 402 } 403 404 static void ade_dump_overlay_compositor_regs(void __iomem *base, u32 comp) 405 { 406 u32 val; 407 408 val = ade_read_reload_bit(base, OVLY_OFST + comp); 409 DRM_DEBUG_DRIVER("[overlay%d]: reload(%d)\n", comp + 1, val); 410 writel(ADE_ENABLE, base + ADE_OVLYX_CTL(comp)); 411 DRM_DEBUG_DRIVER("[overlay%d]: reg_ctl(0x%08x)\n", comp + 1, val); 412 val = readl(base + ADE_OVLY_CTL); 413 DRM_DEBUG_DRIVER("ovly_ctl(0x%08x)\n", val); 414 } 415 416 static void ade_dump_regs(void __iomem *base) 417 { 418 u32 i; 419 420 /* dump channel regs */ 421 for (i = 0; i < ADE_CH_NUM; i++) { 422 /* dump rdma regs */ 423 ade_rdma_dump_regs(base, i); 424 425 /* dump clip regs */ 426 ade_clip_dump_regs(base, i); 427 428 /* dump compositor routing regs */ 429 ade_compositor_routing_dump_regs(base, i); 430 } 431 432 /* dump overlay compositor regs */ 433 ade_dump_overlay_compositor_regs(base, OUT_OVLY); 434 } 435 #else 436 static void ade_dump_regs(void __iomem *base) { } 437 #endif 438 439 static void ade_crtc_atomic_enable(struct drm_crtc *crtc, 440 struct drm_atomic_state *state) 441 { 442 struct kirin_crtc *kcrtc = to_kirin_crtc(crtc); 443 struct ade_hw_ctx *ctx = kcrtc->hw_ctx; 444 int ret; 445 446 if (kcrtc->enable) 447 return; 448 449 if (!ctx->power_on) { 450 ret = ade_power_up(ctx); 451 if (ret) 452 return; 453 } 454 455 ade_set_medianoc_qos(ctx); 456 ade_display_enable(ctx); 457 ade_dump_regs(ctx->base); 458 drm_crtc_vblank_on(crtc); 459 kcrtc->enable = true; 460 } 461 462 static void ade_crtc_atomic_disable(struct drm_crtc *crtc, 463 struct drm_atomic_state *state) 464 { 465 struct kirin_crtc *kcrtc = to_kirin_crtc(crtc); 466 struct ade_hw_ctx *ctx = kcrtc->hw_ctx; 467 468 if (!kcrtc->enable) 469 return; 470 471 drm_crtc_vblank_off(crtc); 472 ade_power_down(ctx); 473 kcrtc->enable = false; 474 } 475 476 static void ade_crtc_mode_set_nofb(struct drm_crtc *crtc) 477 { 478 struct kirin_crtc *kcrtc = to_kirin_crtc(crtc); 479 struct ade_hw_ctx *ctx = kcrtc->hw_ctx; 480 struct drm_display_mode *mode = &crtc->state->mode; 481 struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode; 482 483 if (!ctx->power_on) 484 (void)ade_power_up(ctx); 485 ade_ldi_set_mode(ctx, mode, adj_mode); 486 } 487 488 static void ade_crtc_atomic_begin(struct drm_crtc *crtc, 489 struct drm_atomic_state *state) 490 { 491 struct kirin_crtc *kcrtc = to_kirin_crtc(crtc); 492 struct ade_hw_ctx *ctx = kcrtc->hw_ctx; 493 struct drm_display_mode *mode = &crtc->state->mode; 494 struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode; 495 496 if (!ctx->power_on) 497 (void)ade_power_up(ctx); 498 ade_ldi_set_mode(ctx, mode, adj_mode); 499 } 500 501 static void ade_crtc_atomic_flush(struct drm_crtc *crtc, 502 struct drm_atomic_state *state) 503 504 { 505 struct kirin_crtc *kcrtc = to_kirin_crtc(crtc); 506 struct ade_hw_ctx *ctx = kcrtc->hw_ctx; 507 struct drm_pending_vblank_event *event = crtc->state->event; 508 void __iomem *base = ctx->base; 509 510 /* only crtc is enabled regs take effect */ 511 if (kcrtc->enable) { 512 ade_dump_regs(base); 513 /* flush ade registers */ 514 writel(ADE_ENABLE, base + ADE_EN); 515 } 516 517 if (event) { 518 crtc->state->event = NULL; 519 520 spin_lock_irq(&crtc->dev->event_lock); 521 if (drm_crtc_vblank_get(crtc) == 0) 522 drm_crtc_arm_vblank_event(crtc, event); 523 else 524 drm_crtc_send_vblank_event(crtc, event); 525 spin_unlock_irq(&crtc->dev->event_lock); 526 } 527 } 528 529 static const struct drm_crtc_helper_funcs ade_crtc_helper_funcs = { 530 .mode_fixup = ade_crtc_mode_fixup, 531 .mode_set_nofb = ade_crtc_mode_set_nofb, 532 .atomic_begin = ade_crtc_atomic_begin, 533 .atomic_flush = ade_crtc_atomic_flush, 534 .atomic_enable = ade_crtc_atomic_enable, 535 .atomic_disable = ade_crtc_atomic_disable, 536 }; 537 538 static const struct drm_crtc_funcs ade_crtc_funcs = { 539 .destroy = drm_crtc_cleanup, 540 .set_config = drm_atomic_helper_set_config, 541 .page_flip = drm_atomic_helper_page_flip, 542 .reset = drm_atomic_helper_crtc_reset, 543 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 544 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 545 .enable_vblank = ade_crtc_enable_vblank, 546 .disable_vblank = ade_crtc_disable_vblank, 547 }; 548 549 static void ade_rdma_set(void __iomem *base, struct drm_framebuffer *fb, 550 u32 ch, u32 y, u32 in_h, u32 fmt) 551 { 552 struct drm_gem_cma_object *obj = drm_fb_cma_get_gem_obj(fb, 0); 553 u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en; 554 u32 stride = fb->pitches[0]; 555 u32 addr = (u32)obj->paddr + y * stride; 556 557 DRM_DEBUG_DRIVER("rdma%d: (y=%d, height=%d), stride=%d, paddr=0x%x\n", 558 ch + 1, y, in_h, stride, (u32)obj->paddr); 559 DRM_DEBUG_DRIVER("addr=0x%x, fb:%dx%d, pixel_format=%d(%p4cc)\n", 560 addr, fb->width, fb->height, fmt, 561 &fb->format->format); 562 563 /* get reg offset */ 564 reg_ctrl = RD_CH_CTRL(ch); 565 reg_addr = RD_CH_ADDR(ch); 566 reg_size = RD_CH_SIZE(ch); 567 reg_stride = RD_CH_STRIDE(ch); 568 reg_space = RD_CH_SPACE(ch); 569 reg_en = RD_CH_EN(ch); 570 571 /* 572 * TODO: set rotation 573 */ 574 writel((fmt << 16) & 0x1f0000, base + reg_ctrl); 575 writel(addr, base + reg_addr); 576 writel((in_h << 16) | stride, base + reg_size); 577 writel(stride, base + reg_stride); 578 writel(in_h * stride, base + reg_space); 579 writel(ADE_ENABLE, base + reg_en); 580 ade_update_reload_bit(base, RDMA_OFST + ch, 0); 581 } 582 583 static void ade_rdma_disable(void __iomem *base, u32 ch) 584 { 585 u32 reg_en; 586 587 /* get reg offset */ 588 reg_en = RD_CH_EN(ch); 589 writel(0, base + reg_en); 590 ade_update_reload_bit(base, RDMA_OFST + ch, 1); 591 } 592 593 static void ade_clip_set(void __iomem *base, u32 ch, u32 fb_w, u32 x, 594 u32 in_w, u32 in_h) 595 { 596 u32 disable_val; 597 u32 clip_left; 598 u32 clip_right; 599 600 /* 601 * clip width, no need to clip height 602 */ 603 if (fb_w == in_w) { /* bypass */ 604 disable_val = 1; 605 clip_left = 0; 606 clip_right = 0; 607 } else { 608 disable_val = 0; 609 clip_left = x; 610 clip_right = fb_w - (x + in_w) - 1; 611 } 612 613 DRM_DEBUG_DRIVER("clip%d: clip_left=%d, clip_right=%d\n", 614 ch + 1, clip_left, clip_right); 615 616 writel(disable_val, base + ADE_CLIP_DISABLE(ch)); 617 writel((fb_w - 1) << 16 | (in_h - 1), base + ADE_CLIP_SIZE0(ch)); 618 writel(clip_left << 16 | clip_right, base + ADE_CLIP_SIZE1(ch)); 619 ade_update_reload_bit(base, CLIP_OFST + ch, 0); 620 } 621 622 static void ade_clip_disable(void __iomem *base, u32 ch) 623 { 624 writel(1, base + ADE_CLIP_DISABLE(ch)); 625 ade_update_reload_bit(base, CLIP_OFST + ch, 1); 626 } 627 628 static bool has_Alpha_channel(int format) 629 { 630 switch (format) { 631 case ADE_ARGB_8888: 632 case ADE_ABGR_8888: 633 case ADE_RGBA_8888: 634 case ADE_BGRA_8888: 635 return true; 636 default: 637 return false; 638 } 639 } 640 641 static void ade_get_blending_params(u32 fmt, u8 glb_alpha, u8 *alp_mode, 642 u8 *alp_sel, u8 *under_alp_sel) 643 { 644 bool has_alpha = has_Alpha_channel(fmt); 645 646 /* 647 * get alp_mode 648 */ 649 if (has_alpha && glb_alpha < 255) 650 *alp_mode = ADE_ALP_PIXEL_AND_GLB; 651 else if (has_alpha) 652 *alp_mode = ADE_ALP_PIXEL; 653 else 654 *alp_mode = ADE_ALP_GLOBAL; 655 656 /* 657 * get alp sel 658 */ 659 *alp_sel = ADE_ALP_MUL_COEFF_3; /* 1 */ 660 *under_alp_sel = ADE_ALP_MUL_COEFF_2; /* 0 */ 661 } 662 663 static void ade_compositor_routing_set(void __iomem *base, u8 ch, 664 u32 x0, u32 y0, 665 u32 in_w, u32 in_h, u32 fmt) 666 { 667 u8 ovly_ch = 0; /* TODO: This is the zpos, only one plane now */ 668 u8 glb_alpha = 255; 669 u32 x1 = x0 + in_w - 1; 670 u32 y1 = y0 + in_h - 1; 671 u32 val; 672 u8 alp_sel; 673 u8 under_alp_sel; 674 u8 alp_mode; 675 676 ade_get_blending_params(fmt, glb_alpha, &alp_mode, &alp_sel, 677 &under_alp_sel); 678 679 /* overlay routing setting 680 */ 681 writel(x0 << 16 | y0, base + ADE_OVLY_CH_XY0(ovly_ch)); 682 writel(x1 << 16 | y1, base + ADE_OVLY_CH_XY1(ovly_ch)); 683 val = (ch + 1) << CH_SEL_OFST | BIT(CH_EN_OFST) | 684 alp_sel << CH_ALP_SEL_OFST | 685 under_alp_sel << CH_UNDER_ALP_SEL_OFST | 686 glb_alpha << CH_ALP_GBL_OFST | 687 alp_mode << CH_ALP_MODE_OFST; 688 writel(val, base + ADE_OVLY_CH_CTL(ovly_ch)); 689 /* connect this plane/channel to overlay2 compositor */ 690 ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch), 691 CH_OVLY_SEL_MASK, CH_OVLY_SEL_VAL(OUT_OVLY)); 692 } 693 694 static void ade_compositor_routing_disable(void __iomem *base, u32 ch) 695 { 696 u8 ovly_ch = 0; /* TODO: Only primary plane now */ 697 698 /* disable this plane/channel */ 699 ade_update_bits(base + ADE_OVLY_CH_CTL(ovly_ch), CH_EN_OFST, 700 MASK(1), 0); 701 /* dis-connect this plane/channel of overlay2 compositor */ 702 ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch), 703 CH_OVLY_SEL_MASK, 0); 704 } 705 706 /* 707 * Typicaly, a channel looks like: DMA-->clip-->scale-->ctrans-->compositor 708 */ 709 static void ade_update_channel(struct kirin_plane *kplane, 710 struct drm_framebuffer *fb, int crtc_x, 711 int crtc_y, unsigned int crtc_w, 712 unsigned int crtc_h, u32 src_x, 713 u32 src_y, u32 src_w, u32 src_h) 714 { 715 struct ade_hw_ctx *ctx = kplane->hw_ctx; 716 void __iomem *base = ctx->base; 717 u32 fmt = ade_get_format(fb->format->format); 718 u32 ch = kplane->ch; 719 u32 in_w; 720 u32 in_h; 721 722 DRM_DEBUG_DRIVER("channel%d: src:(%d, %d)-%dx%d, crtc:(%d, %d)-%dx%d", 723 ch + 1, src_x, src_y, src_w, src_h, 724 crtc_x, crtc_y, crtc_w, crtc_h); 725 726 /* 1) DMA setting */ 727 in_w = src_w; 728 in_h = src_h; 729 ade_rdma_set(base, fb, ch, src_y, in_h, fmt); 730 731 /* 2) clip setting */ 732 ade_clip_set(base, ch, fb->width, src_x, in_w, in_h); 733 734 /* 3) TODO: scale setting for overlay planes */ 735 736 /* 4) TODO: ctran/csc setting for overlay planes */ 737 738 /* 5) compositor routing setting */ 739 ade_compositor_routing_set(base, ch, crtc_x, crtc_y, in_w, in_h, fmt); 740 } 741 742 static void ade_disable_channel(struct kirin_plane *kplane) 743 { 744 struct ade_hw_ctx *ctx = kplane->hw_ctx; 745 void __iomem *base = ctx->base; 746 u32 ch = kplane->ch; 747 748 DRM_DEBUG_DRIVER("disable channel%d\n", ch + 1); 749 750 /* disable read DMA */ 751 ade_rdma_disable(base, ch); 752 753 /* disable clip */ 754 ade_clip_disable(base, ch); 755 756 /* disable compositor routing */ 757 ade_compositor_routing_disable(base, ch); 758 } 759 760 static int ade_plane_atomic_check(struct drm_plane *plane, 761 struct drm_atomic_state *state) 762 { 763 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 764 plane); 765 struct drm_framebuffer *fb = new_plane_state->fb; 766 struct drm_crtc *crtc = new_plane_state->crtc; 767 struct drm_crtc_state *crtc_state; 768 u32 src_x = new_plane_state->src_x >> 16; 769 u32 src_y = new_plane_state->src_y >> 16; 770 u32 src_w = new_plane_state->src_w >> 16; 771 u32 src_h = new_plane_state->src_h >> 16; 772 int crtc_x = new_plane_state->crtc_x; 773 int crtc_y = new_plane_state->crtc_y; 774 u32 crtc_w = new_plane_state->crtc_w; 775 u32 crtc_h = new_plane_state->crtc_h; 776 u32 fmt; 777 778 if (!crtc || !fb) 779 return 0; 780 781 fmt = ade_get_format(fb->format->format); 782 if (fmt == ADE_FORMAT_UNSUPPORT) 783 return -EINVAL; 784 785 crtc_state = drm_atomic_get_crtc_state(state, crtc); 786 if (IS_ERR(crtc_state)) 787 return PTR_ERR(crtc_state); 788 789 if (src_w != crtc_w || src_h != crtc_h) { 790 return -EINVAL; 791 } 792 793 if (src_x + src_w > fb->width || 794 src_y + src_h > fb->height) 795 return -EINVAL; 796 797 if (crtc_x < 0 || crtc_y < 0) 798 return -EINVAL; 799 800 if (crtc_x + crtc_w > crtc_state->adjusted_mode.hdisplay || 801 crtc_y + crtc_h > crtc_state->adjusted_mode.vdisplay) 802 return -EINVAL; 803 804 return 0; 805 } 806 807 static void ade_plane_atomic_update(struct drm_plane *plane, 808 struct drm_atomic_state *state) 809 { 810 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 811 plane); 812 struct kirin_plane *kplane = to_kirin_plane(plane); 813 814 ade_update_channel(kplane, new_state->fb, new_state->crtc_x, 815 new_state->crtc_y, 816 new_state->crtc_w, new_state->crtc_h, 817 new_state->src_x >> 16, new_state->src_y >> 16, 818 new_state->src_w >> 16, new_state->src_h >> 16); 819 } 820 821 static void ade_plane_atomic_disable(struct drm_plane *plane, 822 struct drm_atomic_state *state) 823 { 824 struct kirin_plane *kplane = to_kirin_plane(plane); 825 826 ade_disable_channel(kplane); 827 } 828 829 static const struct drm_plane_helper_funcs ade_plane_helper_funcs = { 830 .atomic_check = ade_plane_atomic_check, 831 .atomic_update = ade_plane_atomic_update, 832 .atomic_disable = ade_plane_atomic_disable, 833 }; 834 835 static struct drm_plane_funcs ade_plane_funcs = { 836 .update_plane = drm_atomic_helper_update_plane, 837 .disable_plane = drm_atomic_helper_disable_plane, 838 .destroy = drm_plane_cleanup, 839 .reset = drm_atomic_helper_plane_reset, 840 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 841 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 842 }; 843 844 static void *ade_hw_ctx_alloc(struct platform_device *pdev, 845 struct drm_crtc *crtc) 846 { 847 struct resource *res; 848 struct device *dev = &pdev->dev; 849 struct device_node *np = pdev->dev.of_node; 850 struct ade_hw_ctx *ctx = NULL; 851 int ret; 852 853 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 854 if (!ctx) { 855 DRM_ERROR("failed to alloc ade_hw_ctx\n"); 856 return ERR_PTR(-ENOMEM); 857 } 858 859 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 860 ctx->base = devm_ioremap_resource(dev, res); 861 if (IS_ERR(ctx->base)) { 862 DRM_ERROR("failed to remap ade io base\n"); 863 return ERR_PTR(-EIO); 864 } 865 866 ctx->reset = devm_reset_control_get(dev, NULL); 867 if (IS_ERR(ctx->reset)) 868 return ERR_PTR(-ENODEV); 869 870 ctx->noc_regmap = 871 syscon_regmap_lookup_by_phandle(np, "hisilicon,noc-syscon"); 872 if (IS_ERR(ctx->noc_regmap)) { 873 DRM_ERROR("failed to get noc regmap\n"); 874 return ERR_PTR(-ENODEV); 875 } 876 877 ctx->irq = platform_get_irq(pdev, 0); 878 if (ctx->irq < 0) { 879 DRM_ERROR("failed to get irq\n"); 880 return ERR_PTR(-ENODEV); 881 } 882 883 ctx->ade_core_clk = devm_clk_get(dev, "clk_ade_core"); 884 if (IS_ERR(ctx->ade_core_clk)) { 885 DRM_ERROR("failed to parse clk ADE_CORE\n"); 886 return ERR_PTR(-ENODEV); 887 } 888 889 ctx->media_noc_clk = devm_clk_get(dev, "clk_codec_jpeg"); 890 if (IS_ERR(ctx->media_noc_clk)) { 891 DRM_ERROR("failed to parse clk CODEC_JPEG\n"); 892 return ERR_PTR(-ENODEV); 893 } 894 895 ctx->ade_pix_clk = devm_clk_get(dev, "clk_ade_pix"); 896 if (IS_ERR(ctx->ade_pix_clk)) { 897 DRM_ERROR("failed to parse clk ADE_PIX\n"); 898 return ERR_PTR(-ENODEV); 899 } 900 901 /* vblank irq init */ 902 ret = devm_request_irq(dev, ctx->irq, ade_irq_handler, 903 IRQF_SHARED, dev->driver->name, ctx); 904 if (ret) 905 return ERR_PTR(-EIO); 906 907 ctx->crtc = crtc; 908 909 return ctx; 910 } 911 912 static void ade_hw_ctx_cleanup(void *hw_ctx) 913 { 914 } 915 916 static const struct drm_mode_config_funcs ade_mode_config_funcs = { 917 .fb_create = drm_gem_fb_create, 918 .atomic_check = drm_atomic_helper_check, 919 .atomic_commit = drm_atomic_helper_commit, 920 921 }; 922 923 DEFINE_DRM_GEM_CMA_FOPS(ade_fops); 924 925 static const struct drm_driver ade_driver = { 926 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 927 .fops = &ade_fops, 928 DRM_GEM_CMA_DRIVER_OPS, 929 .name = "kirin", 930 .desc = "Hisilicon Kirin620 SoC DRM Driver", 931 .date = "20150718", 932 .major = 1, 933 .minor = 0, 934 }; 935 936 struct kirin_drm_data ade_driver_data = { 937 .num_planes = ADE_CH_NUM, 938 .prim_plane = ADE_CH1, 939 .channel_formats = channel_formats, 940 .channel_formats_cnt = ARRAY_SIZE(channel_formats), 941 .config_max_width = 2048, 942 .config_max_height = 2048, 943 .driver = &ade_driver, 944 .crtc_helper_funcs = &ade_crtc_helper_funcs, 945 .crtc_funcs = &ade_crtc_funcs, 946 .plane_helper_funcs = &ade_plane_helper_funcs, 947 .plane_funcs = &ade_plane_funcs, 948 .mode_config_funcs = &ade_mode_config_funcs, 949 950 .alloc_hw_ctx = ade_hw_ctx_alloc, 951 .cleanup_hw_ctx = ade_hw_ctx_cleanup, 952 }; 953