15e0df3a0SRongrong Zou /* Hisilicon Hibmc SoC drm driver 25e0df3a0SRongrong Zou * 35e0df3a0SRongrong Zou * Based on the bochs drm driver. 45e0df3a0SRongrong Zou * 55e0df3a0SRongrong Zou * Copyright (c) 2016 Huawei Limited. 65e0df3a0SRongrong Zou * 75e0df3a0SRongrong Zou * Author: 85e0df3a0SRongrong Zou * Rongrong Zou <zourongrong@huawei.com> 95e0df3a0SRongrong Zou * Rongrong Zou <zourongrong@gmail.com> 105e0df3a0SRongrong Zou * Jianhua Li <lijianhua@huawei.com> 115e0df3a0SRongrong Zou * 125e0df3a0SRongrong Zou * This program is free software; you can redistribute it and/or modify 135e0df3a0SRongrong Zou * it under the terms of the GNU General Public License as published by 145e0df3a0SRongrong Zou * the Free Software Foundation; either version 2 of the License, or 155e0df3a0SRongrong Zou * (at your option) any later version. 165e0df3a0SRongrong Zou * 175e0df3a0SRongrong Zou */ 185e0df3a0SRongrong Zou 195e0df3a0SRongrong Zou #ifndef HIBMC_DRM_HW_H 205e0df3a0SRongrong Zou #define HIBMC_DRM_HW_H 215e0df3a0SRongrong Zou 225e0df3a0SRongrong Zou /* register definition */ 235e0df3a0SRongrong Zou #define HIBMC_MISC_CTRL 0x4 245e0df3a0SRongrong Zou 255e0df3a0SRongrong Zou #define HIBMC_MSCCTL_LOCALMEM_RESET(x) ((x) << 6) 265e0df3a0SRongrong Zou #define HIBMC_MSCCTL_LOCALMEM_RESET_MASK 0x40 275e0df3a0SRongrong Zou 285e0df3a0SRongrong Zou #define HIBMC_CURRENT_GATE 0x000040 295e0df3a0SRongrong Zou #define HIBMC_CURR_GATE_DISPLAY(x) ((x) << 2) 305e0df3a0SRongrong Zou #define HIBMC_CURR_GATE_DISPLAY_MASK 0x4 315e0df3a0SRongrong Zou 325e0df3a0SRongrong Zou #define HIBMC_CURR_GATE_LOCALMEM(x) ((x) << 1) 335e0df3a0SRongrong Zou #define HIBMC_CURR_GATE_LOCALMEM_MASK 0x2 345e0df3a0SRongrong Zou 355e0df3a0SRongrong Zou #define HIBMC_MODE0_GATE 0x000044 365e0df3a0SRongrong Zou #define HIBMC_MODE1_GATE 0x000048 375e0df3a0SRongrong Zou #define HIBMC_POWER_MODE_CTRL 0x00004C 385e0df3a0SRongrong Zou 395e0df3a0SRongrong Zou #define HIBMC_PW_MODE_CTL_OSC_INPUT(x) ((x) << 3) 405e0df3a0SRongrong Zou #define HIBMC_PW_MODE_CTL_OSC_INPUT_MASK 0x8 415e0df3a0SRongrong Zou 425e0df3a0SRongrong Zou #define HIBMC_PW_MODE_CTL_MODE(x) ((x) << 0) 435e0df3a0SRongrong Zou #define HIBMC_PW_MODE_CTL_MODE_MASK 0x03 445e0df3a0SRongrong Zou #define HIBMC_PW_MODE_CTL_MODE_SHIFT 0 455e0df3a0SRongrong Zou 465e0df3a0SRongrong Zou #define HIBMC_PW_MODE_CTL_MODE_MODE0 0 475e0df3a0SRongrong Zou #define HIBMC_PW_MODE_CTL_MODE_MODE1 1 485e0df3a0SRongrong Zou #define HIBMC_PW_MODE_CTL_MODE_SLEEP 2 495e0df3a0SRongrong Zou 505e0df3a0SRongrong Zou #define HIBMC_PANEL_PLL_CTRL 0x00005C 515e0df3a0SRongrong Zou #define HIBMC_CRT_PLL_CTRL 0x000060 525e0df3a0SRongrong Zou 535e0df3a0SRongrong Zou #define HIBMC_PLL_CTRL_BYPASS(x) ((x) << 18) 545e0df3a0SRongrong Zou #define HIBMC_PLL_CTRL_BYPASS_MASK 0x40000 555e0df3a0SRongrong Zou 565e0df3a0SRongrong Zou #define HIBMC_PLL_CTRL_POWER(x) ((x) << 17) 575e0df3a0SRongrong Zou #define HIBMC_PLL_CTRL_POWER_MASK 0x20000 585e0df3a0SRongrong Zou 595e0df3a0SRongrong Zou #define HIBMC_PLL_CTRL_INPUT(x) ((x) << 16) 605e0df3a0SRongrong Zou #define HIBMC_PLL_CTRL_INPUT_MASK 0x10000 615e0df3a0SRongrong Zou 625e0df3a0SRongrong Zou #define HIBMC_PLL_CTRL_POD(x) ((x) << 14) 635e0df3a0SRongrong Zou #define HIBMC_PLL_CTRL_POD_MASK 0xC000 645e0df3a0SRongrong Zou 655e0df3a0SRongrong Zou #define HIBMC_PLL_CTRL_OD(x) ((x) << 12) 665e0df3a0SRongrong Zou #define HIBMC_PLL_CTRL_OD_MASK 0x3000 675e0df3a0SRongrong Zou 685e0df3a0SRongrong Zou #define HIBMC_PLL_CTRL_N(x) ((x) << 8) 695e0df3a0SRongrong Zou #define HIBMC_PLL_CTRL_N_MASK 0xF00 705e0df3a0SRongrong Zou 715e0df3a0SRongrong Zou #define HIBMC_PLL_CTRL_M(x) ((x) << 0) 725e0df3a0SRongrong Zou #define HIBMC_PLL_CTRL_M_MASK 0xFF 735e0df3a0SRongrong Zou 745e0df3a0SRongrong Zou #define HIBMC_CRT_DISP_CTL 0x80200 755e0df3a0SRongrong Zou 765e0df3a0SRongrong Zou #define HIBMC_CRT_DISP_CTL_CRTSELECT(x) ((x) << 25) 775e0df3a0SRongrong Zou #define HIBMC_CRT_DISP_CTL_CRTSELECT_MASK 0x2000000 785e0df3a0SRongrong Zou 795e0df3a0SRongrong Zou #define HIBMC_CRTSELECT_CRT 1 805e0df3a0SRongrong Zou 815e0df3a0SRongrong Zou #define HIBMC_CRT_DISP_CTL_CLOCK_PHASE(x) ((x) << 14) 825e0df3a0SRongrong Zou #define HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK 0x4000 835e0df3a0SRongrong Zou 845e0df3a0SRongrong Zou #define HIBMC_CRT_DISP_CTL_VSYNC_PHASE(x) ((x) << 13) 855e0df3a0SRongrong Zou #define HIBMC_CRT_DISP_CTL_VSYNC_PHASE_MASK 0x2000 865e0df3a0SRongrong Zou 875e0df3a0SRongrong Zou #define HIBMC_CRT_DISP_CTL_HSYNC_PHASE(x) ((x) << 12) 885e0df3a0SRongrong Zou #define HIBMC_CRT_DISP_CTL_HSYNC_PHASE_MASK 0x1000 895e0df3a0SRongrong Zou 905e0df3a0SRongrong Zou #define HIBMC_CRT_DISP_CTL_TIMING(x) ((x) << 8) 915e0df3a0SRongrong Zou #define HIBMC_CRT_DISP_CTL_TIMING_MASK 0x100 925e0df3a0SRongrong Zou 935e0df3a0SRongrong Zou #define HIBMC_CRT_DISP_CTL_PLANE(x) ((x) << 2) 945e0df3a0SRongrong Zou #define HIBMC_CRT_DISP_CTL_PLANE_MASK 4 955e0df3a0SRongrong Zou 965e0df3a0SRongrong Zou #define HIBMC_CRT_DISP_CTL_FORMAT(x) ((x) << 0) 975e0df3a0SRongrong Zou #define HIBMC_CRT_DISP_CTL_FORMAT_MASK 0x03 985e0df3a0SRongrong Zou 995e0df3a0SRongrong Zou #define HIBMC_CRT_FB_ADDRESS 0x080204 1005e0df3a0SRongrong Zou 1015e0df3a0SRongrong Zou #define HIBMC_CRT_FB_WIDTH 0x080208 1025e0df3a0SRongrong Zou #define HIBMC_CRT_FB_WIDTH_WIDTH(x) ((x) << 16) 1035e0df3a0SRongrong Zou #define HIBMC_CRT_FB_WIDTH_WIDTH_MASK 0x3FFF0000 1045e0df3a0SRongrong Zou #define HIBMC_CRT_FB_WIDTH_OFFS(x) ((x) << 0) 1055e0df3a0SRongrong Zou #define HIBMC_CRT_FB_WIDTH_OFFS_MASK 0x3FFF 1065e0df3a0SRongrong Zou 1075e0df3a0SRongrong Zou #define HIBMC_CRT_HORZ_TOTAL 0x08020C 1085e0df3a0SRongrong Zou #define HIBMC_CRT_HORZ_TOTAL_TOTAL(x) ((x) << 16) 1095e0df3a0SRongrong Zou #define HIBMC_CRT_HORZ_TOTAL_TOTAL_MASK 0xFFF0000 1105e0df3a0SRongrong Zou 1115e0df3a0SRongrong Zou #define HIBMC_CRT_HORZ_TOTAL_DISP_END(x) ((x) << 0) 1125e0df3a0SRongrong Zou #define HIBMC_CRT_HORZ_TOTAL_DISP_END_MASK 0xFFF 1135e0df3a0SRongrong Zou 1145e0df3a0SRongrong Zou #define HIBMC_CRT_HORZ_SYNC 0x080210 1155e0df3a0SRongrong Zou #define HIBMC_CRT_HORZ_SYNC_WIDTH(x) ((x) << 16) 1165e0df3a0SRongrong Zou #define HIBMC_CRT_HORZ_SYNC_WIDTH_MASK 0xFF0000 1175e0df3a0SRongrong Zou 1185e0df3a0SRongrong Zou #define HIBMC_CRT_HORZ_SYNC_START(x) ((x) << 0) 1195e0df3a0SRongrong Zou #define HIBMC_CRT_HORZ_SYNC_START_MASK 0xFFF 1205e0df3a0SRongrong Zou 1215e0df3a0SRongrong Zou #define HIBMC_CRT_VERT_TOTAL 0x080214 1225e0df3a0SRongrong Zou #define HIBMC_CRT_VERT_TOTAL_TOTAL(x) ((x) << 16) 1235e0df3a0SRongrong Zou #define HIBMC_CRT_VERT_TOTAL_TOTAL_MASK 0x7FFF0000 1245e0df3a0SRongrong Zou 1255e0df3a0SRongrong Zou #define HIBMC_CRT_VERT_TOTAL_DISP_END(x) ((x) << 0) 1265e0df3a0SRongrong Zou #define HIBMC_CRT_VERT_TOTAL_DISP_END_MASK 0x7FF 1275e0df3a0SRongrong Zou 1285e0df3a0SRongrong Zou #define HIBMC_CRT_VERT_SYNC 0x080218 1295e0df3a0SRongrong Zou #define HIBMC_CRT_VERT_SYNC_HEIGHT(x) ((x) << 16) 1305e0df3a0SRongrong Zou #define HIBMC_CRT_VERT_SYNC_HEIGHT_MASK 0x3F0000 1315e0df3a0SRongrong Zou 1325e0df3a0SRongrong Zou #define HIBMC_CRT_VERT_SYNC_START(x) ((x) << 0) 1335e0df3a0SRongrong Zou #define HIBMC_CRT_VERT_SYNC_START_MASK 0x7FF 1345e0df3a0SRongrong Zou 1355e0df3a0SRongrong Zou /* Auto Centering */ 1365e0df3a0SRongrong Zou #define HIBMC_CRT_AUTO_CENTERING_TL 0x080280 1375e0df3a0SRongrong Zou #define HIBMC_CRT_AUTO_CENTERING_TL_TOP(x) ((x) << 16) 1385e0df3a0SRongrong Zou #define HIBMC_CRT_AUTO_CENTERING_TL_TOP_MASK 0x7FF0000 1395e0df3a0SRongrong Zou 1405e0df3a0SRongrong Zou #define HIBMC_CRT_AUTO_CENTERING_TL_LEFT(x) ((x) << 0) 1415e0df3a0SRongrong Zou #define HIBMC_CRT_AUTO_CENTERING_TL_LEFT_MASK 0x7FF 1425e0df3a0SRongrong Zou 1435e0df3a0SRongrong Zou #define HIBMC_CRT_AUTO_CENTERING_BR 0x080284 1445e0df3a0SRongrong Zou #define HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM(x) ((x) << 16) 1455e0df3a0SRongrong Zou #define HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM_MASK 0x7FF0000 1465e0df3a0SRongrong Zou 1475e0df3a0SRongrong Zou #define HIBMC_CRT_AUTO_CENTERING_BR_RIGHT(x) ((x) << 0) 1485e0df3a0SRongrong Zou #define HIBMC_CRT_AUTO_CENTERING_BR_RIGHT_MASK 0x7FF 1495e0df3a0SRongrong Zou 1505e0df3a0SRongrong Zou /* register to control panel output */ 1515e0df3a0SRongrong Zou #define HIBMC_DISPLAY_CONTROL_HISILE 0x80288 1525e0df3a0SRongrong Zou #define HIBMC_DISPLAY_CONTROL_FPVDDEN(x) ((x) << 0) 1535e0df3a0SRongrong Zou #define HIBMC_DISPLAY_CONTROL_PANELDATE(x) ((x) << 1) 1545e0df3a0SRongrong Zou #define HIBMC_DISPLAY_CONTROL_FPEN(x) ((x) << 2) 1555e0df3a0SRongrong Zou #define HIBMC_DISPLAY_CONTROL_VBIASEN(x) ((x) << 3) 1565e0df3a0SRongrong Zou 1575e0df3a0SRongrong Zou #define HIBMC_RAW_INTERRUPT 0x80290 1585e0df3a0SRongrong Zou #define HIBMC_RAW_INTERRUPT_VBLANK(x) ((x) << 2) 1595e0df3a0SRongrong Zou #define HIBMC_RAW_INTERRUPT_VBLANK_MASK 0x4 1605e0df3a0SRongrong Zou 1615e0df3a0SRongrong Zou #define HIBMC_RAW_INTERRUPT_EN 0x80298 1625e0df3a0SRongrong Zou #define HIBMC_RAW_INTERRUPT_EN_VBLANK(x) ((x) << 2) 1635e0df3a0SRongrong Zou #define HIBMC_RAW_INTERRUPT_EN_VBLANK_MASK 0x4 1645e0df3a0SRongrong Zou 1655e0df3a0SRongrong Zou /* register and values for PLL control */ 1665e0df3a0SRongrong Zou #define CRT_PLL1_HS 0x802a8 1675e0df3a0SRongrong Zou #define CRT_PLL1_HS_OUTER_BYPASS(x) ((x) << 30) 1685e0df3a0SRongrong Zou #define CRT_PLL1_HS_INTER_BYPASS(x) ((x) << 29) 1695e0df3a0SRongrong Zou #define CRT_PLL1_HS_POWERON(x) ((x) << 24) 1705e0df3a0SRongrong Zou 1715e0df3a0SRongrong Zou #define CRT_PLL1_HS_25MHZ 0x23d40f02 1725e0df3a0SRongrong Zou #define CRT_PLL1_HS_40MHZ 0x23940801 1735e0df3a0SRongrong Zou #define CRT_PLL1_HS_65MHZ 0x23940d01 1745e0df3a0SRongrong Zou #define CRT_PLL1_HS_78MHZ 0x23540F82 1755e0df3a0SRongrong Zou #define CRT_PLL1_HS_74MHZ 0x23941dc2 1765e0df3a0SRongrong Zou #define CRT_PLL1_HS_80MHZ 0x23941001 1775e0df3a0SRongrong Zou #define CRT_PLL1_HS_80MHZ_1152 0x23540fc2 1785e0df3a0SRongrong Zou #define CRT_PLL1_HS_108MHZ 0x23b41b01 1795e0df3a0SRongrong Zou #define CRT_PLL1_HS_162MHZ 0x23480681 1805e0df3a0SRongrong Zou #define CRT_PLL1_HS_148MHZ 0x23541dc2 1815e0df3a0SRongrong Zou #define CRT_PLL1_HS_193MHZ 0x234807c1 1825e0df3a0SRongrong Zou 1835e0df3a0SRongrong Zou #define CRT_PLL2_HS 0x802ac 1845e0df3a0SRongrong Zou #define CRT_PLL2_HS_25MHZ 0x206B851E 1855e0df3a0SRongrong Zou #define CRT_PLL2_HS_40MHZ 0x30000000 1865e0df3a0SRongrong Zou #define CRT_PLL2_HS_65MHZ 0x40000000 1875e0df3a0SRongrong Zou #define CRT_PLL2_HS_78MHZ 0x50E147AE 1885e0df3a0SRongrong Zou #define CRT_PLL2_HS_74MHZ 0x602B6AE7 1895e0df3a0SRongrong Zou #define CRT_PLL2_HS_80MHZ 0x70000000 1905e0df3a0SRongrong Zou #define CRT_PLL2_HS_108MHZ 0x80000000 1915e0df3a0SRongrong Zou #define CRT_PLL2_HS_162MHZ 0xA0000000 1925e0df3a0SRongrong Zou #define CRT_PLL2_HS_148MHZ 0xB0CCCCCD 1935e0df3a0SRongrong Zou #define CRT_PLL2_HS_193MHZ 0xC0872B02 1945e0df3a0SRongrong Zou 1955e0df3a0SRongrong Zou #define HIBMC_FIELD(field, value) (field(value) & field##_MASK) 1965e0df3a0SRongrong Zou #endif 197