1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Hisilicon Hibmc SoC drm driver 3 * 4 * Based on the bochs drm driver. 5 * 6 * Copyright (c) 2016 Huawei Limited. 7 * 8 * Author: 9 * Rongrong Zou <zourongrong@huawei.com> 10 * Rongrong Zou <zourongrong@gmail.com> 11 * Jianhua Li <lijianhua@huawei.com> 12 */ 13 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_gem_vram_helper.h> 20 #include <drm/drm_irq.h> 21 #include <drm/drm_managed.h> 22 #include <drm/drm_vblank.h> 23 24 #include "hibmc_drm_drv.h" 25 #include "hibmc_drm_regs.h" 26 27 DEFINE_DRM_GEM_FOPS(hibmc_fops); 28 29 static irqreturn_t hibmc_drm_interrupt(int irq, void *arg) 30 { 31 struct drm_device *dev = (struct drm_device *)arg; 32 struct hibmc_drm_private *priv = 33 (struct hibmc_drm_private *)dev->dev_private; 34 u32 status; 35 36 status = readl(priv->mmio + HIBMC_RAW_INTERRUPT); 37 38 if (status & HIBMC_RAW_INTERRUPT_VBLANK(1)) { 39 writel(HIBMC_RAW_INTERRUPT_VBLANK(1), 40 priv->mmio + HIBMC_RAW_INTERRUPT); 41 drm_handle_vblank(dev, 0); 42 } 43 44 return IRQ_HANDLED; 45 } 46 47 static struct drm_driver hibmc_driver = { 48 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 49 .fops = &hibmc_fops, 50 .name = "hibmc", 51 .date = "20160828", 52 .desc = "hibmc drm driver", 53 .major = 1, 54 .minor = 0, 55 .debugfs_init = drm_vram_mm_debugfs_init, 56 .dumb_create = hibmc_dumb_create, 57 .dumb_map_offset = drm_gem_vram_driver_dumb_mmap_offset, 58 .gem_prime_mmap = drm_gem_prime_mmap, 59 .irq_handler = hibmc_drm_interrupt, 60 }; 61 62 static int __maybe_unused hibmc_pm_suspend(struct device *dev) 63 { 64 struct drm_device *drm_dev = dev_get_drvdata(dev); 65 66 return drm_mode_config_helper_suspend(drm_dev); 67 } 68 69 static int __maybe_unused hibmc_pm_resume(struct device *dev) 70 { 71 struct drm_device *drm_dev = dev_get_drvdata(dev); 72 73 return drm_mode_config_helper_resume(drm_dev); 74 } 75 76 static const struct dev_pm_ops hibmc_pm_ops = { 77 SET_SYSTEM_SLEEP_PM_OPS(hibmc_pm_suspend, 78 hibmc_pm_resume) 79 }; 80 81 static int hibmc_kms_init(struct hibmc_drm_private *priv) 82 { 83 int ret; 84 85 drm_mode_config_init(priv->dev); 86 priv->mode_config_initialized = true; 87 88 priv->dev->mode_config.min_width = 0; 89 priv->dev->mode_config.min_height = 0; 90 priv->dev->mode_config.max_width = 1920; 91 priv->dev->mode_config.max_height = 1200; 92 93 priv->dev->mode_config.fb_base = priv->fb_base; 94 priv->dev->mode_config.preferred_depth = 32; 95 priv->dev->mode_config.prefer_shadow = 1; 96 97 priv->dev->mode_config.funcs = (void *)&hibmc_mode_funcs; 98 99 ret = hibmc_de_init(priv); 100 if (ret) { 101 drm_err(priv->dev, "failed to init de: %d\n", ret); 102 return ret; 103 } 104 105 ret = hibmc_vdac_init(priv); 106 if (ret) { 107 drm_err(priv->dev, "failed to init vdac: %d\n", ret); 108 return ret; 109 } 110 111 return 0; 112 } 113 114 static void hibmc_kms_fini(struct hibmc_drm_private *priv) 115 { 116 if (priv->mode_config_initialized) { 117 drm_mode_config_cleanup(priv->dev); 118 priv->mode_config_initialized = false; 119 } 120 } 121 122 /* 123 * It can operate in one of three modes: 0, 1 or Sleep. 124 */ 125 void hibmc_set_power_mode(struct hibmc_drm_private *priv, 126 unsigned int power_mode) 127 { 128 unsigned int control_value = 0; 129 void __iomem *mmio = priv->mmio; 130 unsigned int input = 1; 131 132 if (power_mode > HIBMC_PW_MODE_CTL_MODE_SLEEP) 133 return; 134 135 if (power_mode == HIBMC_PW_MODE_CTL_MODE_SLEEP) 136 input = 0; 137 138 control_value = readl(mmio + HIBMC_POWER_MODE_CTRL); 139 control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK | 140 HIBMC_PW_MODE_CTL_OSC_INPUT_MASK); 141 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode); 142 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input); 143 writel(control_value, mmio + HIBMC_POWER_MODE_CTRL); 144 } 145 146 void hibmc_set_current_gate(struct hibmc_drm_private *priv, unsigned int gate) 147 { 148 unsigned int gate_reg; 149 unsigned int mode; 150 void __iomem *mmio = priv->mmio; 151 152 /* Get current power mode. */ 153 mode = (readl(mmio + HIBMC_POWER_MODE_CTRL) & 154 HIBMC_PW_MODE_CTL_MODE_MASK) >> HIBMC_PW_MODE_CTL_MODE_SHIFT; 155 156 switch (mode) { 157 case HIBMC_PW_MODE_CTL_MODE_MODE0: 158 gate_reg = HIBMC_MODE0_GATE; 159 break; 160 161 case HIBMC_PW_MODE_CTL_MODE_MODE1: 162 gate_reg = HIBMC_MODE1_GATE; 163 break; 164 165 default: 166 gate_reg = HIBMC_MODE0_GATE; 167 break; 168 } 169 writel(gate, mmio + gate_reg); 170 } 171 172 static void hibmc_hw_config(struct hibmc_drm_private *priv) 173 { 174 unsigned int reg; 175 176 /* On hardware reset, power mode 0 is default. */ 177 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0); 178 179 /* Enable display power gate & LOCALMEM power gate*/ 180 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 181 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 182 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 183 reg |= HIBMC_CURR_GATE_DISPLAY(1); 184 reg |= HIBMC_CURR_GATE_LOCALMEM(1); 185 186 hibmc_set_current_gate(priv, reg); 187 188 /* 189 * Reset the memory controller. If the memory controller 190 * is not reset in chip,the system might hang when sw accesses 191 * the memory.The memory should be resetted after 192 * changing the MXCLK. 193 */ 194 reg = readl(priv->mmio + HIBMC_MISC_CTRL); 195 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK; 196 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(0); 197 writel(reg, priv->mmio + HIBMC_MISC_CTRL); 198 199 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK; 200 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(1); 201 202 writel(reg, priv->mmio + HIBMC_MISC_CTRL); 203 } 204 205 static int hibmc_hw_map(struct hibmc_drm_private *priv) 206 { 207 struct drm_device *dev = priv->dev; 208 struct pci_dev *pdev = dev->pdev; 209 resource_size_t addr, size, ioaddr, iosize; 210 211 ioaddr = pci_resource_start(pdev, 1); 212 iosize = pci_resource_len(pdev, 1); 213 priv->mmio = devm_ioremap(dev->dev, ioaddr, iosize); 214 if (!priv->mmio) { 215 drm_err(dev, "Cannot map mmio region\n"); 216 return -ENOMEM; 217 } 218 219 addr = pci_resource_start(pdev, 0); 220 size = pci_resource_len(pdev, 0); 221 priv->fb_map = devm_ioremap(dev->dev, addr, size); 222 if (!priv->fb_map) { 223 drm_err(dev, "Cannot map framebuffer\n"); 224 return -ENOMEM; 225 } 226 priv->fb_base = addr; 227 priv->fb_size = size; 228 229 return 0; 230 } 231 232 static int hibmc_hw_init(struct hibmc_drm_private *priv) 233 { 234 int ret; 235 236 ret = hibmc_hw_map(priv); 237 if (ret) 238 return ret; 239 240 hibmc_hw_config(priv); 241 242 return 0; 243 } 244 245 static int hibmc_unload(struct drm_device *dev) 246 { 247 struct hibmc_drm_private *priv = dev->dev_private; 248 249 drm_atomic_helper_shutdown(dev); 250 251 if (dev->irq_enabled) 252 drm_irq_uninstall(dev); 253 254 pci_disable_msi(dev->pdev); 255 hibmc_kms_fini(priv); 256 hibmc_mm_fini(priv); 257 dev->dev_private = NULL; 258 return 0; 259 } 260 261 static int hibmc_load(struct drm_device *dev) 262 { 263 struct hibmc_drm_private *priv; 264 int ret; 265 266 priv = drmm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 267 if (!priv) { 268 drm_err(dev, "no memory to allocate for hibmc_drm_private\n"); 269 return -ENOMEM; 270 } 271 dev->dev_private = priv; 272 priv->dev = dev; 273 274 ret = hibmc_hw_init(priv); 275 if (ret) 276 goto err; 277 278 ret = hibmc_mm_init(priv); 279 if (ret) 280 goto err; 281 282 ret = hibmc_kms_init(priv); 283 if (ret) 284 goto err; 285 286 ret = drm_vblank_init(dev, dev->mode_config.num_crtc); 287 if (ret) { 288 drm_err(dev, "failed to initialize vblank: %d\n", ret); 289 goto err; 290 } 291 292 ret = pci_enable_msi(dev->pdev); 293 if (ret) { 294 drm_warn(dev, "enabling MSI failed: %d\n", ret); 295 } else { 296 ret = drm_irq_install(dev, dev->pdev->irq); 297 if (ret) 298 drm_warn(dev, "install irq failed: %d\n", ret); 299 } 300 301 /* reset all the states of crtc/plane/encoder/connector */ 302 drm_mode_config_reset(dev); 303 304 return 0; 305 306 err: 307 hibmc_unload(dev); 308 drm_err(dev, "failed to initialize drm driver: %d\n", ret); 309 return ret; 310 } 311 312 static int hibmc_pci_probe(struct pci_dev *pdev, 313 const struct pci_device_id *ent) 314 { 315 struct drm_device *dev; 316 int ret; 317 318 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 319 "hibmcdrmfb"); 320 if (ret) 321 return ret; 322 323 dev = drm_dev_alloc(&hibmc_driver, &pdev->dev); 324 if (IS_ERR(dev)) { 325 DRM_ERROR("failed to allocate drm_device\n"); 326 return PTR_ERR(dev); 327 } 328 329 dev->pdev = pdev; 330 pci_set_drvdata(pdev, dev); 331 332 ret = pci_enable_device(pdev); 333 if (ret) { 334 drm_err(dev, "failed to enable pci device: %d\n", ret); 335 goto err_free; 336 } 337 338 ret = hibmc_load(dev); 339 if (ret) { 340 drm_err(dev, "failed to load hibmc: %d\n", ret); 341 goto err_disable; 342 } 343 344 ret = drm_dev_register(dev, 0); 345 if (ret) { 346 drm_err(dev, "failed to register drv for userspace access: %d\n", 347 ret); 348 goto err_unload; 349 } 350 351 drm_fbdev_generic_setup(dev, dev->mode_config.preferred_depth); 352 353 return 0; 354 355 err_unload: 356 hibmc_unload(dev); 357 err_disable: 358 pci_disable_device(pdev); 359 err_free: 360 drm_dev_put(dev); 361 362 return ret; 363 } 364 365 static void hibmc_pci_remove(struct pci_dev *pdev) 366 { 367 struct drm_device *dev = pci_get_drvdata(pdev); 368 369 drm_dev_unregister(dev); 370 hibmc_unload(dev); 371 drm_dev_put(dev); 372 } 373 374 static struct pci_device_id hibmc_pci_table[] = { 375 { PCI_VDEVICE(HUAWEI, 0x1711) }, 376 {0,} 377 }; 378 379 static struct pci_driver hibmc_pci_driver = { 380 .name = "hibmc-drm", 381 .id_table = hibmc_pci_table, 382 .probe = hibmc_pci_probe, 383 .remove = hibmc_pci_remove, 384 .driver.pm = &hibmc_pm_ops, 385 }; 386 387 module_pci_driver(hibmc_pci_driver); 388 389 MODULE_DEVICE_TABLE(pci, hibmc_pci_table); 390 MODULE_AUTHOR("RongrongZou <zourongrong@huawei.com>"); 391 MODULE_DESCRIPTION("DRM Driver for Hisilicon Hibmc"); 392 MODULE_LICENSE("GPL v2"); 393