1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Hisilicon Hibmc SoC drm driver
3  *
4  * Based on the bochs drm driver.
5  *
6  * Copyright (c) 2016 Huawei Limited.
7  *
8  * Author:
9  *	Rongrong Zou <zourongrong@huawei.com>
10  *	Rongrong Zou <zourongrong@gmail.com>
11  *	Jianhua Li <lijianhua@huawei.com>
12  */
13 
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 
17 #include <drm/drm_aperture.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_drv.h>
20 #include <drm/drm_gem_framebuffer_helper.h>
21 #include <drm/drm_gem_vram_helper.h>
22 #include <drm/drm_irq.h>
23 #include <drm/drm_managed.h>
24 #include <drm/drm_vblank.h>
25 
26 #include "hibmc_drm_drv.h"
27 #include "hibmc_drm_regs.h"
28 
29 DEFINE_DRM_GEM_FOPS(hibmc_fops);
30 
31 static irqreturn_t hibmc_drm_interrupt(int irq, void *arg)
32 {
33 	struct drm_device *dev = (struct drm_device *)arg;
34 	struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
35 	u32 status;
36 
37 	status = readl(priv->mmio + HIBMC_RAW_INTERRUPT);
38 
39 	if (status & HIBMC_RAW_INTERRUPT_VBLANK(1)) {
40 		writel(HIBMC_RAW_INTERRUPT_VBLANK(1),
41 		       priv->mmio + HIBMC_RAW_INTERRUPT);
42 		drm_handle_vblank(dev, 0);
43 	}
44 
45 	return IRQ_HANDLED;
46 }
47 
48 static int hibmc_dumb_create(struct drm_file *file, struct drm_device *dev,
49 			     struct drm_mode_create_dumb *args)
50 {
51 	return drm_gem_vram_fill_create_dumb(file, dev, 0, 128, args);
52 }
53 
54 static const struct drm_driver hibmc_driver = {
55 	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
56 	.fops			= &hibmc_fops,
57 	.name			= "hibmc",
58 	.date			= "20160828",
59 	.desc			= "hibmc drm driver",
60 	.major			= 1,
61 	.minor			= 0,
62 	.debugfs_init		= drm_vram_mm_debugfs_init,
63 	.dumb_create            = hibmc_dumb_create,
64 	.dumb_map_offset        = drm_gem_ttm_dumb_map_offset,
65 	.gem_prime_mmap		= drm_gem_prime_mmap,
66 	.irq_handler		= hibmc_drm_interrupt,
67 };
68 
69 static int __maybe_unused hibmc_pm_suspend(struct device *dev)
70 {
71 	struct drm_device *drm_dev = dev_get_drvdata(dev);
72 
73 	return drm_mode_config_helper_suspend(drm_dev);
74 }
75 
76 static int  __maybe_unused hibmc_pm_resume(struct device *dev)
77 {
78 	struct drm_device *drm_dev = dev_get_drvdata(dev);
79 
80 	return drm_mode_config_helper_resume(drm_dev);
81 }
82 
83 static const struct dev_pm_ops hibmc_pm_ops = {
84 	SET_SYSTEM_SLEEP_PM_OPS(hibmc_pm_suspend,
85 				hibmc_pm_resume)
86 };
87 
88 static const struct drm_mode_config_funcs hibmc_mode_funcs = {
89 	.mode_valid = drm_vram_helper_mode_valid,
90 	.atomic_check = drm_atomic_helper_check,
91 	.atomic_commit = drm_atomic_helper_commit,
92 	.fb_create = drm_gem_fb_create,
93 };
94 
95 static int hibmc_kms_init(struct hibmc_drm_private *priv)
96 {
97 	struct drm_device *dev = &priv->dev;
98 	int ret;
99 
100 	ret = drmm_mode_config_init(dev);
101 	if (ret)
102 		return ret;
103 
104 	dev->mode_config.min_width = 0;
105 	dev->mode_config.min_height = 0;
106 	dev->mode_config.max_width = 1920;
107 	dev->mode_config.max_height = 1200;
108 
109 	dev->mode_config.fb_base = priv->fb_base;
110 	dev->mode_config.preferred_depth = 32;
111 	dev->mode_config.prefer_shadow = 1;
112 
113 	dev->mode_config.funcs = (void *)&hibmc_mode_funcs;
114 
115 	ret = hibmc_de_init(priv);
116 	if (ret) {
117 		drm_err(dev, "failed to init de: %d\n", ret);
118 		return ret;
119 	}
120 
121 	ret = hibmc_vdac_init(priv);
122 	if (ret) {
123 		drm_err(dev, "failed to init vdac: %d\n", ret);
124 		return ret;
125 	}
126 
127 	return 0;
128 }
129 
130 /*
131  * It can operate in one of three modes: 0, 1 or Sleep.
132  */
133 void hibmc_set_power_mode(struct hibmc_drm_private *priv, u32 power_mode)
134 {
135 	u32 control_value = 0;
136 	void __iomem   *mmio = priv->mmio;
137 	u32 input = 1;
138 
139 	if (power_mode > HIBMC_PW_MODE_CTL_MODE_SLEEP)
140 		return;
141 
142 	if (power_mode == HIBMC_PW_MODE_CTL_MODE_SLEEP)
143 		input = 0;
144 
145 	control_value = readl(mmio + HIBMC_POWER_MODE_CTRL);
146 	control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK |
147 			   HIBMC_PW_MODE_CTL_OSC_INPUT_MASK);
148 	control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode);
149 	control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input);
150 	writel(control_value, mmio + HIBMC_POWER_MODE_CTRL);
151 }
152 
153 void hibmc_set_current_gate(struct hibmc_drm_private *priv, unsigned int gate)
154 {
155 	u32 gate_reg;
156 	u32 mode;
157 	void __iomem   *mmio = priv->mmio;
158 
159 	/* Get current power mode. */
160 	mode = (readl(mmio + HIBMC_POWER_MODE_CTRL) &
161 		HIBMC_PW_MODE_CTL_MODE_MASK) >> HIBMC_PW_MODE_CTL_MODE_SHIFT;
162 
163 	switch (mode) {
164 	case HIBMC_PW_MODE_CTL_MODE_MODE0:
165 		gate_reg = HIBMC_MODE0_GATE;
166 		break;
167 
168 	case HIBMC_PW_MODE_CTL_MODE_MODE1:
169 		gate_reg = HIBMC_MODE1_GATE;
170 		break;
171 
172 	default:
173 		gate_reg = HIBMC_MODE0_GATE;
174 		break;
175 	}
176 	writel(gate, mmio + gate_reg);
177 }
178 
179 static void hibmc_hw_config(struct hibmc_drm_private *priv)
180 {
181 	u32 reg;
182 
183 	/* On hardware reset, power mode 0 is default. */
184 	hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
185 
186 	/* Enable display power gate & LOCALMEM power gate*/
187 	reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
188 	reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
189 	reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
190 	reg |= HIBMC_CURR_GATE_DISPLAY(1);
191 	reg |= HIBMC_CURR_GATE_LOCALMEM(1);
192 
193 	hibmc_set_current_gate(priv, reg);
194 
195 	/*
196 	 * Reset the memory controller. If the memory controller
197 	 * is not reset in chip,the system might hang when sw accesses
198 	 * the memory.The memory should be resetted after
199 	 * changing the MXCLK.
200 	 */
201 	reg = readl(priv->mmio + HIBMC_MISC_CTRL);
202 	reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK;
203 	reg |= HIBMC_MSCCTL_LOCALMEM_RESET(0);
204 	writel(reg, priv->mmio + HIBMC_MISC_CTRL);
205 
206 	reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK;
207 	reg |= HIBMC_MSCCTL_LOCALMEM_RESET(1);
208 
209 	writel(reg, priv->mmio + HIBMC_MISC_CTRL);
210 }
211 
212 static int hibmc_hw_map(struct hibmc_drm_private *priv)
213 {
214 	struct drm_device *dev = &priv->dev;
215 	struct pci_dev *pdev = to_pci_dev(dev->dev);
216 	resource_size_t addr, size, ioaddr, iosize;
217 
218 	ioaddr = pci_resource_start(pdev, 1);
219 	iosize = pci_resource_len(pdev, 1);
220 	priv->mmio = devm_ioremap(dev->dev, ioaddr, iosize);
221 	if (!priv->mmio) {
222 		drm_err(dev, "Cannot map mmio region\n");
223 		return -ENOMEM;
224 	}
225 
226 	addr = pci_resource_start(pdev, 0);
227 	size = pci_resource_len(pdev, 0);
228 	priv->fb_map = devm_ioremap(dev->dev, addr, size);
229 	if (!priv->fb_map) {
230 		drm_err(dev, "Cannot map framebuffer\n");
231 		return -ENOMEM;
232 	}
233 	priv->fb_base = addr;
234 	priv->fb_size = size;
235 
236 	return 0;
237 }
238 
239 static int hibmc_hw_init(struct hibmc_drm_private *priv)
240 {
241 	int ret;
242 
243 	ret = hibmc_hw_map(priv);
244 	if (ret)
245 		return ret;
246 
247 	hibmc_hw_config(priv);
248 
249 	return 0;
250 }
251 
252 static int hibmc_unload(struct drm_device *dev)
253 {
254 	drm_atomic_helper_shutdown(dev);
255 
256 	if (dev->irq_enabled)
257 		drm_irq_uninstall(dev);
258 
259 	pci_disable_msi(to_pci_dev(dev->dev));
260 
261 	return 0;
262 }
263 
264 static int hibmc_load(struct drm_device *dev)
265 {
266 	struct pci_dev *pdev = to_pci_dev(dev->dev);
267 	struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
268 	int ret;
269 
270 	ret = hibmc_hw_init(priv);
271 	if (ret)
272 		goto err;
273 
274 	ret = drmm_vram_helper_init(dev, pci_resource_start(pdev, 0), priv->fb_size);
275 	if (ret) {
276 		drm_err(dev, "Error initializing VRAM MM; %d\n", ret);
277 		goto err;
278 	}
279 
280 	ret = hibmc_kms_init(priv);
281 	if (ret)
282 		goto err;
283 
284 	ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
285 	if (ret) {
286 		drm_err(dev, "failed to initialize vblank: %d\n", ret);
287 		goto err;
288 	}
289 
290 	ret = pci_enable_msi(pdev);
291 	if (ret) {
292 		drm_warn(dev, "enabling MSI failed: %d\n", ret);
293 	} else {
294 		ret = drm_irq_install(dev, pdev->irq);
295 		if (ret)
296 			drm_warn(dev, "install irq failed: %d\n", ret);
297 	}
298 
299 	/* reset all the states of crtc/plane/encoder/connector */
300 	drm_mode_config_reset(dev);
301 
302 	return 0;
303 
304 err:
305 	hibmc_unload(dev);
306 	drm_err(dev, "failed to initialize drm driver: %d\n", ret);
307 	return ret;
308 }
309 
310 static int hibmc_pci_probe(struct pci_dev *pdev,
311 			   const struct pci_device_id *ent)
312 {
313 	struct hibmc_drm_private *priv;
314 	struct drm_device *dev;
315 	int ret;
316 
317 	ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "hibmcdrmfb");
318 	if (ret)
319 		return ret;
320 
321 	priv = devm_drm_dev_alloc(&pdev->dev, &hibmc_driver,
322 				  struct hibmc_drm_private, dev);
323 	if (IS_ERR(priv)) {
324 		DRM_ERROR("failed to allocate drm_device\n");
325 		return PTR_ERR(priv);
326 	}
327 
328 	dev = &priv->dev;
329 	pci_set_drvdata(pdev, dev);
330 
331 	ret = pcim_enable_device(pdev);
332 	if (ret) {
333 		drm_err(dev, "failed to enable pci device: %d\n", ret);
334 		goto err_return;
335 	}
336 
337 	ret = hibmc_load(dev);
338 	if (ret) {
339 		drm_err(dev, "failed to load hibmc: %d\n", ret);
340 		goto err_return;
341 	}
342 
343 	ret = drm_dev_register(dev, 0);
344 	if (ret) {
345 		drm_err(dev, "failed to register drv for userspace access: %d\n",
346 			  ret);
347 		goto err_unload;
348 	}
349 
350 	drm_fbdev_generic_setup(dev, dev->mode_config.preferred_depth);
351 
352 	return 0;
353 
354 err_unload:
355 	hibmc_unload(dev);
356 err_return:
357 	return ret;
358 }
359 
360 static void hibmc_pci_remove(struct pci_dev *pdev)
361 {
362 	struct drm_device *dev = pci_get_drvdata(pdev);
363 
364 	drm_dev_unregister(dev);
365 	hibmc_unload(dev);
366 }
367 
368 static const struct pci_device_id hibmc_pci_table[] = {
369 	{ PCI_VDEVICE(HUAWEI, 0x1711) },
370 	{0,}
371 };
372 
373 static struct pci_driver hibmc_pci_driver = {
374 	.name =		"hibmc-drm",
375 	.id_table =	hibmc_pci_table,
376 	.probe =	hibmc_pci_probe,
377 	.remove =	hibmc_pci_remove,
378 	.driver.pm =    &hibmc_pm_ops,
379 };
380 
381 module_pci_driver(hibmc_pci_driver);
382 
383 MODULE_DEVICE_TABLE(pci, hibmc_pci_table);
384 MODULE_AUTHOR("RongrongZou <zourongrong@huawei.com>");
385 MODULE_DESCRIPTION("DRM Driver for Hisilicon Hibmc");
386 MODULE_LICENSE("GPL v2");
387