1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Hisilicon Hibmc SoC drm driver 3 * 4 * Based on the bochs drm driver. 5 * 6 * Copyright (c) 2016 Huawei Limited. 7 * 8 * Author: 9 * Rongrong Zou <zourongrong@huawei.com> 10 * Rongrong Zou <zourongrong@gmail.com> 11 * Jianhua Li <lijianhua@huawei.com> 12 */ 13 14 #include <linux/console.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_drv.h> 20 #include <drm/drm_gem_vram_helper.h> 21 #include <drm/drm_irq.h> 22 #include <drm/drm_print.h> 23 #include <drm/drm_probe_helper.h> 24 #include <drm/drm_vblank.h> 25 26 #include "hibmc_drm_drv.h" 27 #include "hibmc_drm_regs.h" 28 29 static const struct file_operations hibmc_fops = { 30 .owner = THIS_MODULE, 31 DRM_VRAM_MM_FILE_OPERATIONS 32 }; 33 34 static irqreturn_t hibmc_drm_interrupt(int irq, void *arg) 35 { 36 struct drm_device *dev = (struct drm_device *)arg; 37 struct hibmc_drm_private *priv = 38 (struct hibmc_drm_private *)dev->dev_private; 39 u32 status; 40 41 status = readl(priv->mmio + HIBMC_RAW_INTERRUPT); 42 43 if (status & HIBMC_RAW_INTERRUPT_VBLANK(1)) { 44 writel(HIBMC_RAW_INTERRUPT_VBLANK(1), 45 priv->mmio + HIBMC_RAW_INTERRUPT); 46 drm_handle_vblank(dev, 0); 47 } 48 49 return IRQ_HANDLED; 50 } 51 52 static struct drm_driver hibmc_driver = { 53 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 54 .fops = &hibmc_fops, 55 .name = "hibmc", 56 .date = "20160828", 57 .desc = "hibmc drm driver", 58 .major = 1, 59 .minor = 0, 60 .dumb_create = hibmc_dumb_create, 61 .dumb_map_offset = drm_gem_vram_driver_dumb_mmap_offset, 62 .gem_prime_mmap = drm_gem_prime_mmap, 63 .irq_handler = hibmc_drm_interrupt, 64 }; 65 66 static int __maybe_unused hibmc_pm_suspend(struct device *dev) 67 { 68 struct drm_device *drm_dev = dev_get_drvdata(dev); 69 70 return drm_mode_config_helper_suspend(drm_dev); 71 } 72 73 static int __maybe_unused hibmc_pm_resume(struct device *dev) 74 { 75 struct drm_device *drm_dev = dev_get_drvdata(dev); 76 77 return drm_mode_config_helper_resume(drm_dev); 78 } 79 80 static const struct dev_pm_ops hibmc_pm_ops = { 81 SET_SYSTEM_SLEEP_PM_OPS(hibmc_pm_suspend, 82 hibmc_pm_resume) 83 }; 84 85 static int hibmc_kms_init(struct hibmc_drm_private *priv) 86 { 87 int ret; 88 89 drm_mode_config_init(priv->dev); 90 priv->mode_config_initialized = true; 91 92 priv->dev->mode_config.min_width = 0; 93 priv->dev->mode_config.min_height = 0; 94 priv->dev->mode_config.max_width = 1920; 95 priv->dev->mode_config.max_height = 1440; 96 97 priv->dev->mode_config.fb_base = priv->fb_base; 98 priv->dev->mode_config.preferred_depth = 24; 99 priv->dev->mode_config.prefer_shadow = 0; 100 101 priv->dev->mode_config.funcs = (void *)&hibmc_mode_funcs; 102 103 ret = hibmc_de_init(priv); 104 if (ret) { 105 DRM_ERROR("failed to init de: %d\n", ret); 106 return ret; 107 } 108 109 ret = hibmc_vdac_init(priv); 110 if (ret) { 111 DRM_ERROR("failed to init vdac: %d\n", ret); 112 return ret; 113 } 114 115 return 0; 116 } 117 118 static void hibmc_kms_fini(struct hibmc_drm_private *priv) 119 { 120 if (priv->mode_config_initialized) { 121 drm_mode_config_cleanup(priv->dev); 122 priv->mode_config_initialized = false; 123 } 124 } 125 126 /* 127 * It can operate in one of three modes: 0, 1 or Sleep. 128 */ 129 void hibmc_set_power_mode(struct hibmc_drm_private *priv, 130 unsigned int power_mode) 131 { 132 unsigned int control_value = 0; 133 void __iomem *mmio = priv->mmio; 134 unsigned int input = 1; 135 136 if (power_mode > HIBMC_PW_MODE_CTL_MODE_SLEEP) 137 return; 138 139 if (power_mode == HIBMC_PW_MODE_CTL_MODE_SLEEP) 140 input = 0; 141 142 control_value = readl(mmio + HIBMC_POWER_MODE_CTRL); 143 control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK | 144 HIBMC_PW_MODE_CTL_OSC_INPUT_MASK); 145 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode); 146 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input); 147 writel(control_value, mmio + HIBMC_POWER_MODE_CTRL); 148 } 149 150 void hibmc_set_current_gate(struct hibmc_drm_private *priv, unsigned int gate) 151 { 152 unsigned int gate_reg; 153 unsigned int mode; 154 void __iomem *mmio = priv->mmio; 155 156 /* Get current power mode. */ 157 mode = (readl(mmio + HIBMC_POWER_MODE_CTRL) & 158 HIBMC_PW_MODE_CTL_MODE_MASK) >> HIBMC_PW_MODE_CTL_MODE_SHIFT; 159 160 switch (mode) { 161 case HIBMC_PW_MODE_CTL_MODE_MODE0: 162 gate_reg = HIBMC_MODE0_GATE; 163 break; 164 165 case HIBMC_PW_MODE_CTL_MODE_MODE1: 166 gate_reg = HIBMC_MODE1_GATE; 167 break; 168 169 default: 170 gate_reg = HIBMC_MODE0_GATE; 171 break; 172 } 173 writel(gate, mmio + gate_reg); 174 } 175 176 static void hibmc_hw_config(struct hibmc_drm_private *priv) 177 { 178 unsigned int reg; 179 180 /* On hardware reset, power mode 0 is default. */ 181 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0); 182 183 /* Enable display power gate & LOCALMEM power gate*/ 184 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 185 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 186 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 187 reg |= HIBMC_CURR_GATE_DISPLAY(1); 188 reg |= HIBMC_CURR_GATE_LOCALMEM(1); 189 190 hibmc_set_current_gate(priv, reg); 191 192 /* 193 * Reset the memory controller. If the memory controller 194 * is not reset in chip,the system might hang when sw accesses 195 * the memory.The memory should be resetted after 196 * changing the MXCLK. 197 */ 198 reg = readl(priv->mmio + HIBMC_MISC_CTRL); 199 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK; 200 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(0); 201 writel(reg, priv->mmio + HIBMC_MISC_CTRL); 202 203 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK; 204 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(1); 205 206 writel(reg, priv->mmio + HIBMC_MISC_CTRL); 207 } 208 209 static int hibmc_hw_map(struct hibmc_drm_private *priv) 210 { 211 struct drm_device *dev = priv->dev; 212 struct pci_dev *pdev = dev->pdev; 213 resource_size_t addr, size, ioaddr, iosize; 214 215 ioaddr = pci_resource_start(pdev, 1); 216 iosize = pci_resource_len(pdev, 1); 217 priv->mmio = devm_ioremap_nocache(dev->dev, ioaddr, iosize); 218 if (!priv->mmio) { 219 DRM_ERROR("Cannot map mmio region\n"); 220 return -ENOMEM; 221 } 222 223 addr = pci_resource_start(pdev, 0); 224 size = pci_resource_len(pdev, 0); 225 priv->fb_map = devm_ioremap(dev->dev, addr, size); 226 if (!priv->fb_map) { 227 DRM_ERROR("Cannot map framebuffer\n"); 228 return -ENOMEM; 229 } 230 priv->fb_base = addr; 231 priv->fb_size = size; 232 233 return 0; 234 } 235 236 static int hibmc_hw_init(struct hibmc_drm_private *priv) 237 { 238 int ret; 239 240 ret = hibmc_hw_map(priv); 241 if (ret) 242 return ret; 243 244 hibmc_hw_config(priv); 245 246 return 0; 247 } 248 249 static int hibmc_unload(struct drm_device *dev) 250 { 251 struct hibmc_drm_private *priv = dev->dev_private; 252 253 hibmc_fbdev_fini(priv); 254 255 drm_atomic_helper_shutdown(dev); 256 257 if (dev->irq_enabled) 258 drm_irq_uninstall(dev); 259 if (priv->msi_enabled) 260 pci_disable_msi(dev->pdev); 261 262 hibmc_kms_fini(priv); 263 hibmc_mm_fini(priv); 264 dev->dev_private = NULL; 265 return 0; 266 } 267 268 static int hibmc_load(struct drm_device *dev) 269 { 270 struct hibmc_drm_private *priv; 271 int ret; 272 273 priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL); 274 if (!priv) { 275 DRM_ERROR("no memory to allocate for hibmc_drm_private\n"); 276 return -ENOMEM; 277 } 278 dev->dev_private = priv; 279 priv->dev = dev; 280 281 ret = hibmc_hw_init(priv); 282 if (ret) 283 goto err; 284 285 ret = hibmc_mm_init(priv); 286 if (ret) 287 goto err; 288 289 ret = hibmc_kms_init(priv); 290 if (ret) 291 goto err; 292 293 ret = drm_vblank_init(dev, dev->mode_config.num_crtc); 294 if (ret) { 295 DRM_ERROR("failed to initialize vblank: %d\n", ret); 296 goto err; 297 } 298 299 priv->msi_enabled = 0; 300 ret = pci_enable_msi(dev->pdev); 301 if (ret) { 302 DRM_WARN("enabling MSI failed: %d\n", ret); 303 } else { 304 priv->msi_enabled = 1; 305 ret = drm_irq_install(dev, dev->pdev->irq); 306 if (ret) 307 DRM_WARN("install irq failed: %d\n", ret); 308 } 309 310 /* reset all the states of crtc/plane/encoder/connector */ 311 drm_mode_config_reset(dev); 312 313 ret = hibmc_fbdev_init(priv); 314 if (ret) { 315 DRM_ERROR("failed to initialize fbdev: %d\n", ret); 316 goto err; 317 } 318 319 return 0; 320 321 err: 322 hibmc_unload(dev); 323 DRM_ERROR("failed to initialize drm driver: %d\n", ret); 324 return ret; 325 } 326 327 static int hibmc_pci_probe(struct pci_dev *pdev, 328 const struct pci_device_id *ent) 329 { 330 struct drm_device *dev; 331 int ret; 332 333 dev = drm_dev_alloc(&hibmc_driver, &pdev->dev); 334 if (IS_ERR(dev)) { 335 DRM_ERROR("failed to allocate drm_device\n"); 336 return PTR_ERR(dev); 337 } 338 339 dev->pdev = pdev; 340 pci_set_drvdata(pdev, dev); 341 342 ret = pci_enable_device(pdev); 343 if (ret) { 344 DRM_ERROR("failed to enable pci device: %d\n", ret); 345 goto err_free; 346 } 347 348 ret = hibmc_load(dev); 349 if (ret) { 350 DRM_ERROR("failed to load hibmc: %d\n", ret); 351 goto err_disable; 352 } 353 354 ret = drm_dev_register(dev, 0); 355 if (ret) { 356 DRM_ERROR("failed to register drv for userspace access: %d\n", 357 ret); 358 goto err_unload; 359 } 360 return 0; 361 362 err_unload: 363 hibmc_unload(dev); 364 err_disable: 365 pci_disable_device(pdev); 366 err_free: 367 drm_dev_put(dev); 368 369 return ret; 370 } 371 372 static void hibmc_pci_remove(struct pci_dev *pdev) 373 { 374 struct drm_device *dev = pci_get_drvdata(pdev); 375 376 drm_dev_unregister(dev); 377 hibmc_unload(dev); 378 drm_dev_put(dev); 379 } 380 381 static struct pci_device_id hibmc_pci_table[] = { 382 { PCI_VDEVICE(HUAWEI, 0x1711) }, 383 {0,} 384 }; 385 386 static struct pci_driver hibmc_pci_driver = { 387 .name = "hibmc-drm", 388 .id_table = hibmc_pci_table, 389 .probe = hibmc_pci_probe, 390 .remove = hibmc_pci_remove, 391 .driver.pm = &hibmc_pm_ops, 392 }; 393 394 module_pci_driver(hibmc_pci_driver); 395 396 MODULE_DEVICE_TABLE(pci, hibmc_pci_table); 397 MODULE_AUTHOR("RongrongZou <zourongrong@huawei.com>"); 398 MODULE_DESCRIPTION("DRM Driver for Hisilicon Hibmc"); 399 MODULE_LICENSE("GPL v2"); 400