1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Hisilicon Hibmc SoC drm driver 3 * 4 * Based on the bochs drm driver. 5 * 6 * Copyright (c) 2016 Huawei Limited. 7 * 8 * Author: 9 * Rongrong Zou <zourongrong@huawei.com> 10 * Rongrong Zou <zourongrong@gmail.com> 11 * Jianhua Li <lijianhua@huawei.com> 12 */ 13 14 #include <linux/console.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_drv.h> 20 #include <drm/drm_fb_helper.h> 21 #include <drm/drm_gem_vram_helper.h> 22 #include <drm/drm_irq.h> 23 #include <drm/drm_print.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_vblank.h> 26 27 #include "hibmc_drm_drv.h" 28 #include "hibmc_drm_regs.h" 29 30 DEFINE_DRM_GEM_FOPS(hibmc_fops); 31 32 static irqreturn_t hibmc_drm_interrupt(int irq, void *arg) 33 { 34 struct drm_device *dev = (struct drm_device *)arg; 35 struct hibmc_drm_private *priv = 36 (struct hibmc_drm_private *)dev->dev_private; 37 u32 status; 38 39 status = readl(priv->mmio + HIBMC_RAW_INTERRUPT); 40 41 if (status & HIBMC_RAW_INTERRUPT_VBLANK(1)) { 42 writel(HIBMC_RAW_INTERRUPT_VBLANK(1), 43 priv->mmio + HIBMC_RAW_INTERRUPT); 44 drm_handle_vblank(dev, 0); 45 } 46 47 return IRQ_HANDLED; 48 } 49 50 static struct drm_driver hibmc_driver = { 51 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 52 .fops = &hibmc_fops, 53 .name = "hibmc", 54 .date = "20160828", 55 .desc = "hibmc drm driver", 56 .major = 1, 57 .minor = 0, 58 .debugfs_init = drm_vram_mm_debugfs_init, 59 .dumb_create = hibmc_dumb_create, 60 .dumb_map_offset = drm_gem_vram_driver_dumb_mmap_offset, 61 .gem_prime_mmap = drm_gem_prime_mmap, 62 .irq_handler = hibmc_drm_interrupt, 63 }; 64 65 static int __maybe_unused hibmc_pm_suspend(struct device *dev) 66 { 67 struct drm_device *drm_dev = dev_get_drvdata(dev); 68 69 return drm_mode_config_helper_suspend(drm_dev); 70 } 71 72 static int __maybe_unused hibmc_pm_resume(struct device *dev) 73 { 74 struct drm_device *drm_dev = dev_get_drvdata(dev); 75 76 return drm_mode_config_helper_resume(drm_dev); 77 } 78 79 static const struct dev_pm_ops hibmc_pm_ops = { 80 SET_SYSTEM_SLEEP_PM_OPS(hibmc_pm_suspend, 81 hibmc_pm_resume) 82 }; 83 84 static int hibmc_kms_init(struct hibmc_drm_private *priv) 85 { 86 int ret; 87 88 drm_mode_config_init(priv->dev); 89 priv->mode_config_initialized = true; 90 91 priv->dev->mode_config.min_width = 0; 92 priv->dev->mode_config.min_height = 0; 93 priv->dev->mode_config.max_width = 1920; 94 priv->dev->mode_config.max_height = 1200; 95 96 priv->dev->mode_config.fb_base = priv->fb_base; 97 priv->dev->mode_config.preferred_depth = 24; 98 priv->dev->mode_config.prefer_shadow = 1; 99 100 priv->dev->mode_config.funcs = (void *)&hibmc_mode_funcs; 101 102 ret = hibmc_de_init(priv); 103 if (ret) { 104 DRM_ERROR("failed to init de: %d\n", ret); 105 return ret; 106 } 107 108 ret = hibmc_vdac_init(priv); 109 if (ret) { 110 DRM_ERROR("failed to init vdac: %d\n", ret); 111 return ret; 112 } 113 114 return 0; 115 } 116 117 static void hibmc_kms_fini(struct hibmc_drm_private *priv) 118 { 119 if (priv->mode_config_initialized) { 120 drm_mode_config_cleanup(priv->dev); 121 priv->mode_config_initialized = false; 122 } 123 } 124 125 /* 126 * It can operate in one of three modes: 0, 1 or Sleep. 127 */ 128 void hibmc_set_power_mode(struct hibmc_drm_private *priv, 129 unsigned int power_mode) 130 { 131 unsigned int control_value = 0; 132 void __iomem *mmio = priv->mmio; 133 unsigned int input = 1; 134 135 if (power_mode > HIBMC_PW_MODE_CTL_MODE_SLEEP) 136 return; 137 138 if (power_mode == HIBMC_PW_MODE_CTL_MODE_SLEEP) 139 input = 0; 140 141 control_value = readl(mmio + HIBMC_POWER_MODE_CTRL); 142 control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK | 143 HIBMC_PW_MODE_CTL_OSC_INPUT_MASK); 144 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode); 145 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input); 146 writel(control_value, mmio + HIBMC_POWER_MODE_CTRL); 147 } 148 149 void hibmc_set_current_gate(struct hibmc_drm_private *priv, unsigned int gate) 150 { 151 unsigned int gate_reg; 152 unsigned int mode; 153 void __iomem *mmio = priv->mmio; 154 155 /* Get current power mode. */ 156 mode = (readl(mmio + HIBMC_POWER_MODE_CTRL) & 157 HIBMC_PW_MODE_CTL_MODE_MASK) >> HIBMC_PW_MODE_CTL_MODE_SHIFT; 158 159 switch (mode) { 160 case HIBMC_PW_MODE_CTL_MODE_MODE0: 161 gate_reg = HIBMC_MODE0_GATE; 162 break; 163 164 case HIBMC_PW_MODE_CTL_MODE_MODE1: 165 gate_reg = HIBMC_MODE1_GATE; 166 break; 167 168 default: 169 gate_reg = HIBMC_MODE0_GATE; 170 break; 171 } 172 writel(gate, mmio + gate_reg); 173 } 174 175 static void hibmc_hw_config(struct hibmc_drm_private *priv) 176 { 177 unsigned int reg; 178 179 /* On hardware reset, power mode 0 is default. */ 180 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0); 181 182 /* Enable display power gate & LOCALMEM power gate*/ 183 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 184 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 185 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 186 reg |= HIBMC_CURR_GATE_DISPLAY(1); 187 reg |= HIBMC_CURR_GATE_LOCALMEM(1); 188 189 hibmc_set_current_gate(priv, reg); 190 191 /* 192 * Reset the memory controller. If the memory controller 193 * is not reset in chip,the system might hang when sw accesses 194 * the memory.The memory should be resetted after 195 * changing the MXCLK. 196 */ 197 reg = readl(priv->mmio + HIBMC_MISC_CTRL); 198 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK; 199 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(0); 200 writel(reg, priv->mmio + HIBMC_MISC_CTRL); 201 202 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK; 203 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(1); 204 205 writel(reg, priv->mmio + HIBMC_MISC_CTRL); 206 } 207 208 static int hibmc_hw_map(struct hibmc_drm_private *priv) 209 { 210 struct drm_device *dev = priv->dev; 211 struct pci_dev *pdev = dev->pdev; 212 resource_size_t addr, size, ioaddr, iosize; 213 214 ioaddr = pci_resource_start(pdev, 1); 215 iosize = pci_resource_len(pdev, 1); 216 priv->mmio = devm_ioremap(dev->dev, ioaddr, iosize); 217 if (!priv->mmio) { 218 DRM_ERROR("Cannot map mmio region\n"); 219 return -ENOMEM; 220 } 221 222 addr = pci_resource_start(pdev, 0); 223 size = pci_resource_len(pdev, 0); 224 priv->fb_map = devm_ioremap(dev->dev, addr, size); 225 if (!priv->fb_map) { 226 DRM_ERROR("Cannot map framebuffer\n"); 227 return -ENOMEM; 228 } 229 priv->fb_base = addr; 230 priv->fb_size = size; 231 232 return 0; 233 } 234 235 static int hibmc_hw_init(struct hibmc_drm_private *priv) 236 { 237 int ret; 238 239 ret = hibmc_hw_map(priv); 240 if (ret) 241 return ret; 242 243 hibmc_hw_config(priv); 244 245 return 0; 246 } 247 248 static int hibmc_unload(struct drm_device *dev) 249 { 250 struct hibmc_drm_private *priv = dev->dev_private; 251 252 drm_atomic_helper_shutdown(dev); 253 254 if (dev->irq_enabled) 255 drm_irq_uninstall(dev); 256 if (priv->msi_enabled) 257 pci_disable_msi(dev->pdev); 258 259 hibmc_kms_fini(priv); 260 hibmc_mm_fini(priv); 261 dev->dev_private = NULL; 262 return 0; 263 } 264 265 static int hibmc_load(struct drm_device *dev) 266 { 267 struct hibmc_drm_private *priv; 268 int ret; 269 270 priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL); 271 if (!priv) { 272 DRM_ERROR("no memory to allocate for hibmc_drm_private\n"); 273 return -ENOMEM; 274 } 275 dev->dev_private = priv; 276 priv->dev = dev; 277 278 ret = hibmc_hw_init(priv); 279 if (ret) 280 goto err; 281 282 ret = hibmc_mm_init(priv); 283 if (ret) 284 goto err; 285 286 ret = hibmc_kms_init(priv); 287 if (ret) 288 goto err; 289 290 ret = drm_vblank_init(dev, dev->mode_config.num_crtc); 291 if (ret) { 292 DRM_ERROR("failed to initialize vblank: %d\n", ret); 293 goto err; 294 } 295 296 priv->msi_enabled = 0; 297 ret = pci_enable_msi(dev->pdev); 298 if (ret) { 299 DRM_WARN("enabling MSI failed: %d\n", ret); 300 } else { 301 priv->msi_enabled = 1; 302 ret = drm_irq_install(dev, dev->pdev->irq); 303 if (ret) 304 DRM_WARN("install irq failed: %d\n", ret); 305 } 306 307 /* reset all the states of crtc/plane/encoder/connector */ 308 drm_mode_config_reset(dev); 309 310 ret = drm_fbdev_generic_setup(dev, 16); 311 if (ret) { 312 DRM_ERROR("failed to initialize fbdev: %d\n", ret); 313 goto err; 314 } 315 316 return 0; 317 318 err: 319 hibmc_unload(dev); 320 DRM_ERROR("failed to initialize drm driver: %d\n", ret); 321 return ret; 322 } 323 324 static int hibmc_pci_probe(struct pci_dev *pdev, 325 const struct pci_device_id *ent) 326 { 327 struct drm_device *dev; 328 int ret; 329 330 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 331 "hibmcdrmfb"); 332 if (ret) 333 return ret; 334 335 dev = drm_dev_alloc(&hibmc_driver, &pdev->dev); 336 if (IS_ERR(dev)) { 337 DRM_ERROR("failed to allocate drm_device\n"); 338 return PTR_ERR(dev); 339 } 340 341 dev->pdev = pdev; 342 pci_set_drvdata(pdev, dev); 343 344 ret = pci_enable_device(pdev); 345 if (ret) { 346 DRM_ERROR("failed to enable pci device: %d\n", ret); 347 goto err_free; 348 } 349 350 ret = hibmc_load(dev); 351 if (ret) { 352 DRM_ERROR("failed to load hibmc: %d\n", ret); 353 goto err_disable; 354 } 355 356 ret = drm_dev_register(dev, 0); 357 if (ret) { 358 DRM_ERROR("failed to register drv for userspace access: %d\n", 359 ret); 360 goto err_unload; 361 } 362 return 0; 363 364 err_unload: 365 hibmc_unload(dev); 366 err_disable: 367 pci_disable_device(pdev); 368 err_free: 369 drm_dev_put(dev); 370 371 return ret; 372 } 373 374 static void hibmc_pci_remove(struct pci_dev *pdev) 375 { 376 struct drm_device *dev = pci_get_drvdata(pdev); 377 378 drm_dev_unregister(dev); 379 hibmc_unload(dev); 380 drm_dev_put(dev); 381 } 382 383 static struct pci_device_id hibmc_pci_table[] = { 384 { PCI_VDEVICE(HUAWEI, 0x1711) }, 385 {0,} 386 }; 387 388 static struct pci_driver hibmc_pci_driver = { 389 .name = "hibmc-drm", 390 .id_table = hibmc_pci_table, 391 .probe = hibmc_pci_probe, 392 .remove = hibmc_pci_remove, 393 .driver.pm = &hibmc_pm_ops, 394 }; 395 396 module_pci_driver(hibmc_pci_driver); 397 398 MODULE_DEVICE_TABLE(pci, hibmc_pci_table); 399 MODULE_AUTHOR("RongrongZou <zourongrong@huawei.com>"); 400 MODULE_DESCRIPTION("DRM Driver for Hisilicon Hibmc"); 401 MODULE_LICENSE("GPL v2"); 402