1 /* Hisilicon Hibmc SoC drm driver 2 * 3 * Based on the bochs drm driver. 4 * 5 * Copyright (c) 2016 Huawei Limited. 6 * 7 * Author: 8 * Rongrong Zou <zourongrong@huawei.com> 9 * Rongrong Zou <zourongrong@gmail.com> 10 * Jianhua Li <lijianhua@huawei.com> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 */ 18 19 #include <drm/drm_atomic.h> 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_plane_helper.h> 22 #include <drm/drm_probe_helper.h> 23 24 #include "hibmc_drm_drv.h" 25 #include "hibmc_drm_regs.h" 26 27 struct hibmc_display_panel_pll { 28 unsigned long M; 29 unsigned long N; 30 unsigned long OD; 31 unsigned long POD; 32 }; 33 34 struct hibmc_dislay_pll_config { 35 unsigned long hdisplay; 36 unsigned long vdisplay; 37 u32 pll1_config_value; 38 u32 pll2_config_value; 39 }; 40 41 static const struct hibmc_dislay_pll_config hibmc_pll_table[] = { 42 {800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ}, 43 {1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ}, 44 {1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ}, 45 {1280, 768, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ}, 46 {1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ}, 47 {1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, 48 {1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, 49 {1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ}, 50 {1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ}, 51 {1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ}, 52 }; 53 54 #define PADDING(align, data) (((data) + (align) - 1) & (~((align) - 1))) 55 56 static int hibmc_plane_atomic_check(struct drm_plane *plane, 57 struct drm_plane_state *state) 58 { 59 struct drm_framebuffer *fb = state->fb; 60 struct drm_crtc *crtc = state->crtc; 61 struct drm_crtc_state *crtc_state; 62 u32 src_w = state->src_w >> 16; 63 u32 src_h = state->src_h >> 16; 64 65 if (!crtc || !fb) 66 return 0; 67 68 crtc_state = drm_atomic_get_crtc_state(state->state, crtc); 69 if (IS_ERR(crtc_state)) 70 return PTR_ERR(crtc_state); 71 72 if (src_w != state->crtc_w || src_h != state->crtc_h) { 73 DRM_DEBUG_ATOMIC("scale not support\n"); 74 return -EINVAL; 75 } 76 77 if (state->crtc_x < 0 || state->crtc_y < 0) { 78 DRM_DEBUG_ATOMIC("crtc_x/y of drm_plane state is invalid\n"); 79 return -EINVAL; 80 } 81 82 if (state->crtc_x + state->crtc_w > 83 crtc_state->adjusted_mode.hdisplay || 84 state->crtc_y + state->crtc_h > 85 crtc_state->adjusted_mode.vdisplay) { 86 DRM_DEBUG_ATOMIC("visible portion of plane is invalid\n"); 87 return -EINVAL; 88 } 89 90 return 0; 91 } 92 93 static void hibmc_plane_atomic_update(struct drm_plane *plane, 94 struct drm_plane_state *old_state) 95 { 96 struct drm_plane_state *state = plane->state; 97 u32 reg; 98 int ret; 99 s64 gpu_addr = 0; 100 unsigned int line_l; 101 struct hibmc_drm_private *priv = plane->dev->dev_private; 102 struct hibmc_framebuffer *hibmc_fb; 103 struct drm_gem_vram_object *gbo; 104 105 if (!state->fb) 106 return; 107 108 hibmc_fb = to_hibmc_framebuffer(state->fb); 109 gbo = drm_gem_vram_of_gem(hibmc_fb->obj); 110 111 ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM); 112 if (ret) { 113 DRM_ERROR("failed to pin bo: %d", ret); 114 return; 115 } 116 gpu_addr = drm_gem_vram_offset(gbo); 117 if (gpu_addr < 0) { 118 drm_gem_vram_unpin(gbo); 119 return; 120 } 121 122 writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS); 123 124 reg = state->fb->width * (state->fb->format->cpp[0]); 125 /* now line_pad is 16 */ 126 reg = PADDING(16, reg); 127 128 line_l = state->fb->width * state->fb->format->cpp[0]; 129 line_l = PADDING(16, line_l); 130 writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) | 131 HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_OFFS, line_l), 132 priv->mmio + HIBMC_CRT_FB_WIDTH); 133 134 /* SET PIXEL FORMAT */ 135 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); 136 reg &= ~HIBMC_CRT_DISP_CTL_FORMAT_MASK; 137 reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT, 138 state->fb->format->cpp[0] * 8 / 16); 139 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); 140 } 141 142 static const u32 channel_formats1[] = { 143 DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888, 144 DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, 145 DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888, 146 DRM_FORMAT_ABGR8888 147 }; 148 149 static struct drm_plane_funcs hibmc_plane_funcs = { 150 .update_plane = drm_atomic_helper_update_plane, 151 .disable_plane = drm_atomic_helper_disable_plane, 152 .destroy = drm_plane_cleanup, 153 .reset = drm_atomic_helper_plane_reset, 154 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 155 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 156 }; 157 158 static const struct drm_plane_helper_funcs hibmc_plane_helper_funcs = { 159 .atomic_check = hibmc_plane_atomic_check, 160 .atomic_update = hibmc_plane_atomic_update, 161 }; 162 163 static struct drm_plane *hibmc_plane_init(struct hibmc_drm_private *priv) 164 { 165 struct drm_device *dev = priv->dev; 166 struct drm_plane *plane; 167 int ret = 0; 168 169 plane = devm_kzalloc(dev->dev, sizeof(*plane), GFP_KERNEL); 170 if (!plane) { 171 DRM_ERROR("failed to alloc memory when init plane\n"); 172 return ERR_PTR(-ENOMEM); 173 } 174 /* 175 * plane init 176 * TODO: Now only support primary plane, overlay planes 177 * need to do. 178 */ 179 ret = drm_universal_plane_init(dev, plane, 1, &hibmc_plane_funcs, 180 channel_formats1, 181 ARRAY_SIZE(channel_formats1), 182 NULL, 183 DRM_PLANE_TYPE_PRIMARY, 184 NULL); 185 if (ret) { 186 DRM_ERROR("failed to init plane: %d\n", ret); 187 return ERR_PTR(ret); 188 } 189 190 drm_plane_helper_add(plane, &hibmc_plane_helper_funcs); 191 return plane; 192 } 193 194 static void hibmc_crtc_atomic_enable(struct drm_crtc *crtc, 195 struct drm_crtc_state *old_state) 196 { 197 unsigned int reg; 198 struct hibmc_drm_private *priv = crtc->dev->dev_private; 199 200 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0); 201 202 /* Enable display power gate & LOCALMEM power gate*/ 203 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 204 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 205 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 206 reg |= HIBMC_CURR_GATE_LOCALMEM(1); 207 reg |= HIBMC_CURR_GATE_DISPLAY(1); 208 hibmc_set_current_gate(priv, reg); 209 drm_crtc_vblank_on(crtc); 210 } 211 212 static void hibmc_crtc_atomic_disable(struct drm_crtc *crtc, 213 struct drm_crtc_state *old_state) 214 { 215 unsigned int reg; 216 struct hibmc_drm_private *priv = crtc->dev->dev_private; 217 218 drm_crtc_vblank_off(crtc); 219 220 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_SLEEP); 221 222 /* Enable display power gate & LOCALMEM power gate*/ 223 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 224 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 225 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 226 reg |= HIBMC_CURR_GATE_LOCALMEM(0); 227 reg |= HIBMC_CURR_GATE_DISPLAY(0); 228 hibmc_set_current_gate(priv, reg); 229 } 230 231 static unsigned int format_pll_reg(void) 232 { 233 unsigned int pllreg = 0; 234 struct hibmc_display_panel_pll pll = {0}; 235 236 /* 237 * Note that all PLL's have the same format. Here, 238 * we just use Panel PLL parameter to work out the bit 239 * fields in the register.On returning a 32 bit number, the value can 240 * be applied to any PLL in the calling function. 241 */ 242 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_BYPASS, 0); 243 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POWER, 1); 244 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_INPUT, 0); 245 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD); 246 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD); 247 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N); 248 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M); 249 250 return pllreg; 251 } 252 253 static void set_vclock_hisilicon(struct drm_device *dev, unsigned long pll) 254 { 255 u32 val; 256 struct hibmc_drm_private *priv = dev->dev_private; 257 258 val = readl(priv->mmio + CRT_PLL1_HS); 259 val &= ~(CRT_PLL1_HS_OUTER_BYPASS(1)); 260 writel(val, priv->mmio + CRT_PLL1_HS); 261 262 val = CRT_PLL1_HS_INTER_BYPASS(1) | CRT_PLL1_HS_POWERON(1); 263 writel(val, priv->mmio + CRT_PLL1_HS); 264 265 writel(pll, priv->mmio + CRT_PLL1_HS); 266 267 usleep_range(1000, 2000); 268 269 val = pll & ~(CRT_PLL1_HS_POWERON(1)); 270 writel(val, priv->mmio + CRT_PLL1_HS); 271 272 usleep_range(1000, 2000); 273 274 val &= ~(CRT_PLL1_HS_INTER_BYPASS(1)); 275 writel(val, priv->mmio + CRT_PLL1_HS); 276 277 usleep_range(1000, 2000); 278 279 val |= CRT_PLL1_HS_OUTER_BYPASS(1); 280 writel(val, priv->mmio + CRT_PLL1_HS); 281 } 282 283 static void get_pll_config(unsigned long x, unsigned long y, 284 u32 *pll1, u32 *pll2) 285 { 286 int i; 287 int count = ARRAY_SIZE(hibmc_pll_table); 288 289 for (i = 0; i < count; i++) { 290 if (hibmc_pll_table[i].hdisplay == x && 291 hibmc_pll_table[i].vdisplay == y) { 292 *pll1 = hibmc_pll_table[i].pll1_config_value; 293 *pll2 = hibmc_pll_table[i].pll2_config_value; 294 return; 295 } 296 } 297 298 /* if found none, we use default value */ 299 *pll1 = CRT_PLL1_HS_25MHZ; 300 *pll2 = CRT_PLL2_HS_25MHZ; 301 } 302 303 /* 304 * This function takes care the extra registers and bit fields required to 305 * setup a mode in board. 306 * Explanation about Display Control register: 307 * FPGA only supports 7 predefined pixel clocks, and clock select is 308 * in bit 4:0 of new register 0x802a8. 309 */ 310 static unsigned int display_ctrl_adjust(struct drm_device *dev, 311 struct drm_display_mode *mode, 312 unsigned int ctrl) 313 { 314 unsigned long x, y; 315 u32 pll1; /* bit[31:0] of PLL */ 316 u32 pll2; /* bit[63:32] of PLL */ 317 struct hibmc_drm_private *priv = dev->dev_private; 318 319 x = mode->hdisplay; 320 y = mode->vdisplay; 321 322 get_pll_config(x, y, &pll1, &pll2); 323 writel(pll2, priv->mmio + CRT_PLL2_HS); 324 set_vclock_hisilicon(dev, pll1); 325 326 /* 327 * Hisilicon has to set up the top-left and bottom-right 328 * registers as well. 329 * Note that normal chip only use those two register for 330 * auto-centering mode. 331 */ 332 writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_TOP, 0) | 333 HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_LEFT, 0), 334 priv->mmio + HIBMC_CRT_AUTO_CENTERING_TL); 335 336 writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM, y - 1) | 337 HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_RIGHT, x - 1), 338 priv->mmio + HIBMC_CRT_AUTO_CENTERING_BR); 339 340 /* 341 * Assume common fields in ctrl have been properly set before 342 * calling this function. 343 * This function only sets the extra fields in ctrl. 344 */ 345 346 /* Set bit 25 of display controller: Select CRT or VGA clock */ 347 ctrl &= ~HIBMC_CRT_DISP_CTL_CRTSELECT_MASK; 348 ctrl &= ~HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK; 349 350 ctrl |= HIBMC_CRT_DISP_CTL_CRTSELECT(HIBMC_CRTSELECT_CRT); 351 352 /* clock_phase_polarity is 0 */ 353 ctrl |= HIBMC_CRT_DISP_CTL_CLOCK_PHASE(0); 354 355 writel(ctrl, priv->mmio + HIBMC_CRT_DISP_CTL); 356 357 return ctrl; 358 } 359 360 static void hibmc_crtc_mode_set_nofb(struct drm_crtc *crtc) 361 { 362 unsigned int val; 363 struct drm_display_mode *mode = &crtc->state->mode; 364 struct drm_device *dev = crtc->dev; 365 struct hibmc_drm_private *priv = dev->dev_private; 366 int width = mode->hsync_end - mode->hsync_start; 367 int height = mode->vsync_end - mode->vsync_start; 368 369 writel(format_pll_reg(), priv->mmio + HIBMC_CRT_PLL_CTRL); 370 writel(HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_TOTAL, mode->htotal - 1) | 371 HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_DISP_END, mode->hdisplay - 1), 372 priv->mmio + HIBMC_CRT_HORZ_TOTAL); 373 374 writel(HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_WIDTH, width) | 375 HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_START, mode->hsync_start - 1), 376 priv->mmio + HIBMC_CRT_HORZ_SYNC); 377 378 writel(HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_TOTAL, mode->vtotal - 1) | 379 HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_DISP_END, mode->vdisplay - 1), 380 priv->mmio + HIBMC_CRT_VERT_TOTAL); 381 382 writel(HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_HEIGHT, height) | 383 HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_START, mode->vsync_start - 1), 384 priv->mmio + HIBMC_CRT_VERT_SYNC); 385 386 val = HIBMC_FIELD(HIBMC_CRT_DISP_CTL_VSYNC_PHASE, 0); 387 val |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_HSYNC_PHASE, 0); 388 val |= HIBMC_CRT_DISP_CTL_TIMING(1); 389 val |= HIBMC_CRT_DISP_CTL_PLANE(1); 390 391 display_ctrl_adjust(dev, mode, val); 392 } 393 394 static void hibmc_crtc_atomic_begin(struct drm_crtc *crtc, 395 struct drm_crtc_state *old_state) 396 { 397 unsigned int reg; 398 struct drm_device *dev = crtc->dev; 399 struct hibmc_drm_private *priv = dev->dev_private; 400 401 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0); 402 403 /* Enable display power gate & LOCALMEM power gate*/ 404 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 405 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 406 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 407 reg |= HIBMC_CURR_GATE_DISPLAY(1); 408 reg |= HIBMC_CURR_GATE_LOCALMEM(1); 409 hibmc_set_current_gate(priv, reg); 410 411 /* We can add more initialization as needed. */ 412 } 413 414 static void hibmc_crtc_atomic_flush(struct drm_crtc *crtc, 415 struct drm_crtc_state *old_state) 416 417 { 418 unsigned long flags; 419 420 spin_lock_irqsave(&crtc->dev->event_lock, flags); 421 if (crtc->state->event) 422 drm_crtc_send_vblank_event(crtc, crtc->state->event); 423 crtc->state->event = NULL; 424 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 425 } 426 427 static int hibmc_crtc_enable_vblank(struct drm_crtc *crtc) 428 { 429 struct hibmc_drm_private *priv = crtc->dev->dev_private; 430 431 writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(1), 432 priv->mmio + HIBMC_RAW_INTERRUPT_EN); 433 434 return 0; 435 } 436 437 static void hibmc_crtc_disable_vblank(struct drm_crtc *crtc) 438 { 439 struct hibmc_drm_private *priv = crtc->dev->dev_private; 440 441 writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(0), 442 priv->mmio + HIBMC_RAW_INTERRUPT_EN); 443 } 444 445 static const struct drm_crtc_funcs hibmc_crtc_funcs = { 446 .page_flip = drm_atomic_helper_page_flip, 447 .set_config = drm_atomic_helper_set_config, 448 .destroy = drm_crtc_cleanup, 449 .reset = drm_atomic_helper_crtc_reset, 450 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 451 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 452 .enable_vblank = hibmc_crtc_enable_vblank, 453 .disable_vblank = hibmc_crtc_disable_vblank, 454 }; 455 456 static const struct drm_crtc_helper_funcs hibmc_crtc_helper_funcs = { 457 .mode_set_nofb = hibmc_crtc_mode_set_nofb, 458 .atomic_begin = hibmc_crtc_atomic_begin, 459 .atomic_flush = hibmc_crtc_atomic_flush, 460 .atomic_enable = hibmc_crtc_atomic_enable, 461 .atomic_disable = hibmc_crtc_atomic_disable, 462 }; 463 464 int hibmc_de_init(struct hibmc_drm_private *priv) 465 { 466 struct drm_device *dev = priv->dev; 467 struct drm_crtc *crtc; 468 struct drm_plane *plane; 469 int ret; 470 471 plane = hibmc_plane_init(priv); 472 if (IS_ERR(plane)) { 473 DRM_ERROR("failed to create plane: %ld\n", PTR_ERR(plane)); 474 return PTR_ERR(plane); 475 } 476 477 crtc = devm_kzalloc(dev->dev, sizeof(*crtc), GFP_KERNEL); 478 if (!crtc) { 479 DRM_ERROR("failed to alloc memory when init crtc\n"); 480 return -ENOMEM; 481 } 482 483 ret = drm_crtc_init_with_planes(dev, crtc, plane, 484 NULL, &hibmc_crtc_funcs, NULL); 485 if (ret) { 486 DRM_ERROR("failed to init crtc: %d\n", ret); 487 return ret; 488 } 489 490 ret = drm_mode_crtc_set_gamma_size(crtc, 256); 491 if (ret) { 492 DRM_ERROR("failed to set gamma size: %d\n", ret); 493 return ret; 494 } 495 drm_crtc_helper_add(crtc, &hibmc_crtc_helper_funcs); 496 497 return 0; 498 } 499