1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Hisilicon Hibmc SoC drm driver
3  *
4  * Based on the bochs drm driver.
5  *
6  * Copyright (c) 2016 Huawei Limited.
7  *
8  * Author:
9  *	Rongrong Zou <zourongrong@huawei.com>
10  *	Rongrong Zou <zourongrong@gmail.com>
11  *	Jianhua Li <lijianhua@huawei.com>
12  */
13 
14 #include <linux/delay.h>
15 
16 #include <drm/drm_atomic.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_fourcc.h>
19 #include <drm/drm_gem_vram_helper.h>
20 #include <drm/drm_plane_helper.h>
21 #include <drm/drm_print.h>
22 #include <drm/drm_probe_helper.h>
23 #include <drm/drm_vblank.h>
24 
25 #include "hibmc_drm_drv.h"
26 #include "hibmc_drm_regs.h"
27 
28 struct hibmc_display_panel_pll {
29 	unsigned long M;
30 	unsigned long N;
31 	unsigned long OD;
32 	unsigned long POD;
33 };
34 
35 struct hibmc_dislay_pll_config {
36 	unsigned long hdisplay;
37 	unsigned long vdisplay;
38 	u32 pll1_config_value;
39 	u32 pll2_config_value;
40 };
41 
42 static const struct hibmc_dislay_pll_config hibmc_pll_table[] = {
43 	{640, 480, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ},
44 	{800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ},
45 	{1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ},
46 	{1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ},
47 	{1280, 768, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ},
48 	{1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ},
49 	{1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
50 	{1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
51 	{1440, 900, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ},
52 	{1600, 900, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
53 	{1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ},
54 	{1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ},
55 	{1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ},
56 };
57 
58 #define PADDING(align, data) (((data) + (align) - 1) & (~((align) - 1)))
59 
60 static int hibmc_plane_atomic_check(struct drm_plane *plane,
61 				    struct drm_plane_state *state)
62 {
63 	struct drm_framebuffer *fb = state->fb;
64 	struct drm_crtc *crtc = state->crtc;
65 	struct drm_crtc_state *crtc_state;
66 	u32 src_w = state->src_w >> 16;
67 	u32 src_h = state->src_h >> 16;
68 
69 	if (!crtc || !fb)
70 		return 0;
71 
72 	crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
73 	if (IS_ERR(crtc_state))
74 		return PTR_ERR(crtc_state);
75 
76 	if (src_w != state->crtc_w || src_h != state->crtc_h) {
77 		DRM_DEBUG_ATOMIC("scale not support\n");
78 		return -EINVAL;
79 	}
80 
81 	if (state->crtc_x < 0 || state->crtc_y < 0) {
82 		DRM_DEBUG_ATOMIC("crtc_x/y of drm_plane state is invalid\n");
83 		return -EINVAL;
84 	}
85 
86 	if (!crtc_state->enable)
87 		return 0;
88 
89 	if (state->crtc_x + state->crtc_w >
90 	    crtc_state->adjusted_mode.hdisplay ||
91 	    state->crtc_y + state->crtc_h >
92 	    crtc_state->adjusted_mode.vdisplay) {
93 		DRM_DEBUG_ATOMIC("visible portion of plane is invalid\n");
94 		return -EINVAL;
95 	}
96 
97 	return 0;
98 }
99 
100 static void hibmc_plane_atomic_update(struct drm_plane *plane,
101 				      struct drm_plane_state *old_state)
102 {
103 	struct drm_plane_state	*state	= plane->state;
104 	u32 reg;
105 	s64 gpu_addr = 0;
106 	unsigned int line_l;
107 	struct hibmc_drm_private *priv = plane->dev->dev_private;
108 	struct drm_gem_vram_object *gbo;
109 
110 	if (!state->fb)
111 		return;
112 
113 	gbo = drm_gem_vram_of_gem(state->fb->obj[0]);
114 
115 	gpu_addr = drm_gem_vram_offset(gbo);
116 	if (WARN_ON_ONCE(gpu_addr < 0))
117 		return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */
118 
119 	writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS);
120 
121 	reg = state->fb->width * (state->fb->format->cpp[0]);
122 	/* now line_pad is 16 */
123 	reg = PADDING(16, reg);
124 
125 	line_l = state->fb->width * state->fb->format->cpp[0];
126 	line_l = PADDING(16, line_l);
127 	writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) |
128 	       HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_OFFS, line_l),
129 	       priv->mmio + HIBMC_CRT_FB_WIDTH);
130 
131 	/* SET PIXEL FORMAT */
132 	reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);
133 	reg &= ~HIBMC_CRT_DISP_CTL_FORMAT_MASK;
134 	reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT,
135 			   state->fb->format->cpp[0] * 8 / 16);
136 	writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);
137 }
138 
139 static const u32 channel_formats1[] = {
140 	DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888,
141 	DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
142 	DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888,
143 	DRM_FORMAT_ABGR8888
144 };
145 
146 static struct drm_plane_funcs hibmc_plane_funcs = {
147 	.update_plane	= drm_atomic_helper_update_plane,
148 	.disable_plane	= drm_atomic_helper_disable_plane,
149 	.destroy = drm_plane_cleanup,
150 	.reset = drm_atomic_helper_plane_reset,
151 	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
152 	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
153 };
154 
155 static const struct drm_plane_helper_funcs hibmc_plane_helper_funcs = {
156 	.prepare_fb	= drm_gem_vram_plane_helper_prepare_fb,
157 	.cleanup_fb	= drm_gem_vram_plane_helper_cleanup_fb,
158 	.atomic_check = hibmc_plane_atomic_check,
159 	.atomic_update = hibmc_plane_atomic_update,
160 };
161 
162 static struct drm_plane *hibmc_plane_init(struct hibmc_drm_private *priv)
163 {
164 	struct drm_device *dev = priv->dev;
165 	struct drm_plane *plane;
166 	int ret = 0;
167 
168 	plane = devm_kzalloc(dev->dev, sizeof(*plane), GFP_KERNEL);
169 	if (!plane) {
170 		DRM_ERROR("failed to alloc memory when init plane\n");
171 		return ERR_PTR(-ENOMEM);
172 	}
173 	/*
174 	 * plane init
175 	 * TODO: Now only support primary plane, overlay planes
176 	 * need to do.
177 	 */
178 	ret = drm_universal_plane_init(dev, plane, 1, &hibmc_plane_funcs,
179 				       channel_formats1,
180 				       ARRAY_SIZE(channel_formats1),
181 				       NULL,
182 				       DRM_PLANE_TYPE_PRIMARY,
183 				       NULL);
184 	if (ret) {
185 		DRM_ERROR("failed to init plane: %d\n", ret);
186 		return ERR_PTR(ret);
187 	}
188 
189 	drm_plane_helper_add(plane, &hibmc_plane_helper_funcs);
190 	return plane;
191 }
192 
193 static void hibmc_crtc_dpms(struct drm_crtc *crtc, int dpms)
194 {
195 	struct hibmc_drm_private *priv = crtc->dev->dev_private;
196 	unsigned int reg;
197 
198 	reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);
199 	reg &= ~HIBMC_CRT_DISP_CTL_DPMS_MASK;
200 	reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_DPMS, dpms);
201 	reg &= ~HIBMC_CRT_DISP_CTL_TIMING_MASK;
202 	if (dpms == HIBMC_CRT_DPMS_ON)
203 		reg |= HIBMC_CRT_DISP_CTL_TIMING(1);
204 	writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);
205 }
206 
207 static void hibmc_crtc_atomic_enable(struct drm_crtc *crtc,
208 				     struct drm_crtc_state *old_state)
209 {
210 	unsigned int reg;
211 	struct hibmc_drm_private *priv = crtc->dev->dev_private;
212 
213 	hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
214 
215 	/* Enable display power gate & LOCALMEM power gate*/
216 	reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
217 	reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
218 	reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
219 	reg |= HIBMC_CURR_GATE_LOCALMEM(1);
220 	reg |= HIBMC_CURR_GATE_DISPLAY(1);
221 	hibmc_set_current_gate(priv, reg);
222 	drm_crtc_vblank_on(crtc);
223 	hibmc_crtc_dpms(crtc, HIBMC_CRT_DPMS_ON);
224 }
225 
226 static void hibmc_crtc_atomic_disable(struct drm_crtc *crtc,
227 				      struct drm_crtc_state *old_state)
228 {
229 	unsigned int reg;
230 	struct hibmc_drm_private *priv = crtc->dev->dev_private;
231 
232 	hibmc_crtc_dpms(crtc, HIBMC_CRT_DPMS_OFF);
233 	drm_crtc_vblank_off(crtc);
234 
235 	hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_SLEEP);
236 
237 	/* Enable display power gate & LOCALMEM power gate*/
238 	reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
239 	reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
240 	reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
241 	reg |= HIBMC_CURR_GATE_LOCALMEM(0);
242 	reg |= HIBMC_CURR_GATE_DISPLAY(0);
243 	hibmc_set_current_gate(priv, reg);
244 }
245 
246 static enum drm_mode_status
247 hibmc_crtc_mode_valid(struct drm_crtc *crtc,
248 		      const struct drm_display_mode *mode)
249 {
250 	int i = 0;
251 	int vrefresh = drm_mode_vrefresh(mode);
252 
253 	if (vrefresh < 59 || vrefresh > 61)
254 		return MODE_NOCLOCK;
255 
256 	for (i = 0; i < ARRAY_SIZE(hibmc_pll_table); i++) {
257 		if (hibmc_pll_table[i].hdisplay == mode->hdisplay &&
258 		    hibmc_pll_table[i].vdisplay == mode->vdisplay)
259 			return MODE_OK;
260 	}
261 
262 	return MODE_BAD;
263 }
264 
265 static unsigned int format_pll_reg(void)
266 {
267 	unsigned int pllreg = 0;
268 	struct hibmc_display_panel_pll pll = {0};
269 
270 	/*
271 	 * Note that all PLL's have the same format. Here,
272 	 * we just use Panel PLL parameter to work out the bit
273 	 * fields in the register.On returning a 32 bit number, the value can
274 	 * be applied to any PLL in the calling function.
275 	 */
276 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_BYPASS, 0);
277 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POWER, 1);
278 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_INPUT, 0);
279 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD);
280 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD);
281 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N);
282 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M);
283 
284 	return pllreg;
285 }
286 
287 static void set_vclock_hisilicon(struct drm_device *dev, unsigned long pll)
288 {
289 	u32 val;
290 	struct hibmc_drm_private *priv = dev->dev_private;
291 
292 	val = readl(priv->mmio + CRT_PLL1_HS);
293 	val &= ~(CRT_PLL1_HS_OUTER_BYPASS(1));
294 	writel(val, priv->mmio + CRT_PLL1_HS);
295 
296 	val = CRT_PLL1_HS_INTER_BYPASS(1) | CRT_PLL1_HS_POWERON(1);
297 	writel(val, priv->mmio + CRT_PLL1_HS);
298 
299 	writel(pll, priv->mmio + CRT_PLL1_HS);
300 
301 	usleep_range(1000, 2000);
302 
303 	val = pll & ~(CRT_PLL1_HS_POWERON(1));
304 	writel(val, priv->mmio + CRT_PLL1_HS);
305 
306 	usleep_range(1000, 2000);
307 
308 	val &= ~(CRT_PLL1_HS_INTER_BYPASS(1));
309 	writel(val, priv->mmio + CRT_PLL1_HS);
310 
311 	usleep_range(1000, 2000);
312 
313 	val |= CRT_PLL1_HS_OUTER_BYPASS(1);
314 	writel(val, priv->mmio + CRT_PLL1_HS);
315 }
316 
317 static void get_pll_config(unsigned long x, unsigned long y,
318 			   u32 *pll1, u32 *pll2)
319 {
320 	int i;
321 	int count = ARRAY_SIZE(hibmc_pll_table);
322 
323 	for (i = 0; i < count; i++) {
324 		if (hibmc_pll_table[i].hdisplay == x &&
325 		    hibmc_pll_table[i].vdisplay == y) {
326 			*pll1 = hibmc_pll_table[i].pll1_config_value;
327 			*pll2 = hibmc_pll_table[i].pll2_config_value;
328 			return;
329 		}
330 	}
331 
332 	/* if found none, we use default value */
333 	*pll1 = CRT_PLL1_HS_25MHZ;
334 	*pll2 = CRT_PLL2_HS_25MHZ;
335 }
336 
337 /*
338  * This function takes care the extra registers and bit fields required to
339  * setup a mode in board.
340  * Explanation about Display Control register:
341  * FPGA only supports 7 predefined pixel clocks, and clock select is
342  * in bit 4:0 of new register 0x802a8.
343  */
344 static unsigned int display_ctrl_adjust(struct drm_device *dev,
345 					struct drm_display_mode *mode,
346 					unsigned int ctrl)
347 {
348 	unsigned long x, y;
349 	u32 pll1; /* bit[31:0] of PLL */
350 	u32 pll2; /* bit[63:32] of PLL */
351 	struct hibmc_drm_private *priv = dev->dev_private;
352 
353 	x = mode->hdisplay;
354 	y = mode->vdisplay;
355 
356 	get_pll_config(x, y, &pll1, &pll2);
357 	writel(pll2, priv->mmio + CRT_PLL2_HS);
358 	set_vclock_hisilicon(dev, pll1);
359 
360 	/*
361 	 * Hisilicon has to set up the top-left and bottom-right
362 	 * registers as well.
363 	 * Note that normal chip only use those two register for
364 	 * auto-centering mode.
365 	 */
366 	writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_TOP, 0) |
367 	       HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_LEFT, 0),
368 	       priv->mmio + HIBMC_CRT_AUTO_CENTERING_TL);
369 
370 	writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM, y - 1) |
371 	       HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_RIGHT, x - 1),
372 	       priv->mmio + HIBMC_CRT_AUTO_CENTERING_BR);
373 
374 	/*
375 	 * Assume common fields in ctrl have been properly set before
376 	 * calling this function.
377 	 * This function only sets the extra fields in ctrl.
378 	 */
379 
380 	/* Set bit 25 of display controller: Select CRT or VGA clock */
381 	ctrl &= ~HIBMC_CRT_DISP_CTL_CRTSELECT_MASK;
382 	ctrl &= ~HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK;
383 
384 	ctrl |= HIBMC_CRT_DISP_CTL_CRTSELECT(HIBMC_CRTSELECT_CRT);
385 
386 	/* clock_phase_polarity is 0 */
387 	ctrl |= HIBMC_CRT_DISP_CTL_CLOCK_PHASE(0);
388 
389 	writel(ctrl, priv->mmio + HIBMC_CRT_DISP_CTL);
390 
391 	return ctrl;
392 }
393 
394 static void hibmc_crtc_mode_set_nofb(struct drm_crtc *crtc)
395 {
396 	unsigned int val;
397 	struct drm_display_mode *mode = &crtc->state->mode;
398 	struct drm_device *dev = crtc->dev;
399 	struct hibmc_drm_private *priv = dev->dev_private;
400 	int width = mode->hsync_end - mode->hsync_start;
401 	int height = mode->vsync_end - mode->vsync_start;
402 
403 	writel(format_pll_reg(), priv->mmio + HIBMC_CRT_PLL_CTRL);
404 	writel(HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_TOTAL, mode->htotal - 1) |
405 	       HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_DISP_END, mode->hdisplay - 1),
406 	       priv->mmio + HIBMC_CRT_HORZ_TOTAL);
407 
408 	writel(HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_WIDTH, width) |
409 	       HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_START, mode->hsync_start - 1),
410 	       priv->mmio + HIBMC_CRT_HORZ_SYNC);
411 
412 	writel(HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_TOTAL, mode->vtotal - 1) |
413 	       HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_DISP_END, mode->vdisplay - 1),
414 	       priv->mmio + HIBMC_CRT_VERT_TOTAL);
415 
416 	writel(HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_HEIGHT, height) |
417 	       HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_START, mode->vsync_start - 1),
418 	       priv->mmio + HIBMC_CRT_VERT_SYNC);
419 
420 	val = HIBMC_FIELD(HIBMC_CRT_DISP_CTL_VSYNC_PHASE, 0);
421 	val |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_HSYNC_PHASE, 0);
422 	val |= HIBMC_CRT_DISP_CTL_TIMING(1);
423 	val |= HIBMC_CRT_DISP_CTL_PLANE(1);
424 
425 	display_ctrl_adjust(dev, mode, val);
426 }
427 
428 static void hibmc_crtc_atomic_begin(struct drm_crtc *crtc,
429 				    struct drm_crtc_state *old_state)
430 {
431 	unsigned int reg;
432 	struct drm_device *dev = crtc->dev;
433 	struct hibmc_drm_private *priv = dev->dev_private;
434 
435 	hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
436 
437 	/* Enable display power gate & LOCALMEM power gate*/
438 	reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
439 	reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
440 	reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
441 	reg |= HIBMC_CURR_GATE_DISPLAY(1);
442 	reg |= HIBMC_CURR_GATE_LOCALMEM(1);
443 	hibmc_set_current_gate(priv, reg);
444 
445 	/* We can add more initialization as needed. */
446 }
447 
448 static void hibmc_crtc_atomic_flush(struct drm_crtc *crtc,
449 				    struct drm_crtc_state *old_state)
450 
451 {
452 	unsigned long flags;
453 
454 	spin_lock_irqsave(&crtc->dev->event_lock, flags);
455 	if (crtc->state->event)
456 		drm_crtc_send_vblank_event(crtc, crtc->state->event);
457 	crtc->state->event = NULL;
458 	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
459 }
460 
461 static int hibmc_crtc_enable_vblank(struct drm_crtc *crtc)
462 {
463 	struct hibmc_drm_private *priv = crtc->dev->dev_private;
464 
465 	writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(1),
466 	       priv->mmio + HIBMC_RAW_INTERRUPT_EN);
467 
468 	return 0;
469 }
470 
471 static void hibmc_crtc_disable_vblank(struct drm_crtc *crtc)
472 {
473 	struct hibmc_drm_private *priv = crtc->dev->dev_private;
474 
475 	writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(0),
476 	       priv->mmio + HIBMC_RAW_INTERRUPT_EN);
477 }
478 
479 static void hibmc_crtc_load_lut(struct drm_crtc *crtc)
480 {
481 	struct hibmc_drm_private *priv = crtc->dev->dev_private;
482 	void __iomem   *mmio = priv->mmio;
483 	u16 *r, *g, *b;
484 	unsigned int reg;
485 	int i;
486 
487 	r = crtc->gamma_store;
488 	g = r + crtc->gamma_size;
489 	b = g + crtc->gamma_size;
490 
491 	for (i = 0; i < crtc->gamma_size; i++) {
492 		unsigned int offset = i << 2;
493 		u8 red = *r++ >> 8;
494 		u8 green = *g++ >> 8;
495 		u8 blue = *b++ >> 8;
496 		u32 rgb = (red << 16) | (green << 8) | blue;
497 
498 		writel(rgb, mmio + HIBMC_CRT_PALETTE + offset);
499 	}
500 
501 	reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);
502 	reg |= HIBMC_FIELD(HIBMC_CTL_DISP_CTL_GAMMA, 1);
503 	writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);
504 }
505 
506 static int hibmc_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
507 				u16 *blue, uint32_t size,
508 				struct drm_modeset_acquire_ctx *ctx)
509 {
510 	hibmc_crtc_load_lut(crtc);
511 
512 	return 0;
513 }
514 
515 static const struct drm_crtc_funcs hibmc_crtc_funcs = {
516 	.page_flip = drm_atomic_helper_page_flip,
517 	.set_config = drm_atomic_helper_set_config,
518 	.destroy = drm_crtc_cleanup,
519 	.reset = drm_atomic_helper_crtc_reset,
520 	.atomic_duplicate_state =  drm_atomic_helper_crtc_duplicate_state,
521 	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
522 	.enable_vblank = hibmc_crtc_enable_vblank,
523 	.disable_vblank = hibmc_crtc_disable_vblank,
524 	.gamma_set = hibmc_crtc_gamma_set,
525 };
526 
527 static const struct drm_crtc_helper_funcs hibmc_crtc_helper_funcs = {
528 	.mode_set_nofb	= hibmc_crtc_mode_set_nofb,
529 	.atomic_begin	= hibmc_crtc_atomic_begin,
530 	.atomic_flush	= hibmc_crtc_atomic_flush,
531 	.atomic_enable	= hibmc_crtc_atomic_enable,
532 	.atomic_disable	= hibmc_crtc_atomic_disable,
533 	.mode_valid = hibmc_crtc_mode_valid,
534 };
535 
536 int hibmc_de_init(struct hibmc_drm_private *priv)
537 {
538 	struct drm_device *dev = priv->dev;
539 	struct drm_crtc *crtc;
540 	struct drm_plane *plane;
541 	int ret;
542 
543 	plane = hibmc_plane_init(priv);
544 	if (IS_ERR(plane)) {
545 		DRM_ERROR("failed to create plane: %ld\n", PTR_ERR(plane));
546 		return PTR_ERR(plane);
547 	}
548 
549 	crtc = devm_kzalloc(dev->dev, sizeof(*crtc), GFP_KERNEL);
550 	if (!crtc) {
551 		DRM_ERROR("failed to alloc memory when init crtc\n");
552 		return -ENOMEM;
553 	}
554 
555 	ret = drm_crtc_init_with_planes(dev, crtc, plane,
556 					NULL, &hibmc_crtc_funcs, NULL);
557 	if (ret) {
558 		DRM_ERROR("failed to init crtc: %d\n", ret);
559 		return ret;
560 	}
561 
562 	ret = drm_mode_crtc_set_gamma_size(crtc, 256);
563 	if (ret) {
564 		DRM_ERROR("failed to set gamma size: %d\n", ret);
565 		return ret;
566 	}
567 	drm_crtc_helper_add(crtc, &hibmc_crtc_helper_funcs);
568 
569 	return 0;
570 }
571