1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Hisilicon Hibmc SoC drm driver 3 * 4 * Based on the bochs drm driver. 5 * 6 * Copyright (c) 2016 Huawei Limited. 7 * 8 * Author: 9 * Rongrong Zou <zourongrong@huawei.com> 10 * Rongrong Zou <zourongrong@gmail.com> 11 * Jianhua Li <lijianhua@huawei.com> 12 */ 13 14 #include <linux/delay.h> 15 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_fourcc.h> 19 #include <drm/drm_gem_vram_helper.h> 20 #include <drm/drm_vblank.h> 21 22 #include "hibmc_drm_drv.h" 23 #include "hibmc_drm_regs.h" 24 25 struct hibmc_display_panel_pll { 26 u64 M; 27 u64 N; 28 u64 OD; 29 u64 POD; 30 }; 31 32 struct hibmc_dislay_pll_config { 33 u64 hdisplay; 34 u64 vdisplay; 35 u32 pll1_config_value; 36 u32 pll2_config_value; 37 }; 38 39 static const struct hibmc_dislay_pll_config hibmc_pll_table[] = { 40 {640, 480, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ}, 41 {800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ}, 42 {1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ}, 43 {1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ}, 44 {1280, 768, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ}, 45 {1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ}, 46 {1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, 47 {1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, 48 {1440, 900, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ}, 49 {1600, 900, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, 50 {1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ}, 51 {1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ}, 52 {1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ}, 53 }; 54 55 static int hibmc_plane_atomic_check(struct drm_plane *plane, 56 struct drm_atomic_state *state) 57 { 58 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 59 plane); 60 struct drm_framebuffer *fb = new_plane_state->fb; 61 struct drm_crtc *crtc = new_plane_state->crtc; 62 struct drm_crtc_state *crtc_state; 63 u32 src_w = new_plane_state->src_w >> 16; 64 u32 src_h = new_plane_state->src_h >> 16; 65 66 if (!crtc || !fb) 67 return 0; 68 69 crtc_state = drm_atomic_get_crtc_state(state, crtc); 70 if (IS_ERR(crtc_state)) 71 return PTR_ERR(crtc_state); 72 73 if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) { 74 drm_dbg_atomic(plane->dev, "scale not support\n"); 75 return -EINVAL; 76 } 77 78 if (new_plane_state->crtc_x < 0 || new_plane_state->crtc_y < 0) { 79 drm_dbg_atomic(plane->dev, "crtc_x/y of drm_plane state is invalid\n"); 80 return -EINVAL; 81 } 82 83 if (!crtc_state->enable) 84 return 0; 85 86 if (new_plane_state->crtc_x + new_plane_state->crtc_w > 87 crtc_state->adjusted_mode.hdisplay || 88 new_plane_state->crtc_y + new_plane_state->crtc_h > 89 crtc_state->adjusted_mode.vdisplay) { 90 drm_dbg_atomic(plane->dev, "visible portion of plane is invalid\n"); 91 return -EINVAL; 92 } 93 94 if (new_plane_state->fb->pitches[0] % 128 != 0) { 95 drm_dbg_atomic(plane->dev, "wrong stride with 128-byte aligned\n"); 96 return -EINVAL; 97 } 98 return 0; 99 } 100 101 static void hibmc_plane_atomic_update(struct drm_plane *plane, 102 struct drm_atomic_state *state) 103 { 104 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 105 plane); 106 u32 reg; 107 s64 gpu_addr = 0; 108 u32 line_l; 109 struct hibmc_drm_private *priv = to_hibmc_drm_private(plane->dev); 110 struct drm_gem_vram_object *gbo; 111 112 if (!new_state->fb) 113 return; 114 115 gbo = drm_gem_vram_of_gem(new_state->fb->obj[0]); 116 117 gpu_addr = drm_gem_vram_offset(gbo); 118 if (WARN_ON_ONCE(gpu_addr < 0)) 119 return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */ 120 121 writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS); 122 123 reg = new_state->fb->width * (new_state->fb->format->cpp[0]); 124 125 line_l = new_state->fb->pitches[0]; 126 writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) | 127 HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_OFFS, line_l), 128 priv->mmio + HIBMC_CRT_FB_WIDTH); 129 130 /* SET PIXEL FORMAT */ 131 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); 132 reg &= ~HIBMC_CRT_DISP_CTL_FORMAT_MASK; 133 reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT, 134 new_state->fb->format->cpp[0] * 8 / 16); 135 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); 136 } 137 138 static const u32 channel_formats1[] = { 139 DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888, 140 DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, 141 DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888, 142 DRM_FORMAT_ABGR8888 143 }; 144 145 static const struct drm_plane_funcs hibmc_plane_funcs = { 146 .update_plane = drm_atomic_helper_update_plane, 147 .disable_plane = drm_atomic_helper_disable_plane, 148 .destroy = drm_plane_cleanup, 149 .reset = drm_atomic_helper_plane_reset, 150 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 151 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 152 }; 153 154 static const struct drm_plane_helper_funcs hibmc_plane_helper_funcs = { 155 .prepare_fb = drm_gem_vram_plane_helper_prepare_fb, 156 .cleanup_fb = drm_gem_vram_plane_helper_cleanup_fb, 157 .atomic_check = hibmc_plane_atomic_check, 158 .atomic_update = hibmc_plane_atomic_update, 159 }; 160 161 static void hibmc_crtc_dpms(struct drm_crtc *crtc, u32 dpms) 162 { 163 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); 164 u32 reg; 165 166 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); 167 reg &= ~HIBMC_CRT_DISP_CTL_DPMS_MASK; 168 reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_DPMS, dpms); 169 reg &= ~HIBMC_CRT_DISP_CTL_TIMING_MASK; 170 if (dpms == HIBMC_CRT_DPMS_ON) 171 reg |= HIBMC_CRT_DISP_CTL_TIMING(1); 172 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); 173 } 174 175 static void hibmc_crtc_atomic_enable(struct drm_crtc *crtc, 176 struct drm_atomic_state *state) 177 { 178 u32 reg; 179 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); 180 181 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0); 182 183 /* Enable display power gate & LOCALMEM power gate*/ 184 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 185 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 186 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 187 reg |= HIBMC_CURR_GATE_LOCALMEM(1); 188 reg |= HIBMC_CURR_GATE_DISPLAY(1); 189 hibmc_set_current_gate(priv, reg); 190 drm_crtc_vblank_on(crtc); 191 hibmc_crtc_dpms(crtc, HIBMC_CRT_DPMS_ON); 192 } 193 194 static void hibmc_crtc_atomic_disable(struct drm_crtc *crtc, 195 struct drm_atomic_state *state) 196 { 197 u32 reg; 198 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); 199 200 hibmc_crtc_dpms(crtc, HIBMC_CRT_DPMS_OFF); 201 drm_crtc_vblank_off(crtc); 202 203 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_SLEEP); 204 205 /* Enable display power gate & LOCALMEM power gate*/ 206 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 207 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 208 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 209 reg |= HIBMC_CURR_GATE_LOCALMEM(0); 210 reg |= HIBMC_CURR_GATE_DISPLAY(0); 211 hibmc_set_current_gate(priv, reg); 212 } 213 214 static enum drm_mode_status 215 hibmc_crtc_mode_valid(struct drm_crtc *crtc, 216 const struct drm_display_mode *mode) 217 { 218 size_t i = 0; 219 int vrefresh = drm_mode_vrefresh(mode); 220 221 if (vrefresh < 59 || vrefresh > 61) 222 return MODE_NOCLOCK; 223 224 for (i = 0; i < ARRAY_SIZE(hibmc_pll_table); i++) { 225 if (hibmc_pll_table[i].hdisplay == mode->hdisplay && 226 hibmc_pll_table[i].vdisplay == mode->vdisplay) 227 return MODE_OK; 228 } 229 230 return MODE_BAD; 231 } 232 233 static u32 format_pll_reg(void) 234 { 235 u32 pllreg = 0; 236 struct hibmc_display_panel_pll pll = {0}; 237 238 /* 239 * Note that all PLL's have the same format. Here, 240 * we just use Panel PLL parameter to work out the bit 241 * fields in the register.On returning a 32 bit number, the value can 242 * be applied to any PLL in the calling function. 243 */ 244 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_BYPASS, 0); 245 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POWER, 1); 246 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_INPUT, 0); 247 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD); 248 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD); 249 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N); 250 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M); 251 252 return pllreg; 253 } 254 255 static void set_vclock_hisilicon(struct drm_device *dev, u64 pll) 256 { 257 u32 val; 258 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev); 259 260 val = readl(priv->mmio + CRT_PLL1_HS); 261 val &= ~(CRT_PLL1_HS_OUTER_BYPASS(1)); 262 writel(val, priv->mmio + CRT_PLL1_HS); 263 264 val = CRT_PLL1_HS_INTER_BYPASS(1) | CRT_PLL1_HS_POWERON(1); 265 writel(val, priv->mmio + CRT_PLL1_HS); 266 267 writel(pll, priv->mmio + CRT_PLL1_HS); 268 269 usleep_range(1000, 2000); 270 271 val = pll & ~(CRT_PLL1_HS_POWERON(1)); 272 writel(val, priv->mmio + CRT_PLL1_HS); 273 274 usleep_range(1000, 2000); 275 276 val &= ~(CRT_PLL1_HS_INTER_BYPASS(1)); 277 writel(val, priv->mmio + CRT_PLL1_HS); 278 279 usleep_range(1000, 2000); 280 281 val |= CRT_PLL1_HS_OUTER_BYPASS(1); 282 writel(val, priv->mmio + CRT_PLL1_HS); 283 } 284 285 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) 286 { 287 size_t i; 288 size_t count = ARRAY_SIZE(hibmc_pll_table); 289 290 for (i = 0; i < count; i++) { 291 if (hibmc_pll_table[i].hdisplay == x && 292 hibmc_pll_table[i].vdisplay == y) { 293 *pll1 = hibmc_pll_table[i].pll1_config_value; 294 *pll2 = hibmc_pll_table[i].pll2_config_value; 295 return; 296 } 297 } 298 299 /* if found none, we use default value */ 300 *pll1 = CRT_PLL1_HS_25MHZ; 301 *pll2 = CRT_PLL2_HS_25MHZ; 302 } 303 304 /* 305 * This function takes care the extra registers and bit fields required to 306 * setup a mode in board. 307 * Explanation about Display Control register: 308 * FPGA only supports 7 predefined pixel clocks, and clock select is 309 * in bit 4:0 of new register 0x802a8. 310 */ 311 static u32 display_ctrl_adjust(struct drm_device *dev, 312 struct drm_display_mode *mode, 313 u32 ctrl) 314 { 315 u64 x, y; 316 u32 pll1; /* bit[31:0] of PLL */ 317 u32 pll2; /* bit[63:32] of PLL */ 318 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev); 319 320 x = mode->hdisplay; 321 y = mode->vdisplay; 322 323 get_pll_config(x, y, &pll1, &pll2); 324 writel(pll2, priv->mmio + CRT_PLL2_HS); 325 set_vclock_hisilicon(dev, pll1); 326 327 /* 328 * Hisilicon has to set up the top-left and bottom-right 329 * registers as well. 330 * Note that normal chip only use those two register for 331 * auto-centering mode. 332 */ 333 writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_TOP, 0) | 334 HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_LEFT, 0), 335 priv->mmio + HIBMC_CRT_AUTO_CENTERING_TL); 336 337 writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM, y - 1) | 338 HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_RIGHT, x - 1), 339 priv->mmio + HIBMC_CRT_AUTO_CENTERING_BR); 340 341 /* 342 * Assume common fields in ctrl have been properly set before 343 * calling this function. 344 * This function only sets the extra fields in ctrl. 345 */ 346 347 /* Set bit 25 of display controller: Select CRT or VGA clock */ 348 ctrl &= ~HIBMC_CRT_DISP_CTL_CRTSELECT_MASK; 349 ctrl &= ~HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK; 350 351 ctrl |= HIBMC_CRT_DISP_CTL_CRTSELECT(HIBMC_CRTSELECT_CRT); 352 353 /* clock_phase_polarity is 0 */ 354 ctrl |= HIBMC_CRT_DISP_CTL_CLOCK_PHASE(0); 355 356 writel(ctrl, priv->mmio + HIBMC_CRT_DISP_CTL); 357 358 return ctrl; 359 } 360 361 static void hibmc_crtc_mode_set_nofb(struct drm_crtc *crtc) 362 { 363 u32 val; 364 struct drm_display_mode *mode = &crtc->state->mode; 365 struct drm_device *dev = crtc->dev; 366 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev); 367 u32 width = mode->hsync_end - mode->hsync_start; 368 u32 height = mode->vsync_end - mode->vsync_start; 369 370 writel(format_pll_reg(), priv->mmio + HIBMC_CRT_PLL_CTRL); 371 writel(HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_TOTAL, mode->htotal - 1) | 372 HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_DISP_END, mode->hdisplay - 1), 373 priv->mmio + HIBMC_CRT_HORZ_TOTAL); 374 375 writel(HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_WIDTH, width) | 376 HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_START, mode->hsync_start - 1), 377 priv->mmio + HIBMC_CRT_HORZ_SYNC); 378 379 writel(HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_TOTAL, mode->vtotal - 1) | 380 HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_DISP_END, mode->vdisplay - 1), 381 priv->mmio + HIBMC_CRT_VERT_TOTAL); 382 383 writel(HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_HEIGHT, height) | 384 HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_START, mode->vsync_start - 1), 385 priv->mmio + HIBMC_CRT_VERT_SYNC); 386 387 val = HIBMC_FIELD(HIBMC_CRT_DISP_CTL_VSYNC_PHASE, 0); 388 val |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_HSYNC_PHASE, 0); 389 val |= HIBMC_CRT_DISP_CTL_TIMING(1); 390 val |= HIBMC_CRT_DISP_CTL_PLANE(1); 391 392 display_ctrl_adjust(dev, mode, val); 393 } 394 395 static void hibmc_crtc_atomic_begin(struct drm_crtc *crtc, 396 struct drm_atomic_state *state) 397 { 398 u32 reg; 399 struct drm_device *dev = crtc->dev; 400 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev); 401 402 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0); 403 404 /* Enable display power gate & LOCALMEM power gate*/ 405 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 406 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 407 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 408 reg |= HIBMC_CURR_GATE_DISPLAY(1); 409 reg |= HIBMC_CURR_GATE_LOCALMEM(1); 410 hibmc_set_current_gate(priv, reg); 411 412 /* We can add more initialization as needed. */ 413 } 414 415 static void hibmc_crtc_atomic_flush(struct drm_crtc *crtc, 416 struct drm_atomic_state *state) 417 418 { 419 unsigned long flags; 420 421 spin_lock_irqsave(&crtc->dev->event_lock, flags); 422 if (crtc->state->event) 423 drm_crtc_send_vblank_event(crtc, crtc->state->event); 424 crtc->state->event = NULL; 425 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 426 } 427 428 static int hibmc_crtc_enable_vblank(struct drm_crtc *crtc) 429 { 430 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); 431 432 writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(1), 433 priv->mmio + HIBMC_RAW_INTERRUPT_EN); 434 435 return 0; 436 } 437 438 static void hibmc_crtc_disable_vblank(struct drm_crtc *crtc) 439 { 440 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); 441 442 writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(0), 443 priv->mmio + HIBMC_RAW_INTERRUPT_EN); 444 } 445 446 static void hibmc_crtc_load_lut(struct drm_crtc *crtc) 447 { 448 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); 449 void __iomem *mmio = priv->mmio; 450 u16 *r, *g, *b; 451 u32 reg; 452 u32 i; 453 454 r = crtc->gamma_store; 455 g = r + crtc->gamma_size; 456 b = g + crtc->gamma_size; 457 458 for (i = 0; i < crtc->gamma_size; i++) { 459 u32 offset = i << 2; 460 u8 red = *r++ >> 8; 461 u8 green = *g++ >> 8; 462 u8 blue = *b++ >> 8; 463 u32 rgb = (red << 16) | (green << 8) | blue; 464 465 writel(rgb, mmio + HIBMC_CRT_PALETTE + offset); 466 } 467 468 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); 469 reg |= HIBMC_FIELD(HIBMC_CTL_DISP_CTL_GAMMA, 1); 470 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); 471 } 472 473 static int hibmc_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 474 u16 *blue, uint32_t size, 475 struct drm_modeset_acquire_ctx *ctx) 476 { 477 hibmc_crtc_load_lut(crtc); 478 479 return 0; 480 } 481 482 static const struct drm_crtc_funcs hibmc_crtc_funcs = { 483 .page_flip = drm_atomic_helper_page_flip, 484 .set_config = drm_atomic_helper_set_config, 485 .destroy = drm_crtc_cleanup, 486 .reset = drm_atomic_helper_crtc_reset, 487 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 488 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 489 .enable_vblank = hibmc_crtc_enable_vblank, 490 .disable_vblank = hibmc_crtc_disable_vblank, 491 .gamma_set = hibmc_crtc_gamma_set, 492 }; 493 494 static const struct drm_crtc_helper_funcs hibmc_crtc_helper_funcs = { 495 .mode_set_nofb = hibmc_crtc_mode_set_nofb, 496 .atomic_begin = hibmc_crtc_atomic_begin, 497 .atomic_flush = hibmc_crtc_atomic_flush, 498 .atomic_enable = hibmc_crtc_atomic_enable, 499 .atomic_disable = hibmc_crtc_atomic_disable, 500 .mode_valid = hibmc_crtc_mode_valid, 501 }; 502 503 int hibmc_de_init(struct hibmc_drm_private *priv) 504 { 505 struct drm_device *dev = &priv->dev; 506 struct drm_crtc *crtc = &priv->crtc; 507 struct drm_plane *plane = &priv->primary_plane; 508 int ret; 509 510 ret = drm_universal_plane_init(dev, plane, 1, &hibmc_plane_funcs, 511 channel_formats1, 512 ARRAY_SIZE(channel_formats1), 513 NULL, 514 DRM_PLANE_TYPE_PRIMARY, 515 NULL); 516 517 if (ret) { 518 drm_err(dev, "failed to init plane: %d\n", ret); 519 return ret; 520 } 521 522 drm_plane_helper_add(plane, &hibmc_plane_helper_funcs); 523 524 ret = drm_crtc_init_with_planes(dev, crtc, plane, 525 NULL, &hibmc_crtc_funcs, NULL); 526 if (ret) { 527 drm_err(dev, "failed to init crtc: %d\n", ret); 528 return ret; 529 } 530 531 ret = drm_mode_crtc_set_gamma_size(crtc, 256); 532 if (ret) { 533 drm_err(dev, "failed to set gamma size: %d\n", ret); 534 return ret; 535 } 536 drm_crtc_helper_add(crtc, &hibmc_crtc_helper_funcs); 537 538 return 0; 539 } 540