1 /************************************************************************** 2 * Copyright (c) 2007, Intel Corporation. 3 * All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 17 * 18 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 19 * develop this driver. 20 * 21 **************************************************************************/ 22 /* 23 */ 24 25 #include <drm/drm_vblank.h> 26 27 #include "mdfld_output.h" 28 #include "power.h" 29 #include "psb_drv.h" 30 #include "psb_intel_reg.h" 31 #include "psb_irq.h" 32 #include "psb_reg.h" 33 34 /* 35 * inline functions 36 */ 37 38 static inline u32 39 psb_pipestat(int pipe) 40 { 41 if (pipe == 0) 42 return PIPEASTAT; 43 if (pipe == 1) 44 return PIPEBSTAT; 45 if (pipe == 2) 46 return PIPECSTAT; 47 BUG(); 48 } 49 50 static inline u32 51 mid_pipe_event(int pipe) 52 { 53 if (pipe == 0) 54 return _PSB_PIPEA_EVENT_FLAG; 55 if (pipe == 1) 56 return _MDFLD_PIPEB_EVENT_FLAG; 57 if (pipe == 2) 58 return _MDFLD_PIPEC_EVENT_FLAG; 59 BUG(); 60 } 61 62 static inline u32 63 mid_pipe_vsync(int pipe) 64 { 65 if (pipe == 0) 66 return _PSB_VSYNC_PIPEA_FLAG; 67 if (pipe == 1) 68 return _PSB_VSYNC_PIPEB_FLAG; 69 if (pipe == 2) 70 return _MDFLD_PIPEC_VBLANK_FLAG; 71 BUG(); 72 } 73 74 static inline u32 75 mid_pipeconf(int pipe) 76 { 77 if (pipe == 0) 78 return PIPEACONF; 79 if (pipe == 1) 80 return PIPEBCONF; 81 if (pipe == 2) 82 return PIPECCONF; 83 BUG(); 84 } 85 86 void 87 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) 88 { 89 if ((dev_priv->pipestat[pipe] & mask) != mask) { 90 u32 reg = psb_pipestat(pipe); 91 dev_priv->pipestat[pipe] |= mask; 92 /* Enable the interrupt, clear any pending status */ 93 if (gma_power_begin(dev_priv->dev, false)) { 94 u32 writeVal = PSB_RVDC32(reg); 95 writeVal |= (mask | (mask >> 16)); 96 PSB_WVDC32(writeVal, reg); 97 (void) PSB_RVDC32(reg); 98 gma_power_end(dev_priv->dev); 99 } 100 } 101 } 102 103 void 104 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) 105 { 106 if ((dev_priv->pipestat[pipe] & mask) != 0) { 107 u32 reg = psb_pipestat(pipe); 108 dev_priv->pipestat[pipe] &= ~mask; 109 if (gma_power_begin(dev_priv->dev, false)) { 110 u32 writeVal = PSB_RVDC32(reg); 111 writeVal &= ~mask; 112 PSB_WVDC32(writeVal, reg); 113 (void) PSB_RVDC32(reg); 114 gma_power_end(dev_priv->dev); 115 } 116 } 117 } 118 119 static void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe) 120 { 121 if (gma_power_begin(dev_priv->dev, false)) { 122 u32 pipe_event = mid_pipe_event(pipe); 123 dev_priv->vdc_irq_mask |= pipe_event; 124 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 125 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 126 gma_power_end(dev_priv->dev); 127 } 128 } 129 130 static void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe) 131 { 132 if (dev_priv->pipestat[pipe] == 0) { 133 if (gma_power_begin(dev_priv->dev, false)) { 134 u32 pipe_event = mid_pipe_event(pipe); 135 dev_priv->vdc_irq_mask &= ~pipe_event; 136 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 137 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 138 gma_power_end(dev_priv->dev); 139 } 140 } 141 } 142 143 /** 144 * Display controller interrupt handler for pipe event. 145 * 146 */ 147 static void mid_pipe_event_handler(struct drm_device *dev, int pipe) 148 { 149 struct drm_psb_private *dev_priv = 150 (struct drm_psb_private *) dev->dev_private; 151 152 uint32_t pipe_stat_val = 0; 153 uint32_t pipe_stat_reg = psb_pipestat(pipe); 154 uint32_t pipe_enable = dev_priv->pipestat[pipe]; 155 uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16; 156 uint32_t pipe_clear; 157 uint32_t i = 0; 158 159 spin_lock(&dev_priv->irqmask_lock); 160 161 pipe_stat_val = PSB_RVDC32(pipe_stat_reg); 162 pipe_stat_val &= pipe_enable | pipe_status; 163 pipe_stat_val &= pipe_stat_val >> 16; 164 165 spin_unlock(&dev_priv->irqmask_lock); 166 167 /* Clear the 2nd level interrupt status bits 168 * Sometimes the bits are very sticky so we repeat until they unstick */ 169 for (i = 0; i < 0xffff; i++) { 170 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg); 171 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status; 172 173 if (pipe_clear == 0) 174 break; 175 } 176 177 if (pipe_clear) 178 dev_err(dev->dev, 179 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n", 180 __func__, pipe, PSB_RVDC32(pipe_stat_reg)); 181 182 if (pipe_stat_val & PIPE_VBLANK_STATUS) 183 drm_handle_vblank(dev, pipe); 184 185 if (pipe_stat_val & PIPE_TE_STATUS) 186 drm_handle_vblank(dev, pipe); 187 } 188 189 /* 190 * Display controller interrupt handler. 191 */ 192 static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat) 193 { 194 if (vdc_stat & _PSB_IRQ_ASLE) 195 psb_intel_opregion_asle_intr(dev); 196 197 if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG) 198 mid_pipe_event_handler(dev, 0); 199 200 if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG) 201 mid_pipe_event_handler(dev, 1); 202 } 203 204 /* 205 * SGX interrupt handler 206 */ 207 static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2) 208 { 209 struct drm_psb_private *dev_priv = dev->dev_private; 210 u32 val, addr; 211 int error = false; 212 213 if (stat_1 & _PSB_CE_TWOD_COMPLETE) 214 val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS); 215 216 if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) { 217 val = PSB_RSGX32(PSB_CR_BIF_INT_STAT); 218 addr = PSB_RSGX32(PSB_CR_BIF_FAULT); 219 if (val) { 220 if (val & _PSB_CBI_STAT_PF_N_RW) 221 DRM_ERROR("SGX MMU page fault:"); 222 else 223 DRM_ERROR("SGX MMU read / write protection fault:"); 224 225 if (val & _PSB_CBI_STAT_FAULT_CACHE) 226 DRM_ERROR("\tCache requestor"); 227 if (val & _PSB_CBI_STAT_FAULT_TA) 228 DRM_ERROR("\tTA requestor"); 229 if (val & _PSB_CBI_STAT_FAULT_VDM) 230 DRM_ERROR("\tVDM requestor"); 231 if (val & _PSB_CBI_STAT_FAULT_2D) 232 DRM_ERROR("\t2D requestor"); 233 if (val & _PSB_CBI_STAT_FAULT_PBE) 234 DRM_ERROR("\tPBE requestor"); 235 if (val & _PSB_CBI_STAT_FAULT_TSP) 236 DRM_ERROR("\tTSP requestor"); 237 if (val & _PSB_CBI_STAT_FAULT_ISP) 238 DRM_ERROR("\tISP requestor"); 239 if (val & _PSB_CBI_STAT_FAULT_USSEPDS) 240 DRM_ERROR("\tUSSEPDS requestor"); 241 if (val & _PSB_CBI_STAT_FAULT_HOST) 242 DRM_ERROR("\tHost requestor"); 243 244 DRM_ERROR("\tMMU failing address is 0x%08x.\n", 245 (unsigned int)addr); 246 error = true; 247 } 248 } 249 250 /* Clear bits */ 251 PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR); 252 PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2); 253 PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2); 254 } 255 256 irqreturn_t psb_irq_handler(int irq, void *arg) 257 { 258 struct drm_device *dev = arg; 259 struct drm_psb_private *dev_priv = dev->dev_private; 260 uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0; 261 u32 sgx_stat_1, sgx_stat_2; 262 int handled = 0; 263 264 spin_lock(&dev_priv->irqmask_lock); 265 266 vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R); 267 268 if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE)) 269 dsp_int = 1; 270 271 /* FIXME: Handle Medfield 272 if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG) 273 dsp_int = 1; 274 */ 275 276 if (vdc_stat & _PSB_IRQ_SGX_FLAG) 277 sgx_int = 1; 278 if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC) 279 hotplug_int = 1; 280 281 vdc_stat &= dev_priv->vdc_irq_mask; 282 spin_unlock(&dev_priv->irqmask_lock); 283 284 if (dsp_int && gma_power_is_on(dev)) { 285 psb_vdc_interrupt(dev, vdc_stat); 286 handled = 1; 287 } 288 289 if (sgx_int) { 290 sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS); 291 sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2); 292 psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2); 293 handled = 1; 294 } 295 296 /* Note: this bit has other meanings on some devices, so we will 297 need to address that later if it ever matters */ 298 if (hotplug_int && dev_priv->ops->hotplug) { 299 handled = dev_priv->ops->hotplug(dev); 300 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); 301 } 302 303 PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R); 304 (void) PSB_RVDC32(PSB_INT_IDENTITY_R); 305 rmb(); 306 307 if (!handled) 308 return IRQ_NONE; 309 310 return IRQ_HANDLED; 311 } 312 313 void psb_irq_preinstall(struct drm_device *dev) 314 { 315 struct drm_psb_private *dev_priv = 316 (struct drm_psb_private *) dev->dev_private; 317 unsigned long irqflags; 318 319 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 320 321 if (gma_power_is_on(dev)) { 322 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); 323 PSB_WVDC32(0x00000000, PSB_INT_MASK_R); 324 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R); 325 PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE); 326 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); 327 } 328 if (dev->vblank[0].enabled) 329 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG; 330 if (dev->vblank[1].enabled) 331 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG; 332 333 /* FIXME: Handle Medfield irq mask 334 if (dev->vblank[1].enabled) 335 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG; 336 if (dev->vblank[2].enabled) 337 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG; 338 */ 339 340 /* Revisit this area - want per device masks ? */ 341 if (dev_priv->ops->hotplug) 342 dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC; 343 dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG; 344 345 /* This register is safe even if display island is off */ 346 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 347 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 348 } 349 350 int psb_irq_postinstall(struct drm_device *dev) 351 { 352 struct drm_psb_private *dev_priv = dev->dev_private; 353 unsigned long irqflags; 354 355 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 356 357 /* Enable 2D and MMU fault interrupts */ 358 PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2); 359 PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE); 360 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */ 361 362 /* This register is safe even if display island is off */ 363 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 364 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); 365 366 if (dev->vblank[0].enabled) 367 psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE); 368 else 369 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE); 370 371 if (dev->vblank[1].enabled) 372 psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE); 373 else 374 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE); 375 376 if (dev->vblank[2].enabled) 377 psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE); 378 else 379 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE); 380 381 if (dev_priv->ops->hotplug_enable) 382 dev_priv->ops->hotplug_enable(dev, true); 383 384 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 385 return 0; 386 } 387 388 void psb_irq_uninstall(struct drm_device *dev) 389 { 390 struct drm_psb_private *dev_priv = dev->dev_private; 391 unsigned long irqflags; 392 393 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 394 395 if (dev_priv->ops->hotplug_enable) 396 dev_priv->ops->hotplug_enable(dev, false); 397 398 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); 399 400 if (dev->vblank[0].enabled) 401 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE); 402 403 if (dev->vblank[1].enabled) 404 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE); 405 406 if (dev->vblank[2].enabled) 407 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE); 408 409 dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG | 410 _PSB_IRQ_MSVDX_FLAG | 411 _LNC_IRQ_TOPAZ_FLAG; 412 413 /* These two registers are safe even if display island is off */ 414 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 415 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 416 417 wmb(); 418 419 /* This register is safe even if display island is off */ 420 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R); 421 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 422 } 423 424 void psb_irq_turn_on_dpst(struct drm_device *dev) 425 { 426 struct drm_psb_private *dev_priv = 427 (struct drm_psb_private *) dev->dev_private; 428 u32 hist_reg; 429 u32 pwm_reg; 430 431 if (gma_power_begin(dev, false)) { 432 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL); 433 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL); 434 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL); 435 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL); 436 437 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC); 438 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); 439 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE 440 | PWM_PHASEIN_INT_ENABLE, 441 PWM_CONTROL_LOGIC); 442 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); 443 444 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE); 445 446 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL); 447 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR, 448 HISTOGRAM_INT_CONTROL); 449 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); 450 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE, 451 PWM_CONTROL_LOGIC); 452 453 gma_power_end(dev); 454 } 455 } 456 457 int psb_irq_enable_dpst(struct drm_device *dev) 458 { 459 struct drm_psb_private *dev_priv = 460 (struct drm_psb_private *) dev->dev_private; 461 unsigned long irqflags; 462 463 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 464 465 /* enable DPST */ 466 mid_enable_pipe_event(dev_priv, 0); 467 psb_irq_turn_on_dpst(dev); 468 469 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 470 return 0; 471 } 472 473 void psb_irq_turn_off_dpst(struct drm_device *dev) 474 { 475 struct drm_psb_private *dev_priv = 476 (struct drm_psb_private *) dev->dev_private; 477 u32 hist_reg; 478 u32 pwm_reg; 479 480 if (gma_power_begin(dev, false)) { 481 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL); 482 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL); 483 484 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE); 485 486 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); 487 PSB_WVDC32(pwm_reg & ~PWM_PHASEIN_INT_ENABLE, 488 PWM_CONTROL_LOGIC); 489 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); 490 491 gma_power_end(dev); 492 } 493 } 494 495 int psb_irq_disable_dpst(struct drm_device *dev) 496 { 497 struct drm_psb_private *dev_priv = 498 (struct drm_psb_private *) dev->dev_private; 499 unsigned long irqflags; 500 501 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 502 503 mid_disable_pipe_event(dev_priv, 0); 504 psb_irq_turn_off_dpst(dev); 505 506 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 507 508 return 0; 509 } 510 511 /* 512 * It is used to enable VBLANK interrupt 513 */ 514 int psb_enable_vblank(struct drm_device *dev, unsigned int pipe) 515 { 516 struct drm_psb_private *dev_priv = dev->dev_private; 517 unsigned long irqflags; 518 uint32_t reg_val = 0; 519 uint32_t pipeconf_reg = mid_pipeconf(pipe); 520 521 /* Medfield is different - we should perhaps extract out vblank 522 and blacklight etc ops */ 523 if (IS_MFLD(dev)) 524 return mdfld_enable_te(dev, pipe); 525 526 if (gma_power_begin(dev, false)) { 527 reg_val = REG_READ(pipeconf_reg); 528 gma_power_end(dev); 529 } 530 531 if (!(reg_val & PIPEACONF_ENABLE)) 532 return -EINVAL; 533 534 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 535 536 if (pipe == 0) 537 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG; 538 else if (pipe == 1) 539 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG; 540 541 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 542 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 543 psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE); 544 545 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 546 547 return 0; 548 } 549 550 /* 551 * It is used to disable VBLANK interrupt 552 */ 553 void psb_disable_vblank(struct drm_device *dev, unsigned int pipe) 554 { 555 struct drm_psb_private *dev_priv = dev->dev_private; 556 unsigned long irqflags; 557 558 if (IS_MFLD(dev)) 559 mdfld_disable_te(dev, pipe); 560 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 561 562 if (pipe == 0) 563 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG; 564 else if (pipe == 1) 565 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG; 566 567 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 568 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 569 psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE); 570 571 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 572 } 573 574 /* 575 * It is used to enable TE interrupt 576 */ 577 int mdfld_enable_te(struct drm_device *dev, int pipe) 578 { 579 struct drm_psb_private *dev_priv = 580 (struct drm_psb_private *) dev->dev_private; 581 unsigned long irqflags; 582 uint32_t reg_val = 0; 583 uint32_t pipeconf_reg = mid_pipeconf(pipe); 584 585 if (gma_power_begin(dev, false)) { 586 reg_val = REG_READ(pipeconf_reg); 587 gma_power_end(dev); 588 } 589 590 if (!(reg_val & PIPEACONF_ENABLE)) 591 return -EINVAL; 592 593 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 594 595 mid_enable_pipe_event(dev_priv, pipe); 596 psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE); 597 598 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 599 600 return 0; 601 } 602 603 /* 604 * It is used to disable TE interrupt 605 */ 606 void mdfld_disable_te(struct drm_device *dev, int pipe) 607 { 608 struct drm_psb_private *dev_priv = 609 (struct drm_psb_private *) dev->dev_private; 610 unsigned long irqflags; 611 612 if (!dev_priv->dsr_enable) 613 return; 614 615 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 616 617 mid_disable_pipe_event(dev_priv, pipe); 618 psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE); 619 620 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 621 } 622 623 /* Called from drm generic code, passed a 'crtc', which 624 * we use as a pipe index 625 */ 626 u32 psb_get_vblank_counter(struct drm_device *dev, unsigned int pipe) 627 { 628 uint32_t high_frame = PIPEAFRAMEHIGH; 629 uint32_t low_frame = PIPEAFRAMEPIXEL; 630 uint32_t pipeconf_reg = PIPEACONF; 631 uint32_t reg_val = 0; 632 uint32_t high1 = 0, high2 = 0, low = 0, count = 0; 633 634 switch (pipe) { 635 case 0: 636 break; 637 case 1: 638 high_frame = PIPEBFRAMEHIGH; 639 low_frame = PIPEBFRAMEPIXEL; 640 pipeconf_reg = PIPEBCONF; 641 break; 642 case 2: 643 high_frame = PIPECFRAMEHIGH; 644 low_frame = PIPECFRAMEPIXEL; 645 pipeconf_reg = PIPECCONF; 646 break; 647 default: 648 dev_err(dev->dev, "%s, invalid pipe.\n", __func__); 649 return 0; 650 } 651 652 if (!gma_power_begin(dev, false)) 653 return 0; 654 655 reg_val = REG_READ(pipeconf_reg); 656 657 if (!(reg_val & PIPEACONF_ENABLE)) { 658 dev_err(dev->dev, "trying to get vblank count for disabled pipe %u\n", 659 pipe); 660 goto psb_get_vblank_counter_exit; 661 } 662 663 /* 664 * High & low register fields aren't synchronized, so make sure 665 * we get a low value that's stable across two reads of the high 666 * register. 667 */ 668 do { 669 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> 670 PIPE_FRAME_HIGH_SHIFT); 671 low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> 672 PIPE_FRAME_LOW_SHIFT); 673 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> 674 PIPE_FRAME_HIGH_SHIFT); 675 } while (high1 != high2); 676 677 count = (high1 << 8) | low; 678 679 psb_get_vblank_counter_exit: 680 681 gma_power_end(dev); 682 683 return count; 684 } 685 686