1 // SPDX-License-Identifier: GPL-2.0-only 2 /************************************************************************** 3 * Copyright (c) 2007, Intel Corporation. 4 * All Rights Reserved. 5 * 6 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 7 * develop this driver. 8 * 9 **************************************************************************/ 10 11 #include <drm/drm_vblank.h> 12 13 #include "mdfld_output.h" 14 #include "power.h" 15 #include "psb_drv.h" 16 #include "psb_intel_reg.h" 17 #include "psb_irq.h" 18 #include "psb_reg.h" 19 20 /* 21 * inline functions 22 */ 23 24 static inline u32 25 psb_pipestat(int pipe) 26 { 27 if (pipe == 0) 28 return PIPEASTAT; 29 if (pipe == 1) 30 return PIPEBSTAT; 31 if (pipe == 2) 32 return PIPECSTAT; 33 BUG(); 34 } 35 36 static inline u32 37 mid_pipe_event(int pipe) 38 { 39 if (pipe == 0) 40 return _PSB_PIPEA_EVENT_FLAG; 41 if (pipe == 1) 42 return _MDFLD_PIPEB_EVENT_FLAG; 43 if (pipe == 2) 44 return _MDFLD_PIPEC_EVENT_FLAG; 45 BUG(); 46 } 47 48 static inline u32 49 mid_pipe_vsync(int pipe) 50 { 51 if (pipe == 0) 52 return _PSB_VSYNC_PIPEA_FLAG; 53 if (pipe == 1) 54 return _PSB_VSYNC_PIPEB_FLAG; 55 if (pipe == 2) 56 return _MDFLD_PIPEC_VBLANK_FLAG; 57 BUG(); 58 } 59 60 static inline u32 61 mid_pipeconf(int pipe) 62 { 63 if (pipe == 0) 64 return PIPEACONF; 65 if (pipe == 1) 66 return PIPEBCONF; 67 if (pipe == 2) 68 return PIPECCONF; 69 BUG(); 70 } 71 72 void 73 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) 74 { 75 if ((dev_priv->pipestat[pipe] & mask) != mask) { 76 u32 reg = psb_pipestat(pipe); 77 dev_priv->pipestat[pipe] |= mask; 78 /* Enable the interrupt, clear any pending status */ 79 if (gma_power_begin(dev_priv->dev, false)) { 80 u32 writeVal = PSB_RVDC32(reg); 81 writeVal |= (mask | (mask >> 16)); 82 PSB_WVDC32(writeVal, reg); 83 (void) PSB_RVDC32(reg); 84 gma_power_end(dev_priv->dev); 85 } 86 } 87 } 88 89 void 90 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) 91 { 92 if ((dev_priv->pipestat[pipe] & mask) != 0) { 93 u32 reg = psb_pipestat(pipe); 94 dev_priv->pipestat[pipe] &= ~mask; 95 if (gma_power_begin(dev_priv->dev, false)) { 96 u32 writeVal = PSB_RVDC32(reg); 97 writeVal &= ~mask; 98 PSB_WVDC32(writeVal, reg); 99 (void) PSB_RVDC32(reg); 100 gma_power_end(dev_priv->dev); 101 } 102 } 103 } 104 105 static void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe) 106 { 107 if (gma_power_begin(dev_priv->dev, false)) { 108 u32 pipe_event = mid_pipe_event(pipe); 109 dev_priv->vdc_irq_mask |= pipe_event; 110 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 111 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 112 gma_power_end(dev_priv->dev); 113 } 114 } 115 116 static void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe) 117 { 118 if (dev_priv->pipestat[pipe] == 0) { 119 if (gma_power_begin(dev_priv->dev, false)) { 120 u32 pipe_event = mid_pipe_event(pipe); 121 dev_priv->vdc_irq_mask &= ~pipe_event; 122 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 123 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 124 gma_power_end(dev_priv->dev); 125 } 126 } 127 } 128 129 /* 130 * Display controller interrupt handler for pipe event. 131 */ 132 static void mid_pipe_event_handler(struct drm_device *dev, int pipe) 133 { 134 struct drm_psb_private *dev_priv = 135 (struct drm_psb_private *) dev->dev_private; 136 137 uint32_t pipe_stat_val = 0; 138 uint32_t pipe_stat_reg = psb_pipestat(pipe); 139 uint32_t pipe_enable = dev_priv->pipestat[pipe]; 140 uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16; 141 uint32_t pipe_clear; 142 uint32_t i = 0; 143 144 spin_lock(&dev_priv->irqmask_lock); 145 146 pipe_stat_val = PSB_RVDC32(pipe_stat_reg); 147 pipe_stat_val &= pipe_enable | pipe_status; 148 pipe_stat_val &= pipe_stat_val >> 16; 149 150 spin_unlock(&dev_priv->irqmask_lock); 151 152 /* Clear the 2nd level interrupt status bits 153 * Sometimes the bits are very sticky so we repeat until they unstick */ 154 for (i = 0; i < 0xffff; i++) { 155 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg); 156 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status; 157 158 if (pipe_clear == 0) 159 break; 160 } 161 162 if (pipe_clear) 163 dev_err(dev->dev, 164 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n", 165 __func__, pipe, PSB_RVDC32(pipe_stat_reg)); 166 167 if (pipe_stat_val & PIPE_VBLANK_STATUS || 168 (IS_MFLD(dev) && pipe_stat_val & PIPE_TE_STATUS)) { 169 struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe); 170 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 171 unsigned long flags; 172 173 drm_handle_vblank(dev, pipe); 174 175 spin_lock_irqsave(&dev->event_lock, flags); 176 if (gma_crtc->page_flip_event) { 177 drm_crtc_send_vblank_event(crtc, 178 gma_crtc->page_flip_event); 179 gma_crtc->page_flip_event = NULL; 180 drm_crtc_vblank_put(crtc); 181 } 182 spin_unlock_irqrestore(&dev->event_lock, flags); 183 } 184 } 185 186 /* 187 * Display controller interrupt handler. 188 */ 189 static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat) 190 { 191 if (vdc_stat & _PSB_IRQ_ASLE) 192 psb_intel_opregion_asle_intr(dev); 193 194 if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG) 195 mid_pipe_event_handler(dev, 0); 196 197 if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG) 198 mid_pipe_event_handler(dev, 1); 199 } 200 201 /* 202 * SGX interrupt handler 203 */ 204 static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2) 205 { 206 struct drm_psb_private *dev_priv = dev->dev_private; 207 u32 val, addr; 208 209 if (stat_1 & _PSB_CE_TWOD_COMPLETE) 210 val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS); 211 212 if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) { 213 val = PSB_RSGX32(PSB_CR_BIF_INT_STAT); 214 addr = PSB_RSGX32(PSB_CR_BIF_FAULT); 215 if (val) { 216 if (val & _PSB_CBI_STAT_PF_N_RW) 217 DRM_ERROR("SGX MMU page fault:"); 218 else 219 DRM_ERROR("SGX MMU read / write protection fault:"); 220 221 if (val & _PSB_CBI_STAT_FAULT_CACHE) 222 DRM_ERROR("\tCache requestor"); 223 if (val & _PSB_CBI_STAT_FAULT_TA) 224 DRM_ERROR("\tTA requestor"); 225 if (val & _PSB_CBI_STAT_FAULT_VDM) 226 DRM_ERROR("\tVDM requestor"); 227 if (val & _PSB_CBI_STAT_FAULT_2D) 228 DRM_ERROR("\t2D requestor"); 229 if (val & _PSB_CBI_STAT_FAULT_PBE) 230 DRM_ERROR("\tPBE requestor"); 231 if (val & _PSB_CBI_STAT_FAULT_TSP) 232 DRM_ERROR("\tTSP requestor"); 233 if (val & _PSB_CBI_STAT_FAULT_ISP) 234 DRM_ERROR("\tISP requestor"); 235 if (val & _PSB_CBI_STAT_FAULT_USSEPDS) 236 DRM_ERROR("\tUSSEPDS requestor"); 237 if (val & _PSB_CBI_STAT_FAULT_HOST) 238 DRM_ERROR("\tHost requestor"); 239 240 DRM_ERROR("\tMMU failing address is 0x%08x.\n", 241 (unsigned int)addr); 242 } 243 } 244 245 /* Clear bits */ 246 PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR); 247 PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2); 248 PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2); 249 } 250 251 irqreturn_t psb_irq_handler(int irq, void *arg) 252 { 253 struct drm_device *dev = arg; 254 struct drm_psb_private *dev_priv = dev->dev_private; 255 uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0; 256 u32 sgx_stat_1, sgx_stat_2; 257 int handled = 0; 258 259 spin_lock(&dev_priv->irqmask_lock); 260 261 vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R); 262 263 if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE)) 264 dsp_int = 1; 265 266 /* FIXME: Handle Medfield 267 if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG) 268 dsp_int = 1; 269 */ 270 271 if (vdc_stat & _PSB_IRQ_SGX_FLAG) 272 sgx_int = 1; 273 if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC) 274 hotplug_int = 1; 275 276 vdc_stat &= dev_priv->vdc_irq_mask; 277 spin_unlock(&dev_priv->irqmask_lock); 278 279 if (dsp_int && gma_power_is_on(dev)) { 280 psb_vdc_interrupt(dev, vdc_stat); 281 handled = 1; 282 } 283 284 if (sgx_int) { 285 sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS); 286 sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2); 287 psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2); 288 handled = 1; 289 } 290 291 /* Note: this bit has other meanings on some devices, so we will 292 need to address that later if it ever matters */ 293 if (hotplug_int && dev_priv->ops->hotplug) { 294 handled = dev_priv->ops->hotplug(dev); 295 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); 296 } 297 298 PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R); 299 (void) PSB_RVDC32(PSB_INT_IDENTITY_R); 300 rmb(); 301 302 if (!handled) 303 return IRQ_NONE; 304 305 return IRQ_HANDLED; 306 } 307 308 void psb_irq_preinstall(struct drm_device *dev) 309 { 310 struct drm_psb_private *dev_priv = 311 (struct drm_psb_private *) dev->dev_private; 312 unsigned long irqflags; 313 314 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 315 316 if (gma_power_is_on(dev)) { 317 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); 318 PSB_WVDC32(0x00000000, PSB_INT_MASK_R); 319 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R); 320 PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE); 321 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); 322 } 323 if (dev->vblank[0].enabled) 324 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG; 325 if (dev->vblank[1].enabled) 326 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG; 327 328 /* FIXME: Handle Medfield irq mask 329 if (dev->vblank[1].enabled) 330 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG; 331 if (dev->vblank[2].enabled) 332 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG; 333 */ 334 335 /* Revisit this area - want per device masks ? */ 336 if (dev_priv->ops->hotplug) 337 dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC; 338 dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG; 339 340 /* This register is safe even if display island is off */ 341 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 342 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 343 } 344 345 int psb_irq_postinstall(struct drm_device *dev) 346 { 347 struct drm_psb_private *dev_priv = dev->dev_private; 348 unsigned long irqflags; 349 unsigned int i; 350 351 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 352 353 /* Enable 2D and MMU fault interrupts */ 354 PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2); 355 PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE); 356 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */ 357 358 /* This register is safe even if display island is off */ 359 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 360 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); 361 362 for (i = 0; i < dev->num_crtcs; ++i) { 363 if (dev->vblank[i].enabled) 364 psb_enable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE); 365 else 366 psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE); 367 } 368 369 if (dev_priv->ops->hotplug_enable) 370 dev_priv->ops->hotplug_enable(dev, true); 371 372 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 373 return 0; 374 } 375 376 void psb_irq_uninstall(struct drm_device *dev) 377 { 378 struct drm_psb_private *dev_priv = dev->dev_private; 379 unsigned long irqflags; 380 unsigned int i; 381 382 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 383 384 if (dev_priv->ops->hotplug_enable) 385 dev_priv->ops->hotplug_enable(dev, false); 386 387 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); 388 389 for (i = 0; i < dev->num_crtcs; ++i) { 390 if (dev->vblank[i].enabled) 391 psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE); 392 } 393 394 dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG | 395 _PSB_IRQ_MSVDX_FLAG | 396 _LNC_IRQ_TOPAZ_FLAG; 397 398 /* These two registers are safe even if display island is off */ 399 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 400 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 401 402 wmb(); 403 404 /* This register is safe even if display island is off */ 405 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R); 406 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 407 } 408 409 void psb_irq_turn_on_dpst(struct drm_device *dev) 410 { 411 struct drm_psb_private *dev_priv = 412 (struct drm_psb_private *) dev->dev_private; 413 u32 hist_reg; 414 u32 pwm_reg; 415 416 if (gma_power_begin(dev, false)) { 417 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL); 418 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL); 419 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL); 420 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL); 421 422 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC); 423 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); 424 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE 425 | PWM_PHASEIN_INT_ENABLE, 426 PWM_CONTROL_LOGIC); 427 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); 428 429 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE); 430 431 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL); 432 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR, 433 HISTOGRAM_INT_CONTROL); 434 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); 435 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE, 436 PWM_CONTROL_LOGIC); 437 438 gma_power_end(dev); 439 } 440 } 441 442 int psb_irq_enable_dpst(struct drm_device *dev) 443 { 444 struct drm_psb_private *dev_priv = 445 (struct drm_psb_private *) dev->dev_private; 446 unsigned long irqflags; 447 448 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 449 450 /* enable DPST */ 451 mid_enable_pipe_event(dev_priv, 0); 452 psb_irq_turn_on_dpst(dev); 453 454 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 455 return 0; 456 } 457 458 void psb_irq_turn_off_dpst(struct drm_device *dev) 459 { 460 struct drm_psb_private *dev_priv = 461 (struct drm_psb_private *) dev->dev_private; 462 u32 pwm_reg; 463 464 if (gma_power_begin(dev, false)) { 465 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL); 466 PSB_RVDC32(HISTOGRAM_INT_CONTROL); 467 468 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE); 469 470 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); 471 PSB_WVDC32(pwm_reg & ~PWM_PHASEIN_INT_ENABLE, 472 PWM_CONTROL_LOGIC); 473 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); 474 475 gma_power_end(dev); 476 } 477 } 478 479 int psb_irq_disable_dpst(struct drm_device *dev) 480 { 481 struct drm_psb_private *dev_priv = 482 (struct drm_psb_private *) dev->dev_private; 483 unsigned long irqflags; 484 485 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 486 487 mid_disable_pipe_event(dev_priv, 0); 488 psb_irq_turn_off_dpst(dev); 489 490 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 491 492 return 0; 493 } 494 495 /* 496 * It is used to enable VBLANK interrupt 497 */ 498 int psb_enable_vblank(struct drm_crtc *crtc) 499 { 500 struct drm_device *dev = crtc->dev; 501 unsigned int pipe = crtc->index; 502 struct drm_psb_private *dev_priv = dev->dev_private; 503 unsigned long irqflags; 504 uint32_t reg_val = 0; 505 uint32_t pipeconf_reg = mid_pipeconf(pipe); 506 507 /* Medfield is different - we should perhaps extract out vblank 508 and blacklight etc ops */ 509 if (IS_MFLD(dev)) 510 return mdfld_enable_te(dev, pipe); 511 512 if (gma_power_begin(dev, false)) { 513 reg_val = REG_READ(pipeconf_reg); 514 gma_power_end(dev); 515 } 516 517 if (!(reg_val & PIPEACONF_ENABLE)) 518 return -EINVAL; 519 520 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 521 522 if (pipe == 0) 523 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG; 524 else if (pipe == 1) 525 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG; 526 527 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 528 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 529 psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE); 530 531 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 532 533 return 0; 534 } 535 536 /* 537 * It is used to disable VBLANK interrupt 538 */ 539 void psb_disable_vblank(struct drm_crtc *crtc) 540 { 541 struct drm_device *dev = crtc->dev; 542 unsigned int pipe = crtc->index; 543 struct drm_psb_private *dev_priv = dev->dev_private; 544 unsigned long irqflags; 545 546 if (IS_MFLD(dev)) 547 mdfld_disable_te(dev, pipe); 548 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 549 550 if (pipe == 0) 551 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG; 552 else if (pipe == 1) 553 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG; 554 555 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 556 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 557 psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE); 558 559 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 560 } 561 562 /* 563 * It is used to enable TE interrupt 564 */ 565 int mdfld_enable_te(struct drm_device *dev, int pipe) 566 { 567 struct drm_psb_private *dev_priv = 568 (struct drm_psb_private *) dev->dev_private; 569 unsigned long irqflags; 570 uint32_t reg_val = 0; 571 uint32_t pipeconf_reg = mid_pipeconf(pipe); 572 573 if (gma_power_begin(dev, false)) { 574 reg_val = REG_READ(pipeconf_reg); 575 gma_power_end(dev); 576 } 577 578 if (!(reg_val & PIPEACONF_ENABLE)) 579 return -EINVAL; 580 581 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 582 583 mid_enable_pipe_event(dev_priv, pipe); 584 psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE); 585 586 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 587 588 return 0; 589 } 590 591 /* 592 * It is used to disable TE interrupt 593 */ 594 void mdfld_disable_te(struct drm_device *dev, int pipe) 595 { 596 struct drm_psb_private *dev_priv = 597 (struct drm_psb_private *) dev->dev_private; 598 unsigned long irqflags; 599 600 if (!dev_priv->dsr_enable) 601 return; 602 603 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 604 605 mid_disable_pipe_event(dev_priv, pipe); 606 psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE); 607 608 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 609 } 610 611 /* Called from drm generic code, passed a 'crtc', which 612 * we use as a pipe index 613 */ 614 u32 psb_get_vblank_counter(struct drm_crtc *crtc) 615 { 616 struct drm_device *dev = crtc->dev; 617 unsigned int pipe = crtc->index; 618 uint32_t high_frame = PIPEAFRAMEHIGH; 619 uint32_t low_frame = PIPEAFRAMEPIXEL; 620 uint32_t pipeconf_reg = PIPEACONF; 621 uint32_t reg_val = 0; 622 uint32_t high1 = 0, high2 = 0, low = 0, count = 0; 623 624 switch (pipe) { 625 case 0: 626 break; 627 case 1: 628 high_frame = PIPEBFRAMEHIGH; 629 low_frame = PIPEBFRAMEPIXEL; 630 pipeconf_reg = PIPEBCONF; 631 break; 632 case 2: 633 high_frame = PIPECFRAMEHIGH; 634 low_frame = PIPECFRAMEPIXEL; 635 pipeconf_reg = PIPECCONF; 636 break; 637 default: 638 dev_err(dev->dev, "%s, invalid pipe.\n", __func__); 639 return 0; 640 } 641 642 if (!gma_power_begin(dev, false)) 643 return 0; 644 645 reg_val = REG_READ(pipeconf_reg); 646 647 if (!(reg_val & PIPEACONF_ENABLE)) { 648 dev_err(dev->dev, "trying to get vblank count for disabled pipe %u\n", 649 pipe); 650 goto psb_get_vblank_counter_exit; 651 } 652 653 /* 654 * High & low register fields aren't synchronized, so make sure 655 * we get a low value that's stable across two reads of the high 656 * register. 657 */ 658 do { 659 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> 660 PIPE_FRAME_HIGH_SHIFT); 661 low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> 662 PIPE_FRAME_LOW_SHIFT); 663 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> 664 PIPE_FRAME_HIGH_SHIFT); 665 } while (high1 != high2); 666 667 count = (high1 << 8) | low; 668 669 psb_get_vblank_counter_exit: 670 671 gma_power_end(dev); 672 673 return count; 674 } 675 676