1 // SPDX-License-Identifier: GPL-2.0-only 2 /************************************************************************** 3 * Copyright (c) 2007, Intel Corporation. 4 * All Rights Reserved. 5 * 6 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 7 * develop this driver. 8 * 9 **************************************************************************/ 10 11 #include <drm/drm_drv.h> 12 #include <drm/drm_vblank.h> 13 14 #include "power.h" 15 #include "psb_drv.h" 16 #include "psb_intel_reg.h" 17 #include "psb_irq.h" 18 #include "psb_reg.h" 19 20 /* 21 * inline functions 22 */ 23 24 static inline u32 25 psb_pipestat(int pipe) 26 { 27 if (pipe == 0) 28 return PIPEASTAT; 29 if (pipe == 1) 30 return PIPEBSTAT; 31 if (pipe == 2) 32 return PIPECSTAT; 33 BUG(); 34 } 35 36 static inline u32 37 mid_pipe_event(int pipe) 38 { 39 if (pipe == 0) 40 return _PSB_PIPEA_EVENT_FLAG; 41 if (pipe == 1) 42 return _MDFLD_PIPEB_EVENT_FLAG; 43 if (pipe == 2) 44 return _MDFLD_PIPEC_EVENT_FLAG; 45 BUG(); 46 } 47 48 static inline u32 49 mid_pipe_vsync(int pipe) 50 { 51 if (pipe == 0) 52 return _PSB_VSYNC_PIPEA_FLAG; 53 if (pipe == 1) 54 return _PSB_VSYNC_PIPEB_FLAG; 55 if (pipe == 2) 56 return _MDFLD_PIPEC_VBLANK_FLAG; 57 BUG(); 58 } 59 60 static inline u32 61 mid_pipeconf(int pipe) 62 { 63 if (pipe == 0) 64 return PIPEACONF; 65 if (pipe == 1) 66 return PIPEBCONF; 67 if (pipe == 2) 68 return PIPECCONF; 69 BUG(); 70 } 71 72 void 73 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) 74 { 75 if ((dev_priv->pipestat[pipe] & mask) != mask) { 76 u32 reg = psb_pipestat(pipe); 77 dev_priv->pipestat[pipe] |= mask; 78 /* Enable the interrupt, clear any pending status */ 79 if (gma_power_begin(dev_priv->dev, false)) { 80 u32 writeVal = PSB_RVDC32(reg); 81 writeVal |= (mask | (mask >> 16)); 82 PSB_WVDC32(writeVal, reg); 83 (void) PSB_RVDC32(reg); 84 gma_power_end(dev_priv->dev); 85 } 86 } 87 } 88 89 void 90 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) 91 { 92 if ((dev_priv->pipestat[pipe] & mask) != 0) { 93 u32 reg = psb_pipestat(pipe); 94 dev_priv->pipestat[pipe] &= ~mask; 95 if (gma_power_begin(dev_priv->dev, false)) { 96 u32 writeVal = PSB_RVDC32(reg); 97 writeVal &= ~mask; 98 PSB_WVDC32(writeVal, reg); 99 (void) PSB_RVDC32(reg); 100 gma_power_end(dev_priv->dev); 101 } 102 } 103 } 104 105 /* 106 * Display controller interrupt handler for pipe event. 107 */ 108 static void mid_pipe_event_handler(struct drm_device *dev, int pipe) 109 { 110 struct drm_psb_private *dev_priv = 111 (struct drm_psb_private *) dev->dev_private; 112 113 uint32_t pipe_stat_val = 0; 114 uint32_t pipe_stat_reg = psb_pipestat(pipe); 115 uint32_t pipe_enable = dev_priv->pipestat[pipe]; 116 uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16; 117 uint32_t pipe_clear; 118 uint32_t i = 0; 119 120 spin_lock(&dev_priv->irqmask_lock); 121 122 pipe_stat_val = PSB_RVDC32(pipe_stat_reg); 123 pipe_stat_val &= pipe_enable | pipe_status; 124 pipe_stat_val &= pipe_stat_val >> 16; 125 126 spin_unlock(&dev_priv->irqmask_lock); 127 128 /* Clear the 2nd level interrupt status bits 129 * Sometimes the bits are very sticky so we repeat until they unstick */ 130 for (i = 0; i < 0xffff; i++) { 131 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg); 132 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status; 133 134 if (pipe_clear == 0) 135 break; 136 } 137 138 if (pipe_clear) 139 dev_err(dev->dev, 140 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n", 141 __func__, pipe, PSB_RVDC32(pipe_stat_reg)); 142 143 if (pipe_stat_val & PIPE_VBLANK_STATUS) { 144 struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe); 145 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 146 unsigned long flags; 147 148 drm_handle_vblank(dev, pipe); 149 150 spin_lock_irqsave(&dev->event_lock, flags); 151 if (gma_crtc->page_flip_event) { 152 drm_crtc_send_vblank_event(crtc, 153 gma_crtc->page_flip_event); 154 gma_crtc->page_flip_event = NULL; 155 drm_crtc_vblank_put(crtc); 156 } 157 spin_unlock_irqrestore(&dev->event_lock, flags); 158 } 159 } 160 161 /* 162 * Display controller interrupt handler. 163 */ 164 static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat) 165 { 166 if (vdc_stat & _PSB_IRQ_ASLE) 167 psb_intel_opregion_asle_intr(dev); 168 169 if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG) 170 mid_pipe_event_handler(dev, 0); 171 172 if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG) 173 mid_pipe_event_handler(dev, 1); 174 } 175 176 /* 177 * SGX interrupt handler 178 */ 179 static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2) 180 { 181 struct drm_psb_private *dev_priv = dev->dev_private; 182 u32 val, addr; 183 184 if (stat_1 & _PSB_CE_TWOD_COMPLETE) 185 val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS); 186 187 if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) { 188 val = PSB_RSGX32(PSB_CR_BIF_INT_STAT); 189 addr = PSB_RSGX32(PSB_CR_BIF_FAULT); 190 if (val) { 191 if (val & _PSB_CBI_STAT_PF_N_RW) 192 DRM_ERROR("SGX MMU page fault:"); 193 else 194 DRM_ERROR("SGX MMU read / write protection fault:"); 195 196 if (val & _PSB_CBI_STAT_FAULT_CACHE) 197 DRM_ERROR("\tCache requestor"); 198 if (val & _PSB_CBI_STAT_FAULT_TA) 199 DRM_ERROR("\tTA requestor"); 200 if (val & _PSB_CBI_STAT_FAULT_VDM) 201 DRM_ERROR("\tVDM requestor"); 202 if (val & _PSB_CBI_STAT_FAULT_2D) 203 DRM_ERROR("\t2D requestor"); 204 if (val & _PSB_CBI_STAT_FAULT_PBE) 205 DRM_ERROR("\tPBE requestor"); 206 if (val & _PSB_CBI_STAT_FAULT_TSP) 207 DRM_ERROR("\tTSP requestor"); 208 if (val & _PSB_CBI_STAT_FAULT_ISP) 209 DRM_ERROR("\tISP requestor"); 210 if (val & _PSB_CBI_STAT_FAULT_USSEPDS) 211 DRM_ERROR("\tUSSEPDS requestor"); 212 if (val & _PSB_CBI_STAT_FAULT_HOST) 213 DRM_ERROR("\tHost requestor"); 214 215 DRM_ERROR("\tMMU failing address is 0x%08x.\n", 216 (unsigned int)addr); 217 } 218 } 219 220 /* Clear bits */ 221 PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR); 222 PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2); 223 PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2); 224 } 225 226 static irqreturn_t psb_irq_handler(int irq, void *arg) 227 { 228 struct drm_device *dev = arg; 229 struct drm_psb_private *dev_priv = dev->dev_private; 230 uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0; 231 u32 sgx_stat_1, sgx_stat_2; 232 int handled = 0; 233 234 spin_lock(&dev_priv->irqmask_lock); 235 236 vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R); 237 238 if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE)) 239 dsp_int = 1; 240 241 if (vdc_stat & _PSB_IRQ_SGX_FLAG) 242 sgx_int = 1; 243 if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC) 244 hotplug_int = 1; 245 246 vdc_stat &= dev_priv->vdc_irq_mask; 247 spin_unlock(&dev_priv->irqmask_lock); 248 249 if (dsp_int && gma_power_is_on(dev)) { 250 psb_vdc_interrupt(dev, vdc_stat); 251 handled = 1; 252 } 253 254 if (sgx_int) { 255 sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS); 256 sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2); 257 psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2); 258 handled = 1; 259 } 260 261 /* Note: this bit has other meanings on some devices, so we will 262 need to address that later if it ever matters */ 263 if (hotplug_int && dev_priv->ops->hotplug) { 264 handled = dev_priv->ops->hotplug(dev); 265 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); 266 } 267 268 PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R); 269 (void) PSB_RVDC32(PSB_INT_IDENTITY_R); 270 rmb(); 271 272 if (!handled) 273 return IRQ_NONE; 274 275 return IRQ_HANDLED; 276 } 277 278 void psb_irq_preinstall(struct drm_device *dev) 279 { 280 struct drm_psb_private *dev_priv = 281 (struct drm_psb_private *) dev->dev_private; 282 unsigned long irqflags; 283 284 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 285 286 if (gma_power_is_on(dev)) { 287 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); 288 PSB_WVDC32(0x00000000, PSB_INT_MASK_R); 289 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R); 290 PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE); 291 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); 292 } 293 if (dev->vblank[0].enabled) 294 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG; 295 if (dev->vblank[1].enabled) 296 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG; 297 298 /* Revisit this area - want per device masks ? */ 299 if (dev_priv->ops->hotplug) 300 dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC; 301 dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG; 302 303 /* This register is safe even if display island is off */ 304 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 305 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 306 } 307 308 void psb_irq_postinstall(struct drm_device *dev) 309 { 310 struct drm_psb_private *dev_priv = dev->dev_private; 311 unsigned long irqflags; 312 unsigned int i; 313 314 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 315 316 /* Enable 2D and MMU fault interrupts */ 317 PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2); 318 PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE); 319 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */ 320 321 /* This register is safe even if display island is off */ 322 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 323 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); 324 325 for (i = 0; i < dev->num_crtcs; ++i) { 326 if (dev->vblank[i].enabled) 327 psb_enable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE); 328 else 329 psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE); 330 } 331 332 if (dev_priv->ops->hotplug_enable) 333 dev_priv->ops->hotplug_enable(dev, true); 334 335 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 336 } 337 338 int psb_irq_install(struct drm_device *dev, unsigned int irq) 339 { 340 int ret; 341 342 if (irq == IRQ_NOTCONNECTED) 343 return -ENOTCONN; 344 345 psb_irq_preinstall(dev); 346 347 /* PCI devices require shared interrupts. */ 348 ret = request_irq(irq, psb_irq_handler, IRQF_SHARED, dev->driver->name, dev); 349 if (ret) 350 return ret; 351 352 psb_irq_postinstall(dev); 353 354 return 0; 355 } 356 357 void psb_irq_uninstall(struct drm_device *dev) 358 { 359 struct drm_psb_private *dev_priv = dev->dev_private; 360 struct pci_dev *pdev = to_pci_dev(dev->dev); 361 unsigned long irqflags; 362 unsigned int i; 363 364 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 365 366 if (dev_priv->ops->hotplug_enable) 367 dev_priv->ops->hotplug_enable(dev, false); 368 369 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); 370 371 for (i = 0; i < dev->num_crtcs; ++i) { 372 if (dev->vblank[i].enabled) 373 psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE); 374 } 375 376 dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG | 377 _PSB_IRQ_MSVDX_FLAG | 378 _LNC_IRQ_TOPAZ_FLAG; 379 380 /* These two registers are safe even if display island is off */ 381 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 382 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 383 384 wmb(); 385 386 /* This register is safe even if display island is off */ 387 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R); 388 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 389 390 free_irq(pdev->irq, dev); 391 } 392 393 /* 394 * It is used to enable VBLANK interrupt 395 */ 396 int psb_enable_vblank(struct drm_crtc *crtc) 397 { 398 struct drm_device *dev = crtc->dev; 399 unsigned int pipe = crtc->index; 400 struct drm_psb_private *dev_priv = dev->dev_private; 401 unsigned long irqflags; 402 uint32_t reg_val = 0; 403 uint32_t pipeconf_reg = mid_pipeconf(pipe); 404 405 if (gma_power_begin(dev, false)) { 406 reg_val = REG_READ(pipeconf_reg); 407 gma_power_end(dev); 408 } 409 410 if (!(reg_val & PIPEACONF_ENABLE)) 411 return -EINVAL; 412 413 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 414 415 if (pipe == 0) 416 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG; 417 else if (pipe == 1) 418 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG; 419 420 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 421 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 422 psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE); 423 424 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 425 426 return 0; 427 } 428 429 /* 430 * It is used to disable VBLANK interrupt 431 */ 432 void psb_disable_vblank(struct drm_crtc *crtc) 433 { 434 struct drm_device *dev = crtc->dev; 435 unsigned int pipe = crtc->index; 436 struct drm_psb_private *dev_priv = dev->dev_private; 437 unsigned long irqflags; 438 439 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 440 441 if (pipe == 0) 442 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG; 443 else if (pipe == 1) 444 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG; 445 446 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 447 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 448 psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE); 449 450 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 451 } 452 453 /* Called from drm generic code, passed a 'crtc', which 454 * we use as a pipe index 455 */ 456 u32 psb_get_vblank_counter(struct drm_crtc *crtc) 457 { 458 struct drm_device *dev = crtc->dev; 459 unsigned int pipe = crtc->index; 460 uint32_t high_frame = PIPEAFRAMEHIGH; 461 uint32_t low_frame = PIPEAFRAMEPIXEL; 462 uint32_t pipeconf_reg = PIPEACONF; 463 uint32_t reg_val = 0; 464 uint32_t high1 = 0, high2 = 0, low = 0, count = 0; 465 466 switch (pipe) { 467 case 0: 468 break; 469 case 1: 470 high_frame = PIPEBFRAMEHIGH; 471 low_frame = PIPEBFRAMEPIXEL; 472 pipeconf_reg = PIPEBCONF; 473 break; 474 case 2: 475 high_frame = PIPECFRAMEHIGH; 476 low_frame = PIPECFRAMEPIXEL; 477 pipeconf_reg = PIPECCONF; 478 break; 479 default: 480 dev_err(dev->dev, "%s, invalid pipe.\n", __func__); 481 return 0; 482 } 483 484 if (!gma_power_begin(dev, false)) 485 return 0; 486 487 reg_val = REG_READ(pipeconf_reg); 488 489 if (!(reg_val & PIPEACONF_ENABLE)) { 490 dev_err(dev->dev, "trying to get vblank count for disabled pipe %u\n", 491 pipe); 492 goto psb_get_vblank_counter_exit; 493 } 494 495 /* 496 * High & low register fields aren't synchronized, so make sure 497 * we get a low value that's stable across two reads of the high 498 * register. 499 */ 500 do { 501 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> 502 PIPE_FRAME_HIGH_SHIFT); 503 low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> 504 PIPE_FRAME_LOW_SHIFT); 505 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> 506 PIPE_FRAME_HIGH_SHIFT); 507 } while (high1 != high2); 508 509 count = (high1 << 8) | low; 510 511 psb_get_vblank_counter_exit: 512 513 gma_power_end(dev); 514 515 return count; 516 } 517 518