1 // SPDX-License-Identifier: GPL-2.0-only 2 /************************************************************************** 3 * Copyright (c) 2007, Intel Corporation. 4 * All Rights Reserved. 5 * 6 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 7 * develop this driver. 8 * 9 **************************************************************************/ 10 11 #include <drm/drmP.h> 12 #include "psb_drv.h" 13 #include "psb_reg.h" 14 #include "psb_intel_reg.h" 15 #include "power.h" 16 #include "psb_irq.h" 17 #include "mdfld_output.h" 18 19 /* 20 * inline functions 21 */ 22 23 static inline u32 24 psb_pipestat(int pipe) 25 { 26 if (pipe == 0) 27 return PIPEASTAT; 28 if (pipe == 1) 29 return PIPEBSTAT; 30 if (pipe == 2) 31 return PIPECSTAT; 32 BUG(); 33 } 34 35 static inline u32 36 mid_pipe_event(int pipe) 37 { 38 if (pipe == 0) 39 return _PSB_PIPEA_EVENT_FLAG; 40 if (pipe == 1) 41 return _MDFLD_PIPEB_EVENT_FLAG; 42 if (pipe == 2) 43 return _MDFLD_PIPEC_EVENT_FLAG; 44 BUG(); 45 } 46 47 static inline u32 48 mid_pipe_vsync(int pipe) 49 { 50 if (pipe == 0) 51 return _PSB_VSYNC_PIPEA_FLAG; 52 if (pipe == 1) 53 return _PSB_VSYNC_PIPEB_FLAG; 54 if (pipe == 2) 55 return _MDFLD_PIPEC_VBLANK_FLAG; 56 BUG(); 57 } 58 59 static inline u32 60 mid_pipeconf(int pipe) 61 { 62 if (pipe == 0) 63 return PIPEACONF; 64 if (pipe == 1) 65 return PIPEBCONF; 66 if (pipe == 2) 67 return PIPECCONF; 68 BUG(); 69 } 70 71 void 72 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) 73 { 74 if ((dev_priv->pipestat[pipe] & mask) != mask) { 75 u32 reg = psb_pipestat(pipe); 76 dev_priv->pipestat[pipe] |= mask; 77 /* Enable the interrupt, clear any pending status */ 78 if (gma_power_begin(dev_priv->dev, false)) { 79 u32 writeVal = PSB_RVDC32(reg); 80 writeVal |= (mask | (mask >> 16)); 81 PSB_WVDC32(writeVal, reg); 82 (void) PSB_RVDC32(reg); 83 gma_power_end(dev_priv->dev); 84 } 85 } 86 } 87 88 void 89 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) 90 { 91 if ((dev_priv->pipestat[pipe] & mask) != 0) { 92 u32 reg = psb_pipestat(pipe); 93 dev_priv->pipestat[pipe] &= ~mask; 94 if (gma_power_begin(dev_priv->dev, false)) { 95 u32 writeVal = PSB_RVDC32(reg); 96 writeVal &= ~mask; 97 PSB_WVDC32(writeVal, reg); 98 (void) PSB_RVDC32(reg); 99 gma_power_end(dev_priv->dev); 100 } 101 } 102 } 103 104 static void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe) 105 { 106 if (gma_power_begin(dev_priv->dev, false)) { 107 u32 pipe_event = mid_pipe_event(pipe); 108 dev_priv->vdc_irq_mask |= pipe_event; 109 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 110 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 111 gma_power_end(dev_priv->dev); 112 } 113 } 114 115 static void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe) 116 { 117 if (dev_priv->pipestat[pipe] == 0) { 118 if (gma_power_begin(dev_priv->dev, false)) { 119 u32 pipe_event = mid_pipe_event(pipe); 120 dev_priv->vdc_irq_mask &= ~pipe_event; 121 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 122 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 123 gma_power_end(dev_priv->dev); 124 } 125 } 126 } 127 128 /** 129 * Display controller interrupt handler for pipe event. 130 * 131 */ 132 static void mid_pipe_event_handler(struct drm_device *dev, int pipe) 133 { 134 struct drm_psb_private *dev_priv = 135 (struct drm_psb_private *) dev->dev_private; 136 137 uint32_t pipe_stat_val = 0; 138 uint32_t pipe_stat_reg = psb_pipestat(pipe); 139 uint32_t pipe_enable = dev_priv->pipestat[pipe]; 140 uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16; 141 uint32_t pipe_clear; 142 uint32_t i = 0; 143 144 spin_lock(&dev_priv->irqmask_lock); 145 146 pipe_stat_val = PSB_RVDC32(pipe_stat_reg); 147 pipe_stat_val &= pipe_enable | pipe_status; 148 pipe_stat_val &= pipe_stat_val >> 16; 149 150 spin_unlock(&dev_priv->irqmask_lock); 151 152 /* Clear the 2nd level interrupt status bits 153 * Sometimes the bits are very sticky so we repeat until they unstick */ 154 for (i = 0; i < 0xffff; i++) { 155 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg); 156 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status; 157 158 if (pipe_clear == 0) 159 break; 160 } 161 162 if (pipe_clear) 163 dev_err(dev->dev, 164 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n", 165 __func__, pipe, PSB_RVDC32(pipe_stat_reg)); 166 167 if (pipe_stat_val & PIPE_VBLANK_STATUS) 168 drm_handle_vblank(dev, pipe); 169 170 if (pipe_stat_val & PIPE_TE_STATUS) 171 drm_handle_vblank(dev, pipe); 172 } 173 174 /* 175 * Display controller interrupt handler. 176 */ 177 static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat) 178 { 179 if (vdc_stat & _PSB_IRQ_ASLE) 180 psb_intel_opregion_asle_intr(dev); 181 182 if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG) 183 mid_pipe_event_handler(dev, 0); 184 185 if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG) 186 mid_pipe_event_handler(dev, 1); 187 } 188 189 /* 190 * SGX interrupt handler 191 */ 192 static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2) 193 { 194 struct drm_psb_private *dev_priv = dev->dev_private; 195 u32 val, addr; 196 int error = false; 197 198 if (stat_1 & _PSB_CE_TWOD_COMPLETE) 199 val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS); 200 201 if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) { 202 val = PSB_RSGX32(PSB_CR_BIF_INT_STAT); 203 addr = PSB_RSGX32(PSB_CR_BIF_FAULT); 204 if (val) { 205 if (val & _PSB_CBI_STAT_PF_N_RW) 206 DRM_ERROR("SGX MMU page fault:"); 207 else 208 DRM_ERROR("SGX MMU read / write protection fault:"); 209 210 if (val & _PSB_CBI_STAT_FAULT_CACHE) 211 DRM_ERROR("\tCache requestor"); 212 if (val & _PSB_CBI_STAT_FAULT_TA) 213 DRM_ERROR("\tTA requestor"); 214 if (val & _PSB_CBI_STAT_FAULT_VDM) 215 DRM_ERROR("\tVDM requestor"); 216 if (val & _PSB_CBI_STAT_FAULT_2D) 217 DRM_ERROR("\t2D requestor"); 218 if (val & _PSB_CBI_STAT_FAULT_PBE) 219 DRM_ERROR("\tPBE requestor"); 220 if (val & _PSB_CBI_STAT_FAULT_TSP) 221 DRM_ERROR("\tTSP requestor"); 222 if (val & _PSB_CBI_STAT_FAULT_ISP) 223 DRM_ERROR("\tISP requestor"); 224 if (val & _PSB_CBI_STAT_FAULT_USSEPDS) 225 DRM_ERROR("\tUSSEPDS requestor"); 226 if (val & _PSB_CBI_STAT_FAULT_HOST) 227 DRM_ERROR("\tHost requestor"); 228 229 DRM_ERROR("\tMMU failing address is 0x%08x.\n", 230 (unsigned int)addr); 231 error = true; 232 } 233 } 234 235 /* Clear bits */ 236 PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR); 237 PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2); 238 PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2); 239 } 240 241 irqreturn_t psb_irq_handler(int irq, void *arg) 242 { 243 struct drm_device *dev = arg; 244 struct drm_psb_private *dev_priv = dev->dev_private; 245 uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0; 246 u32 sgx_stat_1, sgx_stat_2; 247 int handled = 0; 248 249 spin_lock(&dev_priv->irqmask_lock); 250 251 vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R); 252 253 if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE)) 254 dsp_int = 1; 255 256 /* FIXME: Handle Medfield 257 if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG) 258 dsp_int = 1; 259 */ 260 261 if (vdc_stat & _PSB_IRQ_SGX_FLAG) 262 sgx_int = 1; 263 if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC) 264 hotplug_int = 1; 265 266 vdc_stat &= dev_priv->vdc_irq_mask; 267 spin_unlock(&dev_priv->irqmask_lock); 268 269 if (dsp_int && gma_power_is_on(dev)) { 270 psb_vdc_interrupt(dev, vdc_stat); 271 handled = 1; 272 } 273 274 if (sgx_int) { 275 sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS); 276 sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2); 277 psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2); 278 handled = 1; 279 } 280 281 /* Note: this bit has other meanings on some devices, so we will 282 need to address that later if it ever matters */ 283 if (hotplug_int && dev_priv->ops->hotplug) { 284 handled = dev_priv->ops->hotplug(dev); 285 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); 286 } 287 288 PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R); 289 (void) PSB_RVDC32(PSB_INT_IDENTITY_R); 290 rmb(); 291 292 if (!handled) 293 return IRQ_NONE; 294 295 return IRQ_HANDLED; 296 } 297 298 void psb_irq_preinstall(struct drm_device *dev) 299 { 300 struct drm_psb_private *dev_priv = 301 (struct drm_psb_private *) dev->dev_private; 302 unsigned long irqflags; 303 304 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 305 306 if (gma_power_is_on(dev)) { 307 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); 308 PSB_WVDC32(0x00000000, PSB_INT_MASK_R); 309 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R); 310 PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE); 311 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); 312 } 313 if (dev->vblank[0].enabled) 314 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG; 315 if (dev->vblank[1].enabled) 316 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG; 317 318 /* FIXME: Handle Medfield irq mask 319 if (dev->vblank[1].enabled) 320 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG; 321 if (dev->vblank[2].enabled) 322 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG; 323 */ 324 325 /* Revisit this area - want per device masks ? */ 326 if (dev_priv->ops->hotplug) 327 dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC; 328 dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG; 329 330 /* This register is safe even if display island is off */ 331 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 332 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 333 } 334 335 int psb_irq_postinstall(struct drm_device *dev) 336 { 337 struct drm_psb_private *dev_priv = dev->dev_private; 338 unsigned long irqflags; 339 340 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 341 342 /* Enable 2D and MMU fault interrupts */ 343 PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2); 344 PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE); 345 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */ 346 347 /* This register is safe even if display island is off */ 348 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 349 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); 350 351 if (dev->vblank[0].enabled) 352 psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE); 353 else 354 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE); 355 356 if (dev->vblank[1].enabled) 357 psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE); 358 else 359 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE); 360 361 if (dev->vblank[2].enabled) 362 psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE); 363 else 364 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE); 365 366 if (dev_priv->ops->hotplug_enable) 367 dev_priv->ops->hotplug_enable(dev, true); 368 369 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 370 return 0; 371 } 372 373 void psb_irq_uninstall(struct drm_device *dev) 374 { 375 struct drm_psb_private *dev_priv = dev->dev_private; 376 unsigned long irqflags; 377 378 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 379 380 if (dev_priv->ops->hotplug_enable) 381 dev_priv->ops->hotplug_enable(dev, false); 382 383 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); 384 385 if (dev->vblank[0].enabled) 386 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE); 387 388 if (dev->vblank[1].enabled) 389 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE); 390 391 if (dev->vblank[2].enabled) 392 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE); 393 394 dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG | 395 _PSB_IRQ_MSVDX_FLAG | 396 _LNC_IRQ_TOPAZ_FLAG; 397 398 /* These two registers are safe even if display island is off */ 399 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 400 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 401 402 wmb(); 403 404 /* This register is safe even if display island is off */ 405 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R); 406 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 407 } 408 409 void psb_irq_turn_on_dpst(struct drm_device *dev) 410 { 411 struct drm_psb_private *dev_priv = 412 (struct drm_psb_private *) dev->dev_private; 413 u32 hist_reg; 414 u32 pwm_reg; 415 416 if (gma_power_begin(dev, false)) { 417 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL); 418 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL); 419 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL); 420 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL); 421 422 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC); 423 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); 424 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE 425 | PWM_PHASEIN_INT_ENABLE, 426 PWM_CONTROL_LOGIC); 427 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); 428 429 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE); 430 431 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL); 432 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR, 433 HISTOGRAM_INT_CONTROL); 434 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); 435 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE, 436 PWM_CONTROL_LOGIC); 437 438 gma_power_end(dev); 439 } 440 } 441 442 int psb_irq_enable_dpst(struct drm_device *dev) 443 { 444 struct drm_psb_private *dev_priv = 445 (struct drm_psb_private *) dev->dev_private; 446 unsigned long irqflags; 447 448 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 449 450 /* enable DPST */ 451 mid_enable_pipe_event(dev_priv, 0); 452 psb_irq_turn_on_dpst(dev); 453 454 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 455 return 0; 456 } 457 458 void psb_irq_turn_off_dpst(struct drm_device *dev) 459 { 460 struct drm_psb_private *dev_priv = 461 (struct drm_psb_private *) dev->dev_private; 462 u32 hist_reg; 463 u32 pwm_reg; 464 465 if (gma_power_begin(dev, false)) { 466 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL); 467 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL); 468 469 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE); 470 471 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); 472 PSB_WVDC32(pwm_reg & ~PWM_PHASEIN_INT_ENABLE, 473 PWM_CONTROL_LOGIC); 474 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); 475 476 gma_power_end(dev); 477 } 478 } 479 480 int psb_irq_disable_dpst(struct drm_device *dev) 481 { 482 struct drm_psb_private *dev_priv = 483 (struct drm_psb_private *) dev->dev_private; 484 unsigned long irqflags; 485 486 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 487 488 mid_disable_pipe_event(dev_priv, 0); 489 psb_irq_turn_off_dpst(dev); 490 491 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 492 493 return 0; 494 } 495 496 /* 497 * It is used to enable VBLANK interrupt 498 */ 499 int psb_enable_vblank(struct drm_device *dev, unsigned int pipe) 500 { 501 struct drm_psb_private *dev_priv = dev->dev_private; 502 unsigned long irqflags; 503 uint32_t reg_val = 0; 504 uint32_t pipeconf_reg = mid_pipeconf(pipe); 505 506 /* Medfield is different - we should perhaps extract out vblank 507 and blacklight etc ops */ 508 if (IS_MFLD(dev)) 509 return mdfld_enable_te(dev, pipe); 510 511 if (gma_power_begin(dev, false)) { 512 reg_val = REG_READ(pipeconf_reg); 513 gma_power_end(dev); 514 } 515 516 if (!(reg_val & PIPEACONF_ENABLE)) 517 return -EINVAL; 518 519 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 520 521 if (pipe == 0) 522 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG; 523 else if (pipe == 1) 524 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG; 525 526 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 527 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 528 psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE); 529 530 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 531 532 return 0; 533 } 534 535 /* 536 * It is used to disable VBLANK interrupt 537 */ 538 void psb_disable_vblank(struct drm_device *dev, unsigned int pipe) 539 { 540 struct drm_psb_private *dev_priv = dev->dev_private; 541 unsigned long irqflags; 542 543 if (IS_MFLD(dev)) 544 mdfld_disable_te(dev, pipe); 545 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 546 547 if (pipe == 0) 548 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG; 549 else if (pipe == 1) 550 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG; 551 552 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); 553 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); 554 psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE); 555 556 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 557 } 558 559 /* 560 * It is used to enable TE interrupt 561 */ 562 int mdfld_enable_te(struct drm_device *dev, int pipe) 563 { 564 struct drm_psb_private *dev_priv = 565 (struct drm_psb_private *) dev->dev_private; 566 unsigned long irqflags; 567 uint32_t reg_val = 0; 568 uint32_t pipeconf_reg = mid_pipeconf(pipe); 569 570 if (gma_power_begin(dev, false)) { 571 reg_val = REG_READ(pipeconf_reg); 572 gma_power_end(dev); 573 } 574 575 if (!(reg_val & PIPEACONF_ENABLE)) 576 return -EINVAL; 577 578 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 579 580 mid_enable_pipe_event(dev_priv, pipe); 581 psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE); 582 583 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 584 585 return 0; 586 } 587 588 /* 589 * It is used to disable TE interrupt 590 */ 591 void mdfld_disable_te(struct drm_device *dev, int pipe) 592 { 593 struct drm_psb_private *dev_priv = 594 (struct drm_psb_private *) dev->dev_private; 595 unsigned long irqflags; 596 597 if (!dev_priv->dsr_enable) 598 return; 599 600 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 601 602 mid_disable_pipe_event(dev_priv, pipe); 603 psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE); 604 605 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 606 } 607 608 /* Called from drm generic code, passed a 'crtc', which 609 * we use as a pipe index 610 */ 611 u32 psb_get_vblank_counter(struct drm_device *dev, unsigned int pipe) 612 { 613 uint32_t high_frame = PIPEAFRAMEHIGH; 614 uint32_t low_frame = PIPEAFRAMEPIXEL; 615 uint32_t pipeconf_reg = PIPEACONF; 616 uint32_t reg_val = 0; 617 uint32_t high1 = 0, high2 = 0, low = 0, count = 0; 618 619 switch (pipe) { 620 case 0: 621 break; 622 case 1: 623 high_frame = PIPEBFRAMEHIGH; 624 low_frame = PIPEBFRAMEPIXEL; 625 pipeconf_reg = PIPEBCONF; 626 break; 627 case 2: 628 high_frame = PIPECFRAMEHIGH; 629 low_frame = PIPECFRAMEPIXEL; 630 pipeconf_reg = PIPECCONF; 631 break; 632 default: 633 dev_err(dev->dev, "%s, invalid pipe.\n", __func__); 634 return 0; 635 } 636 637 if (!gma_power_begin(dev, false)) 638 return 0; 639 640 reg_val = REG_READ(pipeconf_reg); 641 642 if (!(reg_val & PIPEACONF_ENABLE)) { 643 dev_err(dev->dev, "trying to get vblank count for disabled pipe %u\n", 644 pipe); 645 goto psb_get_vblank_counter_exit; 646 } 647 648 /* 649 * High & low register fields aren't synchronized, so make sure 650 * we get a low value that's stable across two reads of the high 651 * register. 652 */ 653 do { 654 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> 655 PIPE_FRAME_HIGH_SHIFT); 656 low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> 657 PIPE_FRAME_LOW_SHIFT); 658 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> 659 PIPE_FRAME_HIGH_SHIFT); 660 } while (high1 != high2); 661 662 count = (high1 << 8) | low; 663 664 psb_get_vblank_counter_exit: 665 666 gma_power_end(dev); 667 668 return count; 669 } 670 671