1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/i2c.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/slab.h> 34 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 38 #include "psb_drv.h" 39 #include "psb_intel_drv.h" 40 #include "psb_intel_reg.h" 41 #include "psb_intel_sdvo_regs.h" 42 43 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 44 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 45 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 46 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0) 47 48 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 49 SDVO_TV_MASK) 50 51 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 52 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 53 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 54 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 55 56 57 static const char *tv_format_names[] = { 58 "NTSC_M" , "NTSC_J" , "NTSC_443", 59 "PAL_B" , "PAL_D" , "PAL_G" , 60 "PAL_H" , "PAL_I" , "PAL_M" , 61 "PAL_N" , "PAL_NC" , "PAL_60" , 62 "SECAM_B" , "SECAM_D" , "SECAM_G" , 63 "SECAM_K" , "SECAM_K1", "SECAM_L" , 64 "SECAM_60" 65 }; 66 67 struct psb_intel_sdvo { 68 struct gma_encoder base; 69 70 struct i2c_adapter *i2c; 71 u8 slave_addr; 72 73 struct i2c_adapter ddc; 74 75 /* Register for the SDVO device: SDVOB or SDVOC */ 76 int sdvo_reg; 77 78 /* Active outputs controlled by this SDVO output */ 79 uint16_t controlled_output; 80 81 /* 82 * Capabilities of the SDVO device returned by 83 * i830_sdvo_get_capabilities() 84 */ 85 struct psb_intel_sdvo_caps caps; 86 87 /* Pixel clock limitations reported by the SDVO device, in kHz */ 88 int pixel_clock_min, pixel_clock_max; 89 90 /* 91 * For multiple function SDVO device, 92 * this is for current attached outputs. 93 */ 94 uint16_t attached_output; 95 96 /** 97 * This is used to select the color range of RBG outputs in HDMI mode. 98 * It is only valid when using TMDS encoding and 8 bit per color mode. 99 */ 100 uint32_t color_range; 101 102 /** 103 * This is set if we're going to treat the device as TV-out. 104 * 105 * While we have these nice friendly flags for output types that ought 106 * to decide this for us, the S-Video output on our HDMI+S-Video card 107 * shows up as RGB1 (VGA). 108 */ 109 bool is_tv; 110 111 /* This is for current tv format name */ 112 int tv_format_index; 113 114 /** 115 * This is set if we treat the device as HDMI, instead of DVI. 116 */ 117 bool is_hdmi; 118 bool has_hdmi_monitor; 119 bool has_hdmi_audio; 120 121 /** 122 * This is set if we detect output of sdvo device as LVDS and 123 * have a valid fixed mode to use with the panel. 124 */ 125 bool is_lvds; 126 127 /** 128 * This is sdvo fixed pannel mode pointer 129 */ 130 struct drm_display_mode *sdvo_lvds_fixed_mode; 131 132 /* DDC bus used by this SDVO encoder */ 133 uint8_t ddc_bus; 134 135 /* Input timings for adjusted_mode */ 136 struct psb_intel_sdvo_dtd input_dtd; 137 138 /* Saved SDVO output states */ 139 uint32_t saveSDVO; /* Can be SDVOB or SDVOC depending on sdvo_reg */ 140 }; 141 142 struct psb_intel_sdvo_connector { 143 struct gma_connector base; 144 145 /* Mark the type of connector */ 146 uint16_t output_flag; 147 148 int force_audio; 149 150 /* This contains all current supported TV format */ 151 u8 tv_format_supported[ARRAY_SIZE(tv_format_names)]; 152 int format_supported_num; 153 struct drm_property *tv_format; 154 155 /* add the property for the SDVO-TV */ 156 struct drm_property *left; 157 struct drm_property *right; 158 struct drm_property *top; 159 struct drm_property *bottom; 160 struct drm_property *hpos; 161 struct drm_property *vpos; 162 struct drm_property *contrast; 163 struct drm_property *saturation; 164 struct drm_property *hue; 165 struct drm_property *sharpness; 166 struct drm_property *flicker_filter; 167 struct drm_property *flicker_filter_adaptive; 168 struct drm_property *flicker_filter_2d; 169 struct drm_property *tv_chroma_filter; 170 struct drm_property *tv_luma_filter; 171 struct drm_property *dot_crawl; 172 173 /* add the property for the SDVO-TV/LVDS */ 174 struct drm_property *brightness; 175 176 /* Add variable to record current setting for the above property */ 177 u32 left_margin, right_margin, top_margin, bottom_margin; 178 179 /* this is to get the range of margin.*/ 180 u32 max_hscan, max_vscan; 181 u32 max_hpos, cur_hpos; 182 u32 max_vpos, cur_vpos; 183 u32 cur_brightness, max_brightness; 184 u32 cur_contrast, max_contrast; 185 u32 cur_saturation, max_saturation; 186 u32 cur_hue, max_hue; 187 u32 cur_sharpness, max_sharpness; 188 u32 cur_flicker_filter, max_flicker_filter; 189 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; 190 u32 cur_flicker_filter_2d, max_flicker_filter_2d; 191 u32 cur_tv_chroma_filter, max_tv_chroma_filter; 192 u32 cur_tv_luma_filter, max_tv_luma_filter; 193 u32 cur_dot_crawl, max_dot_crawl; 194 }; 195 196 static struct psb_intel_sdvo *to_psb_intel_sdvo(struct drm_encoder *encoder) 197 { 198 return container_of(encoder, struct psb_intel_sdvo, base.base); 199 } 200 201 static struct psb_intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) 202 { 203 return container_of(gma_attached_encoder(connector), 204 struct psb_intel_sdvo, base); 205 } 206 207 static struct psb_intel_sdvo_connector *to_psb_intel_sdvo_connector(struct drm_connector *connector) 208 { 209 return container_of(to_gma_connector(connector), struct psb_intel_sdvo_connector, base); 210 } 211 212 static bool 213 psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags); 214 static bool 215 psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo, 216 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector, 217 int type); 218 static bool 219 psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo, 220 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector); 221 222 /** 223 * Writes the SDVOB or SDVOC with the given value, but always writes both 224 * SDVOB and SDVOC to work around apparent hardware issues (according to 225 * comments in the BIOS). 226 */ 227 static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u32 val) 228 { 229 struct drm_device *dev = psb_intel_sdvo->base.base.dev; 230 u32 bval = val, cval = val; 231 int i, j; 232 int need_aux = IS_MRST(dev) ? 1 : 0; 233 234 for (j = 0; j <= need_aux; j++) { 235 if (psb_intel_sdvo->sdvo_reg == SDVOB) 236 cval = REG_READ_WITH_AUX(SDVOC, j); 237 else 238 bval = REG_READ_WITH_AUX(SDVOB, j); 239 240 /* 241 * Write the registers twice for luck. Sometimes, 242 * writing them only once doesn't appear to 'stick'. 243 * The BIOS does this too. Yay, magic 244 */ 245 for (i = 0; i < 2; i++) { 246 REG_WRITE_WITH_AUX(SDVOB, bval, j); 247 REG_READ_WITH_AUX(SDVOB, j); 248 REG_WRITE_WITH_AUX(SDVOC, cval, j); 249 REG_READ_WITH_AUX(SDVOC, j); 250 } 251 } 252 } 253 254 static bool psb_intel_sdvo_read_byte(struct psb_intel_sdvo *psb_intel_sdvo, u8 addr, u8 *ch) 255 { 256 struct i2c_msg msgs[] = { 257 { 258 .addr = psb_intel_sdvo->slave_addr, 259 .flags = 0, 260 .len = 1, 261 .buf = &addr, 262 }, 263 { 264 .addr = psb_intel_sdvo->slave_addr, 265 .flags = I2C_M_RD, 266 .len = 1, 267 .buf = ch, 268 } 269 }; 270 int ret; 271 272 if ((ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, 2)) == 2) 273 return true; 274 275 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 276 return false; 277 } 278 279 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} 280 /** Mapping of command numbers to names, for debug output */ 281 static const struct _sdvo_cmd_name { 282 u8 cmd; 283 const char *name; 284 } sdvo_cmd_names[] = { 285 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), 286 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), 287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), 288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), 289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), 290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), 291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), 292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), 293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), 294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), 295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), 296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), 297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), 298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), 299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), 300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), 301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), 302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), 304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), 306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), 307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), 308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), 309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), 310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), 311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), 312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), 313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), 314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), 315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), 316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), 317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), 318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), 319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), 320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), 321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), 322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), 323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), 324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), 325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), 326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), 327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), 328 329 /* Add the op code for SDVO enhancements */ 330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), 331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), 332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), 333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), 334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), 335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), 339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), 341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), 342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), 343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), 344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), 345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), 346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), 347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), 348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), 349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), 350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), 351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), 353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), 354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), 355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), 356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), 357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), 358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), 359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), 360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), 361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), 362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), 363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), 364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), 365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), 366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), 367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), 368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), 369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), 370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), 371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), 372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), 373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), 374 375 /* HDMI op code */ 376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), 377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), 378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), 379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), 380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), 381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), 382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), 383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), 384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), 385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), 386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), 387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), 388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), 389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), 390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), 391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), 392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), 393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), 394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), 395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), 396 }; 397 398 #define IS_SDVOB(reg) (reg == SDVOB) 399 #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC") 400 401 static void psb_intel_sdvo_debug_write(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, 402 const void *args, int args_len) 403 { 404 int i; 405 406 DRM_DEBUG_KMS("%s: W: %02X ", 407 SDVO_NAME(psb_intel_sdvo), cmd); 408 for (i = 0; i < args_len; i++) 409 DRM_DEBUG_KMS("%02X ", ((u8 *)args)[i]); 410 for (; i < 8; i++) 411 DRM_DEBUG_KMS(" "); 412 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 413 if (cmd == sdvo_cmd_names[i].cmd) { 414 DRM_DEBUG_KMS("(%s)", sdvo_cmd_names[i].name); 415 break; 416 } 417 } 418 if (i == ARRAY_SIZE(sdvo_cmd_names)) 419 DRM_DEBUG_KMS("(%02X)", cmd); 420 DRM_DEBUG_KMS("\n"); 421 } 422 423 static const char *cmd_status_names[] = { 424 "Power on", 425 "Success", 426 "Not supported", 427 "Invalid arg", 428 "Pending", 429 "Target not specified", 430 "Scaling not supported" 431 }; 432 433 #define MAX_ARG_LEN 32 434 435 static bool psb_intel_sdvo_write_cmd(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, 436 const void *args, int args_len) 437 { 438 u8 buf[MAX_ARG_LEN*2 + 2], status; 439 struct i2c_msg msgs[MAX_ARG_LEN + 3]; 440 int i, ret; 441 442 if (args_len > MAX_ARG_LEN) { 443 DRM_ERROR("Need to increase arg length\n"); 444 return false; 445 } 446 447 psb_intel_sdvo_debug_write(psb_intel_sdvo, cmd, args, args_len); 448 449 for (i = 0; i < args_len; i++) { 450 msgs[i].addr = psb_intel_sdvo->slave_addr; 451 msgs[i].flags = 0; 452 msgs[i].len = 2; 453 msgs[i].buf = buf + 2 *i; 454 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 455 buf[2*i + 1] = ((u8*)args)[i]; 456 } 457 msgs[i].addr = psb_intel_sdvo->slave_addr; 458 msgs[i].flags = 0; 459 msgs[i].len = 2; 460 msgs[i].buf = buf + 2*i; 461 buf[2*i + 0] = SDVO_I2C_OPCODE; 462 buf[2*i + 1] = cmd; 463 464 /* the following two are to read the response */ 465 status = SDVO_I2C_CMD_STATUS; 466 msgs[i+1].addr = psb_intel_sdvo->slave_addr; 467 msgs[i+1].flags = 0; 468 msgs[i+1].len = 1; 469 msgs[i+1].buf = &status; 470 471 msgs[i+2].addr = psb_intel_sdvo->slave_addr; 472 msgs[i+2].flags = I2C_M_RD; 473 msgs[i+2].len = 1; 474 msgs[i+2].buf = &status; 475 476 ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, i+3); 477 if (ret < 0) { 478 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 479 return false; 480 } 481 if (ret != i+3) { 482 /* failure in I2C transfer */ 483 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 484 return false; 485 } 486 487 return true; 488 } 489 490 static bool psb_intel_sdvo_read_response(struct psb_intel_sdvo *psb_intel_sdvo, 491 void *response, int response_len) 492 { 493 u8 retry = 5; 494 u8 status; 495 int i; 496 497 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(psb_intel_sdvo)); 498 499 /* 500 * The documentation states that all commands will be 501 * processed within 15µs, and that we need only poll 502 * the status byte a maximum of 3 times in order for the 503 * command to be complete. 504 * 505 * Check 5 times in case the hardware failed to read the docs. 506 */ 507 if (!psb_intel_sdvo_read_byte(psb_intel_sdvo, 508 SDVO_I2C_CMD_STATUS, 509 &status)) 510 goto log_fail; 511 512 while ((status == SDVO_CMD_STATUS_PENDING || 513 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && retry--) { 514 udelay(15); 515 if (!psb_intel_sdvo_read_byte(psb_intel_sdvo, 516 SDVO_I2C_CMD_STATUS, 517 &status)) 518 goto log_fail; 519 } 520 521 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) 522 DRM_DEBUG_KMS("(%s)", cmd_status_names[status]); 523 else 524 DRM_DEBUG_KMS("(??? %d)", status); 525 526 if (status != SDVO_CMD_STATUS_SUCCESS) 527 goto log_fail; 528 529 /* Read the command response */ 530 for (i = 0; i < response_len; i++) { 531 if (!psb_intel_sdvo_read_byte(psb_intel_sdvo, 532 SDVO_I2C_RETURN_0 + i, 533 &((u8 *)response)[i])) 534 goto log_fail; 535 DRM_DEBUG_KMS(" %02X", ((u8 *)response)[i]); 536 } 537 DRM_DEBUG_KMS("\n"); 538 return true; 539 540 log_fail: 541 DRM_DEBUG_KMS("... failed\n"); 542 return false; 543 } 544 545 static int psb_intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) 546 { 547 if (mode->clock >= 100000) 548 return 1; 549 else if (mode->clock >= 50000) 550 return 2; 551 else 552 return 4; 553 } 554 555 static bool psb_intel_sdvo_set_control_bus_switch(struct psb_intel_sdvo *psb_intel_sdvo, 556 u8 ddc_bus) 557 { 558 /* This must be the immediately preceding write before the i2c xfer */ 559 return psb_intel_sdvo_write_cmd(psb_intel_sdvo, 560 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 561 &ddc_bus, 1); 562 } 563 564 static bool psb_intel_sdvo_set_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, const void *data, int len) 565 { 566 if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, data, len)) 567 return false; 568 569 return psb_intel_sdvo_read_response(psb_intel_sdvo, NULL, 0); 570 } 571 572 static bool 573 psb_intel_sdvo_get_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, void *value, int len) 574 { 575 if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, NULL, 0)) 576 return false; 577 578 return psb_intel_sdvo_read_response(psb_intel_sdvo, value, len); 579 } 580 581 static bool psb_intel_sdvo_set_target_input(struct psb_intel_sdvo *psb_intel_sdvo) 582 { 583 struct psb_intel_sdvo_set_target_input_args targets = {0}; 584 return psb_intel_sdvo_set_value(psb_intel_sdvo, 585 SDVO_CMD_SET_TARGET_INPUT, 586 &targets, sizeof(targets)); 587 } 588 589 /** 590 * Return whether each input is trained. 591 * 592 * This function is making an assumption about the layout of the response, 593 * which should be checked against the docs. 594 */ 595 static bool psb_intel_sdvo_get_trained_inputs(struct psb_intel_sdvo *psb_intel_sdvo, bool *input_1, bool *input_2) 596 { 597 struct psb_intel_sdvo_get_trained_inputs_response response; 598 599 BUILD_BUG_ON(sizeof(response) != 1); 600 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 601 &response, sizeof(response))) 602 return false; 603 604 *input_1 = response.input0_trained; 605 *input_2 = response.input1_trained; 606 return true; 607 } 608 609 static bool psb_intel_sdvo_set_active_outputs(struct psb_intel_sdvo *psb_intel_sdvo, 610 u16 outputs) 611 { 612 return psb_intel_sdvo_set_value(psb_intel_sdvo, 613 SDVO_CMD_SET_ACTIVE_OUTPUTS, 614 &outputs, sizeof(outputs)); 615 } 616 617 static bool psb_intel_sdvo_set_encoder_power_state(struct psb_intel_sdvo *psb_intel_sdvo, 618 int mode) 619 { 620 u8 state = SDVO_ENCODER_STATE_ON; 621 622 switch (mode) { 623 case DRM_MODE_DPMS_ON: 624 state = SDVO_ENCODER_STATE_ON; 625 break; 626 case DRM_MODE_DPMS_STANDBY: 627 state = SDVO_ENCODER_STATE_STANDBY; 628 break; 629 case DRM_MODE_DPMS_SUSPEND: 630 state = SDVO_ENCODER_STATE_SUSPEND; 631 break; 632 case DRM_MODE_DPMS_OFF: 633 state = SDVO_ENCODER_STATE_OFF; 634 break; 635 } 636 637 return psb_intel_sdvo_set_value(psb_intel_sdvo, 638 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 639 } 640 641 static bool psb_intel_sdvo_get_input_pixel_clock_range(struct psb_intel_sdvo *psb_intel_sdvo, 642 int *clock_min, 643 int *clock_max) 644 { 645 struct psb_intel_sdvo_pixel_clock_range clocks; 646 647 BUILD_BUG_ON(sizeof(clocks) != 4); 648 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, 649 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 650 &clocks, sizeof(clocks))) 651 return false; 652 653 /* Convert the values from units of 10 kHz to kHz. */ 654 *clock_min = clocks.min * 10; 655 *clock_max = clocks.max * 10; 656 return true; 657 } 658 659 static bool psb_intel_sdvo_set_target_output(struct psb_intel_sdvo *psb_intel_sdvo, 660 u16 outputs) 661 { 662 return psb_intel_sdvo_set_value(psb_intel_sdvo, 663 SDVO_CMD_SET_TARGET_OUTPUT, 664 &outputs, sizeof(outputs)); 665 } 666 667 static bool psb_intel_sdvo_set_timing(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, 668 struct psb_intel_sdvo_dtd *dtd) 669 { 670 return psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 671 psb_intel_sdvo_set_value(psb_intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 672 } 673 674 static bool psb_intel_sdvo_set_input_timing(struct psb_intel_sdvo *psb_intel_sdvo, 675 struct psb_intel_sdvo_dtd *dtd) 676 { 677 return psb_intel_sdvo_set_timing(psb_intel_sdvo, 678 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 679 } 680 681 static bool psb_intel_sdvo_set_output_timing(struct psb_intel_sdvo *psb_intel_sdvo, 682 struct psb_intel_sdvo_dtd *dtd) 683 { 684 return psb_intel_sdvo_set_timing(psb_intel_sdvo, 685 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 686 } 687 688 static bool 689 psb_intel_sdvo_create_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo, 690 uint16_t clock, 691 uint16_t width, 692 uint16_t height) 693 { 694 struct psb_intel_sdvo_preferred_input_timing_args args; 695 696 memset(&args, 0, sizeof(args)); 697 args.clock = clock; 698 args.width = width; 699 args.height = height; 700 args.interlace = 0; 701 702 if (psb_intel_sdvo->is_lvds && 703 (psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || 704 psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) 705 args.scaled = 1; 706 707 return psb_intel_sdvo_set_value(psb_intel_sdvo, 708 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 709 &args, sizeof(args)); 710 } 711 712 static bool psb_intel_sdvo_get_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo, 713 struct psb_intel_sdvo_dtd *dtd) 714 { 715 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 716 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 717 return psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 718 &dtd->part1, sizeof(dtd->part1)) && 719 psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 720 &dtd->part2, sizeof(dtd->part2)); 721 } 722 723 static bool psb_intel_sdvo_set_clock_rate_mult(struct psb_intel_sdvo *psb_intel_sdvo, u8 val) 724 { 725 return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 726 } 727 728 static void psb_intel_sdvo_get_dtd_from_mode(struct psb_intel_sdvo_dtd *dtd, 729 const struct drm_display_mode *mode) 730 { 731 uint16_t width, height; 732 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; 733 uint16_t h_sync_offset, v_sync_offset; 734 735 width = mode->crtc_hdisplay; 736 height = mode->crtc_vdisplay; 737 738 /* do some mode translations */ 739 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start; 740 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 741 742 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start; 743 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 744 745 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start; 746 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start; 747 748 dtd->part1.clock = mode->clock / 10; 749 dtd->part1.h_active = width & 0xff; 750 dtd->part1.h_blank = h_blank_len & 0xff; 751 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 752 ((h_blank_len >> 8) & 0xf); 753 dtd->part1.v_active = height & 0xff; 754 dtd->part1.v_blank = v_blank_len & 0xff; 755 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 756 ((v_blank_len >> 8) & 0xf); 757 758 dtd->part2.h_sync_off = h_sync_offset & 0xff; 759 dtd->part2.h_sync_width = h_sync_len & 0xff; 760 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 761 (v_sync_len & 0xf); 762 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 763 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 764 ((v_sync_len & 0x30) >> 4); 765 766 dtd->part2.dtd_flags = 0x18; 767 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 768 dtd->part2.dtd_flags |= 0x2; 769 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 770 dtd->part2.dtd_flags |= 0x4; 771 772 dtd->part2.sdvo_flags = 0; 773 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 774 dtd->part2.reserved = 0; 775 } 776 777 static void psb_intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, 778 const struct psb_intel_sdvo_dtd *dtd) 779 { 780 mode->hdisplay = dtd->part1.h_active; 781 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 782 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; 783 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 784 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; 785 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 786 mode->htotal = mode->hdisplay + dtd->part1.h_blank; 787 mode->htotal += (dtd->part1.h_high & 0xf) << 8; 788 789 mode->vdisplay = dtd->part1.v_active; 790 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 791 mode->vsync_start = mode->vdisplay; 792 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 793 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 794 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; 795 mode->vsync_end = mode->vsync_start + 796 (dtd->part2.v_sync_off_width & 0xf); 797 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 798 mode->vtotal = mode->vdisplay + dtd->part1.v_blank; 799 mode->vtotal += (dtd->part1.v_high & 0xf) << 8; 800 801 mode->clock = dtd->part1.clock * 10; 802 803 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 804 if (dtd->part2.dtd_flags & 0x2) 805 mode->flags |= DRM_MODE_FLAG_PHSYNC; 806 if (dtd->part2.dtd_flags & 0x4) 807 mode->flags |= DRM_MODE_FLAG_PVSYNC; 808 } 809 810 static bool psb_intel_sdvo_check_supp_encode(struct psb_intel_sdvo *psb_intel_sdvo) 811 { 812 struct psb_intel_sdvo_encode encode; 813 814 BUILD_BUG_ON(sizeof(encode) != 2); 815 return psb_intel_sdvo_get_value(psb_intel_sdvo, 816 SDVO_CMD_GET_SUPP_ENCODE, 817 &encode, sizeof(encode)); 818 } 819 820 static bool psb_intel_sdvo_set_encode(struct psb_intel_sdvo *psb_intel_sdvo, 821 uint8_t mode) 822 { 823 return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 824 } 825 826 static bool psb_intel_sdvo_set_colorimetry(struct psb_intel_sdvo *psb_intel_sdvo, 827 uint8_t mode) 828 { 829 return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 830 } 831 832 #if 0 833 static void psb_intel_sdvo_dump_hdmi_buf(struct psb_intel_sdvo *psb_intel_sdvo) 834 { 835 int i, j; 836 uint8_t set_buf_index[2]; 837 uint8_t av_split; 838 uint8_t buf_size; 839 uint8_t buf[48]; 840 uint8_t *pos; 841 842 psb_intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 843 844 for (i = 0; i <= av_split; i++) { 845 set_buf_index[0] = i; set_buf_index[1] = 0; 846 psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 847 set_buf_index, 2); 848 psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 849 psb_intel_sdvo_read_response(encoder, &buf_size, 1); 850 851 pos = buf; 852 for (j = 0; j <= buf_size; j += 8) { 853 psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 854 NULL, 0); 855 psb_intel_sdvo_read_response(encoder, pos, 8); 856 pos += 8; 857 } 858 } 859 } 860 #endif 861 862 static bool psb_intel_sdvo_set_avi_infoframe(struct psb_intel_sdvo *psb_intel_sdvo) 863 { 864 DRM_INFO("HDMI is not supported yet"); 865 866 return false; 867 } 868 869 static bool psb_intel_sdvo_set_tv_format(struct psb_intel_sdvo *psb_intel_sdvo) 870 { 871 struct psb_intel_sdvo_tv_format format; 872 uint32_t format_map; 873 874 format_map = 1 << psb_intel_sdvo->tv_format_index; 875 memset(&format, 0, sizeof(format)); 876 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 877 878 BUILD_BUG_ON(sizeof(format) != 6); 879 return psb_intel_sdvo_set_value(psb_intel_sdvo, 880 SDVO_CMD_SET_TV_FORMAT, 881 &format, sizeof(format)); 882 } 883 884 static bool 885 psb_intel_sdvo_set_output_timings_from_mode(struct psb_intel_sdvo *psb_intel_sdvo, 886 const struct drm_display_mode *mode) 887 { 888 struct psb_intel_sdvo_dtd output_dtd; 889 890 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, 891 psb_intel_sdvo->attached_output)) 892 return false; 893 894 psb_intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 895 if (!psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &output_dtd)) 896 return false; 897 898 return true; 899 } 900 901 static bool 902 psb_intel_sdvo_set_input_timings_for_mode(struct psb_intel_sdvo *psb_intel_sdvo, 903 const struct drm_display_mode *mode, 904 struct drm_display_mode *adjusted_mode) 905 { 906 /* Reset the input timing to the screen. Assume always input 0. */ 907 if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo)) 908 return false; 909 910 if (!psb_intel_sdvo_create_preferred_input_timing(psb_intel_sdvo, 911 mode->clock / 10, 912 mode->hdisplay, 913 mode->vdisplay)) 914 return false; 915 916 if (!psb_intel_sdvo_get_preferred_input_timing(psb_intel_sdvo, 917 &psb_intel_sdvo->input_dtd)) 918 return false; 919 920 psb_intel_sdvo_get_mode_from_dtd(adjusted_mode, &psb_intel_sdvo->input_dtd); 921 922 drm_mode_set_crtcinfo(adjusted_mode, 0); 923 return true; 924 } 925 926 static bool psb_intel_sdvo_mode_fixup(struct drm_encoder *encoder, 927 const struct drm_display_mode *mode, 928 struct drm_display_mode *adjusted_mode) 929 { 930 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder); 931 int multiplier; 932 933 /* We need to construct preferred input timings based on our 934 * output timings. To do that, we have to set the output 935 * timings, even though this isn't really the right place in 936 * the sequence to do it. Oh well. 937 */ 938 if (psb_intel_sdvo->is_tv) { 939 if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo, mode)) 940 return false; 941 942 (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo, 943 mode, 944 adjusted_mode); 945 } else if (psb_intel_sdvo->is_lvds) { 946 if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo, 947 psb_intel_sdvo->sdvo_lvds_fixed_mode)) 948 return false; 949 950 (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo, 951 mode, 952 adjusted_mode); 953 } 954 955 /* Make the CRTC code factor in the SDVO pixel multiplier. The 956 * SDVO device will factor out the multiplier during mode_set. 957 */ 958 multiplier = psb_intel_sdvo_get_pixel_multiplier(adjusted_mode); 959 psb_intel_mode_set_pixel_multiplier(adjusted_mode, multiplier); 960 961 return true; 962 } 963 964 static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder, 965 struct drm_display_mode *mode, 966 struct drm_display_mode *adjusted_mode) 967 { 968 struct drm_device *dev = encoder->dev; 969 struct drm_crtc *crtc = encoder->crtc; 970 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 971 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder); 972 u32 sdvox; 973 struct psb_intel_sdvo_in_out_map in_out; 974 struct psb_intel_sdvo_dtd input_dtd; 975 int pixel_multiplier = psb_intel_mode_get_pixel_multiplier(adjusted_mode); 976 int rate; 977 int need_aux = IS_MRST(dev) ? 1 : 0; 978 979 if (!mode) 980 return; 981 982 /* First, set the input mapping for the first input to our controlled 983 * output. This is only correct if we're a single-input device, in 984 * which case the first input is the output from the appropriate SDVO 985 * channel on the motherboard. In a two-input device, the first input 986 * will be SDVOB and the second SDVOC. 987 */ 988 in_out.in0 = psb_intel_sdvo->attached_output; 989 in_out.in1 = 0; 990 991 psb_intel_sdvo_set_value(psb_intel_sdvo, 992 SDVO_CMD_SET_IN_OUT_MAP, 993 &in_out, sizeof(in_out)); 994 995 /* Set the output timings to the screen */ 996 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, 997 psb_intel_sdvo->attached_output)) 998 return; 999 1000 /* We have tried to get input timing in mode_fixup, and filled into 1001 * adjusted_mode. 1002 */ 1003 if (psb_intel_sdvo->is_tv || psb_intel_sdvo->is_lvds) { 1004 input_dtd = psb_intel_sdvo->input_dtd; 1005 } else { 1006 /* Set the output timing to the screen */ 1007 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, 1008 psb_intel_sdvo->attached_output)) 1009 return; 1010 1011 psb_intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1012 (void) psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &input_dtd); 1013 } 1014 1015 /* Set the input timing to the screen. Assume always input 0. */ 1016 if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo)) 1017 return; 1018 1019 if (psb_intel_sdvo->has_hdmi_monitor) { 1020 psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_HDMI); 1021 psb_intel_sdvo_set_colorimetry(psb_intel_sdvo, 1022 SDVO_COLORIMETRY_RGB256); 1023 psb_intel_sdvo_set_avi_infoframe(psb_intel_sdvo); 1024 } else 1025 psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_DVI); 1026 1027 if (psb_intel_sdvo->is_tv && 1028 !psb_intel_sdvo_set_tv_format(psb_intel_sdvo)) 1029 return; 1030 1031 (void) psb_intel_sdvo_set_input_timing(psb_intel_sdvo, &input_dtd); 1032 1033 switch (pixel_multiplier) { 1034 default: 1035 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1036 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1037 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1038 } 1039 if (!psb_intel_sdvo_set_clock_rate_mult(psb_intel_sdvo, rate)) 1040 return; 1041 1042 /* Set the SDVO control regs. */ 1043 if (need_aux) 1044 sdvox = REG_READ_AUX(psb_intel_sdvo->sdvo_reg); 1045 else 1046 sdvox = REG_READ(psb_intel_sdvo->sdvo_reg); 1047 1048 switch (psb_intel_sdvo->sdvo_reg) { 1049 case SDVOB: 1050 sdvox &= SDVOB_PRESERVE_MASK; 1051 break; 1052 case SDVOC: 1053 sdvox &= SDVOC_PRESERVE_MASK; 1054 break; 1055 } 1056 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1057 1058 if (gma_crtc->pipe == 1) 1059 sdvox |= SDVO_PIPE_B_SELECT; 1060 if (psb_intel_sdvo->has_hdmi_audio) 1061 sdvox |= SDVO_AUDIO_ENABLE; 1062 1063 /* FIXME: Check if this is needed for PSB 1064 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT; 1065 */ 1066 1067 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL) 1068 sdvox |= SDVO_STALL_SELECT; 1069 psb_intel_sdvo_write_sdvox(psb_intel_sdvo, sdvox); 1070 } 1071 1072 static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode) 1073 { 1074 struct drm_device *dev = encoder->dev; 1075 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder); 1076 u32 temp; 1077 int i; 1078 int need_aux = IS_MRST(dev) ? 1 : 0; 1079 1080 switch (mode) { 1081 case DRM_MODE_DPMS_ON: 1082 DRM_DEBUG("DPMS_ON"); 1083 break; 1084 case DRM_MODE_DPMS_OFF: 1085 DRM_DEBUG("DPMS_OFF"); 1086 break; 1087 default: 1088 DRM_DEBUG("DPMS: %d", mode); 1089 } 1090 1091 if (mode != DRM_MODE_DPMS_ON) { 1092 psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, 0); 1093 if (0) 1094 psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode); 1095 1096 if (mode == DRM_MODE_DPMS_OFF) { 1097 if (need_aux) 1098 temp = REG_READ_AUX(psb_intel_sdvo->sdvo_reg); 1099 else 1100 temp = REG_READ(psb_intel_sdvo->sdvo_reg); 1101 1102 if ((temp & SDVO_ENABLE) != 0) { 1103 psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp & ~SDVO_ENABLE); 1104 } 1105 } 1106 } else { 1107 bool input1, input2; 1108 u8 status; 1109 1110 if (need_aux) 1111 temp = REG_READ_AUX(psb_intel_sdvo->sdvo_reg); 1112 else 1113 temp = REG_READ(psb_intel_sdvo->sdvo_reg); 1114 1115 if ((temp & SDVO_ENABLE) == 0) 1116 psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE); 1117 1118 for (i = 0; i < 2; i++) 1119 gma_wait_for_vblank(dev); 1120 1121 status = psb_intel_sdvo_get_trained_inputs(psb_intel_sdvo, &input1, &input2); 1122 /* Warn if the device reported failure to sync. 1123 * A lot of SDVO devices fail to notify of sync, but it's 1124 * a given it the status is a success, we succeeded. 1125 */ 1126 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { 1127 DRM_DEBUG_KMS("First %s output reported failure to " 1128 "sync\n", SDVO_NAME(psb_intel_sdvo)); 1129 } 1130 1131 if (0) 1132 psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode); 1133 psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, psb_intel_sdvo->attached_output); 1134 } 1135 return; 1136 } 1137 1138 static enum drm_mode_status psb_intel_sdvo_mode_valid(struct drm_connector *connector, 1139 struct drm_display_mode *mode) 1140 { 1141 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector); 1142 1143 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1144 return MODE_NO_DBLESCAN; 1145 1146 if (psb_intel_sdvo->pixel_clock_min > mode->clock) 1147 return MODE_CLOCK_LOW; 1148 1149 if (psb_intel_sdvo->pixel_clock_max < mode->clock) 1150 return MODE_CLOCK_HIGH; 1151 1152 if (psb_intel_sdvo->is_lvds) { 1153 if (mode->hdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) 1154 return MODE_PANEL; 1155 1156 if (mode->vdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) 1157 return MODE_PANEL; 1158 } 1159 1160 return MODE_OK; 1161 } 1162 1163 static bool psb_intel_sdvo_get_capabilities(struct psb_intel_sdvo *psb_intel_sdvo, struct psb_intel_sdvo_caps *caps) 1164 { 1165 BUILD_BUG_ON(sizeof(*caps) != 8); 1166 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, 1167 SDVO_CMD_GET_DEVICE_CAPS, 1168 caps, sizeof(*caps))) 1169 return false; 1170 1171 DRM_DEBUG_KMS("SDVO capabilities:\n" 1172 " vendor_id: %d\n" 1173 " device_id: %d\n" 1174 " device_rev_id: %d\n" 1175 " sdvo_version_major: %d\n" 1176 " sdvo_version_minor: %d\n" 1177 " sdvo_inputs_mask: %d\n" 1178 " smooth_scaling: %d\n" 1179 " sharp_scaling: %d\n" 1180 " up_scaling: %d\n" 1181 " down_scaling: %d\n" 1182 " stall_support: %d\n" 1183 " output_flags: %d\n", 1184 caps->vendor_id, 1185 caps->device_id, 1186 caps->device_rev_id, 1187 caps->sdvo_version_major, 1188 caps->sdvo_version_minor, 1189 caps->sdvo_inputs_mask, 1190 caps->smooth_scaling, 1191 caps->sharp_scaling, 1192 caps->up_scaling, 1193 caps->down_scaling, 1194 caps->stall_support, 1195 caps->output_flags); 1196 1197 return true; 1198 } 1199 1200 static bool 1201 psb_intel_sdvo_multifunc_encoder(struct psb_intel_sdvo *psb_intel_sdvo) 1202 { 1203 /* Is there more than one type of output? */ 1204 int caps = psb_intel_sdvo->caps.output_flags & 0xf; 1205 return caps & -caps; 1206 } 1207 1208 static struct edid * 1209 psb_intel_sdvo_get_edid(struct drm_connector *connector) 1210 { 1211 struct psb_intel_sdvo *sdvo = intel_attached_sdvo(connector); 1212 return drm_get_edid(connector, &sdvo->ddc); 1213 } 1214 1215 /* Mac mini hack -- use the same DDC as the analog connector */ 1216 static struct edid * 1217 psb_intel_sdvo_get_analog_edid(struct drm_connector *connector) 1218 { 1219 struct drm_psb_private *dev_priv = connector->dev->dev_private; 1220 1221 return drm_get_edid(connector, 1222 &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter); 1223 } 1224 1225 static enum drm_connector_status 1226 psb_intel_sdvo_hdmi_sink_detect(struct drm_connector *connector) 1227 { 1228 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector); 1229 enum drm_connector_status status; 1230 struct edid *edid; 1231 1232 edid = psb_intel_sdvo_get_edid(connector); 1233 1234 if (edid == NULL && psb_intel_sdvo_multifunc_encoder(psb_intel_sdvo)) { 1235 u8 ddc, saved_ddc = psb_intel_sdvo->ddc_bus; 1236 1237 /* 1238 * Don't use the 1 as the argument of DDC bus switch to get 1239 * the EDID. It is used for SDVO SPD ROM. 1240 */ 1241 for (ddc = psb_intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 1242 psb_intel_sdvo->ddc_bus = ddc; 1243 edid = psb_intel_sdvo_get_edid(connector); 1244 if (edid) 1245 break; 1246 } 1247 /* 1248 * If we found the EDID on the other bus, 1249 * assume that is the correct DDC bus. 1250 */ 1251 if (edid == NULL) 1252 psb_intel_sdvo->ddc_bus = saved_ddc; 1253 } 1254 1255 /* 1256 * When there is no edid and no monitor is connected with VGA 1257 * port, try to use the CRT ddc to read the EDID for DVI-connector. 1258 */ 1259 if (edid == NULL) 1260 edid = psb_intel_sdvo_get_analog_edid(connector); 1261 1262 status = connector_status_unknown; 1263 if (edid != NULL) { 1264 /* DDC bus is shared, match EDID to connector type */ 1265 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 1266 status = connector_status_connected; 1267 if (psb_intel_sdvo->is_hdmi) { 1268 psb_intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 1269 psb_intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 1270 } 1271 } else 1272 status = connector_status_disconnected; 1273 kfree(edid); 1274 } 1275 1276 if (status == connector_status_connected) { 1277 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector); 1278 if (psb_intel_sdvo_connector->force_audio) 1279 psb_intel_sdvo->has_hdmi_audio = psb_intel_sdvo_connector->force_audio > 0; 1280 } 1281 1282 return status; 1283 } 1284 1285 static enum drm_connector_status 1286 psb_intel_sdvo_detect(struct drm_connector *connector, bool force) 1287 { 1288 uint16_t response; 1289 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector); 1290 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector); 1291 enum drm_connector_status ret; 1292 1293 if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, 1294 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0)) 1295 return connector_status_unknown; 1296 1297 /* add 30ms delay when the output type might be TV */ 1298 if (psb_intel_sdvo->caps.output_flags & 1299 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0)) 1300 mdelay(30); 1301 1302 if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2)) 1303 return connector_status_unknown; 1304 1305 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 1306 response & 0xff, response >> 8, 1307 psb_intel_sdvo_connector->output_flag); 1308 1309 if (response == 0) 1310 return connector_status_disconnected; 1311 1312 psb_intel_sdvo->attached_output = response; 1313 1314 psb_intel_sdvo->has_hdmi_monitor = false; 1315 psb_intel_sdvo->has_hdmi_audio = false; 1316 1317 if ((psb_intel_sdvo_connector->output_flag & response) == 0) 1318 ret = connector_status_disconnected; 1319 else if (IS_TMDS(psb_intel_sdvo_connector)) 1320 ret = psb_intel_sdvo_hdmi_sink_detect(connector); 1321 else { 1322 struct edid *edid; 1323 1324 /* if we have an edid check it matches the connection */ 1325 edid = psb_intel_sdvo_get_edid(connector); 1326 if (edid == NULL) 1327 edid = psb_intel_sdvo_get_analog_edid(connector); 1328 if (edid != NULL) { 1329 if (edid->input & DRM_EDID_INPUT_DIGITAL) 1330 ret = connector_status_disconnected; 1331 else 1332 ret = connector_status_connected; 1333 kfree(edid); 1334 } else 1335 ret = connector_status_connected; 1336 } 1337 1338 /* May update encoder flag for like clock for SDVO TV, etc.*/ 1339 if (ret == connector_status_connected) { 1340 psb_intel_sdvo->is_tv = false; 1341 psb_intel_sdvo->is_lvds = false; 1342 psb_intel_sdvo->base.needs_tv_clock = false; 1343 1344 if (response & SDVO_TV_MASK) { 1345 psb_intel_sdvo->is_tv = true; 1346 psb_intel_sdvo->base.needs_tv_clock = true; 1347 } 1348 if (response & SDVO_LVDS_MASK) 1349 psb_intel_sdvo->is_lvds = psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL; 1350 } 1351 1352 return ret; 1353 } 1354 1355 static void psb_intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1356 { 1357 struct edid *edid; 1358 1359 /* set the bus switch and get the modes */ 1360 edid = psb_intel_sdvo_get_edid(connector); 1361 1362 /* 1363 * Mac mini hack. On this device, the DVI-I connector shares one DDC 1364 * link between analog and digital outputs. So, if the regular SDVO 1365 * DDC fails, check to see if the analog output is disconnected, in 1366 * which case we'll look there for the digital DDC data. 1367 */ 1368 if (edid == NULL) 1369 edid = psb_intel_sdvo_get_analog_edid(connector); 1370 1371 if (edid != NULL) { 1372 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector); 1373 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 1374 bool connector_is_digital = !!IS_TMDS(psb_intel_sdvo_connector); 1375 1376 if (connector_is_digital == monitor_is_digital) { 1377 drm_connector_update_edid_property(connector, edid); 1378 drm_add_edid_modes(connector, edid); 1379 } 1380 1381 kfree(edid); 1382 } 1383 } 1384 1385 /* 1386 * Set of SDVO TV modes. 1387 * Note! This is in reply order (see loop in get_tv_modes). 1388 * XXX: all 60Hz refresh? 1389 */ 1390 static const struct drm_display_mode sdvo_tv_modes[] = { 1391 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 1392 416, 0, 200, 201, 232, 233, 0, 1393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1394 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 1395 416, 0, 240, 241, 272, 273, 0, 1396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1397 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 1398 496, 0, 300, 301, 332, 333, 0, 1399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1400 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 1401 736, 0, 350, 351, 382, 383, 0, 1402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1403 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 1404 736, 0, 400, 401, 432, 433, 0, 1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1406 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 1407 736, 0, 480, 481, 512, 513, 0, 1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1409 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 1410 800, 0, 480, 481, 512, 513, 0, 1411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1412 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 1413 800, 0, 576, 577, 608, 609, 0, 1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1415 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 1416 816, 0, 350, 351, 382, 383, 0, 1417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1418 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 1419 816, 0, 400, 401, 432, 433, 0, 1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1421 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 1422 816, 0, 480, 481, 512, 513, 0, 1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1424 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 1425 816, 0, 540, 541, 572, 573, 0, 1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1427 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 1428 816, 0, 576, 577, 608, 609, 0, 1429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1430 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 1431 864, 0, 576, 577, 608, 609, 0, 1432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1433 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 1434 896, 0, 600, 601, 632, 633, 0, 1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1436 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 1437 928, 0, 624, 625, 656, 657, 0, 1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1439 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 1440 1016, 0, 766, 767, 798, 799, 0, 1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1442 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 1443 1120, 0, 768, 769, 800, 801, 0, 1444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1445 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 1446 1376, 0, 1024, 1025, 1056, 1057, 0, 1447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1448 }; 1449 1450 static void psb_intel_sdvo_get_tv_modes(struct drm_connector *connector) 1451 { 1452 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector); 1453 struct psb_intel_sdvo_sdtv_resolution_request tv_res; 1454 uint32_t reply = 0, format_map = 0; 1455 int i; 1456 1457 /* Read the list of supported input resolutions for the selected TV 1458 * format. 1459 */ 1460 format_map = 1 << psb_intel_sdvo->tv_format_index; 1461 memcpy(&tv_res, &format_map, 1462 min(sizeof(format_map), sizeof(struct psb_intel_sdvo_sdtv_resolution_request))); 1463 1464 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, psb_intel_sdvo->attached_output)) 1465 return; 1466 1467 BUILD_BUG_ON(sizeof(tv_res) != 3); 1468 if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, 1469 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 1470 &tv_res, sizeof(tv_res))) 1471 return; 1472 if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &reply, 3)) 1473 return; 1474 1475 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 1476 if (reply & (1 << i)) { 1477 struct drm_display_mode *nmode; 1478 nmode = drm_mode_duplicate(connector->dev, 1479 &sdvo_tv_modes[i]); 1480 if (nmode) 1481 drm_mode_probed_add(connector, nmode); 1482 } 1483 } 1484 1485 static void psb_intel_sdvo_get_lvds_modes(struct drm_connector *connector) 1486 { 1487 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector); 1488 struct drm_psb_private *dev_priv = connector->dev->dev_private; 1489 struct drm_display_mode *newmode; 1490 1491 /* 1492 * Attempt to get the mode list from DDC. 1493 * Assume that the preferred modes are 1494 * arranged in priority order. 1495 */ 1496 psb_intel_ddc_get_modes(connector, psb_intel_sdvo->i2c); 1497 if (list_empty(&connector->probed_modes) == false) 1498 goto end; 1499 1500 /* Fetch modes from VBT */ 1501 if (dev_priv->sdvo_lvds_vbt_mode != NULL) { 1502 newmode = drm_mode_duplicate(connector->dev, 1503 dev_priv->sdvo_lvds_vbt_mode); 1504 if (newmode != NULL) { 1505 /* Guarantee the mode is preferred */ 1506 newmode->type = (DRM_MODE_TYPE_PREFERRED | 1507 DRM_MODE_TYPE_DRIVER); 1508 drm_mode_probed_add(connector, newmode); 1509 } 1510 } 1511 1512 end: 1513 list_for_each_entry(newmode, &connector->probed_modes, head) { 1514 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1515 psb_intel_sdvo->sdvo_lvds_fixed_mode = 1516 drm_mode_duplicate(connector->dev, newmode); 1517 1518 drm_mode_set_crtcinfo(psb_intel_sdvo->sdvo_lvds_fixed_mode, 1519 0); 1520 1521 psb_intel_sdvo->is_lvds = true; 1522 break; 1523 } 1524 } 1525 1526 } 1527 1528 static int psb_intel_sdvo_get_modes(struct drm_connector *connector) 1529 { 1530 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector); 1531 1532 if (IS_TV(psb_intel_sdvo_connector)) 1533 psb_intel_sdvo_get_tv_modes(connector); 1534 else if (IS_LVDS(psb_intel_sdvo_connector)) 1535 psb_intel_sdvo_get_lvds_modes(connector); 1536 else 1537 psb_intel_sdvo_get_ddc_modes(connector); 1538 1539 return !list_empty(&connector->probed_modes); 1540 } 1541 1542 static void psb_intel_sdvo_destroy(struct drm_connector *connector) 1543 { 1544 drm_connector_unregister(connector); 1545 drm_connector_cleanup(connector); 1546 kfree(connector); 1547 } 1548 1549 static bool psb_intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) 1550 { 1551 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector); 1552 struct edid *edid; 1553 bool has_audio = false; 1554 1555 if (!psb_intel_sdvo->is_hdmi) 1556 return false; 1557 1558 edid = psb_intel_sdvo_get_edid(connector); 1559 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) 1560 has_audio = drm_detect_monitor_audio(edid); 1561 1562 return has_audio; 1563 } 1564 1565 static int 1566 psb_intel_sdvo_set_property(struct drm_connector *connector, 1567 struct drm_property *property, 1568 uint64_t val) 1569 { 1570 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector); 1571 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector); 1572 struct drm_psb_private *dev_priv = connector->dev->dev_private; 1573 uint16_t temp_value; 1574 uint8_t cmd; 1575 int ret; 1576 1577 ret = drm_object_property_set_value(&connector->base, property, val); 1578 if (ret) 1579 return ret; 1580 1581 if (property == dev_priv->force_audio_property) { 1582 int i = val; 1583 bool has_audio; 1584 1585 if (i == psb_intel_sdvo_connector->force_audio) 1586 return 0; 1587 1588 psb_intel_sdvo_connector->force_audio = i; 1589 1590 if (i == 0) 1591 has_audio = psb_intel_sdvo_detect_hdmi_audio(connector); 1592 else 1593 has_audio = i > 0; 1594 1595 if (has_audio == psb_intel_sdvo->has_hdmi_audio) 1596 return 0; 1597 1598 psb_intel_sdvo->has_hdmi_audio = has_audio; 1599 goto done; 1600 } 1601 1602 if (property == dev_priv->broadcast_rgb_property) { 1603 if (val == !!psb_intel_sdvo->color_range) 1604 return 0; 1605 1606 psb_intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; 1607 goto done; 1608 } 1609 1610 #define CHECK_PROPERTY(name, NAME) \ 1611 if (psb_intel_sdvo_connector->name == property) { \ 1612 if (psb_intel_sdvo_connector->cur_##name == temp_value) return 0; \ 1613 if (psb_intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ 1614 cmd = SDVO_CMD_SET_##NAME; \ 1615 psb_intel_sdvo_connector->cur_##name = temp_value; \ 1616 goto set_value; \ 1617 } 1618 1619 if (property == psb_intel_sdvo_connector->tv_format) { 1620 if (val >= ARRAY_SIZE(tv_format_names)) 1621 return -EINVAL; 1622 1623 if (psb_intel_sdvo->tv_format_index == 1624 psb_intel_sdvo_connector->tv_format_supported[val]) 1625 return 0; 1626 1627 psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[val]; 1628 goto done; 1629 } else if (IS_TV_OR_LVDS(psb_intel_sdvo_connector)) { 1630 temp_value = val; 1631 if (psb_intel_sdvo_connector->left == property) { 1632 drm_object_property_set_value(&connector->base, 1633 psb_intel_sdvo_connector->right, val); 1634 if (psb_intel_sdvo_connector->left_margin == temp_value) 1635 return 0; 1636 1637 psb_intel_sdvo_connector->left_margin = temp_value; 1638 psb_intel_sdvo_connector->right_margin = temp_value; 1639 temp_value = psb_intel_sdvo_connector->max_hscan - 1640 psb_intel_sdvo_connector->left_margin; 1641 cmd = SDVO_CMD_SET_OVERSCAN_H; 1642 goto set_value; 1643 } else if (psb_intel_sdvo_connector->right == property) { 1644 drm_object_property_set_value(&connector->base, 1645 psb_intel_sdvo_connector->left, val); 1646 if (psb_intel_sdvo_connector->right_margin == temp_value) 1647 return 0; 1648 1649 psb_intel_sdvo_connector->left_margin = temp_value; 1650 psb_intel_sdvo_connector->right_margin = temp_value; 1651 temp_value = psb_intel_sdvo_connector->max_hscan - 1652 psb_intel_sdvo_connector->left_margin; 1653 cmd = SDVO_CMD_SET_OVERSCAN_H; 1654 goto set_value; 1655 } else if (psb_intel_sdvo_connector->top == property) { 1656 drm_object_property_set_value(&connector->base, 1657 psb_intel_sdvo_connector->bottom, val); 1658 if (psb_intel_sdvo_connector->top_margin == temp_value) 1659 return 0; 1660 1661 psb_intel_sdvo_connector->top_margin = temp_value; 1662 psb_intel_sdvo_connector->bottom_margin = temp_value; 1663 temp_value = psb_intel_sdvo_connector->max_vscan - 1664 psb_intel_sdvo_connector->top_margin; 1665 cmd = SDVO_CMD_SET_OVERSCAN_V; 1666 goto set_value; 1667 } else if (psb_intel_sdvo_connector->bottom == property) { 1668 drm_object_property_set_value(&connector->base, 1669 psb_intel_sdvo_connector->top, val); 1670 if (psb_intel_sdvo_connector->bottom_margin == temp_value) 1671 return 0; 1672 1673 psb_intel_sdvo_connector->top_margin = temp_value; 1674 psb_intel_sdvo_connector->bottom_margin = temp_value; 1675 temp_value = psb_intel_sdvo_connector->max_vscan - 1676 psb_intel_sdvo_connector->top_margin; 1677 cmd = SDVO_CMD_SET_OVERSCAN_V; 1678 goto set_value; 1679 } 1680 CHECK_PROPERTY(hpos, HPOS) 1681 CHECK_PROPERTY(vpos, VPOS) 1682 CHECK_PROPERTY(saturation, SATURATION) 1683 CHECK_PROPERTY(contrast, CONTRAST) 1684 CHECK_PROPERTY(hue, HUE) 1685 CHECK_PROPERTY(brightness, BRIGHTNESS) 1686 CHECK_PROPERTY(sharpness, SHARPNESS) 1687 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) 1688 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) 1689 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) 1690 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) 1691 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) 1692 CHECK_PROPERTY(dot_crawl, DOT_CRAWL) 1693 } 1694 1695 return -EINVAL; /* unknown property */ 1696 1697 set_value: 1698 if (!psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &temp_value, 2)) 1699 return -EIO; 1700 1701 1702 done: 1703 if (psb_intel_sdvo->base.base.crtc) { 1704 struct drm_crtc *crtc = psb_intel_sdvo->base.base.crtc; 1705 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, 1706 crtc->y, crtc->primary->fb); 1707 } 1708 1709 return 0; 1710 #undef CHECK_PROPERTY 1711 } 1712 1713 static void psb_intel_sdvo_save(struct drm_connector *connector) 1714 { 1715 struct drm_device *dev = connector->dev; 1716 struct gma_encoder *gma_encoder = gma_attached_encoder(connector); 1717 struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(&gma_encoder->base); 1718 1719 sdvo->saveSDVO = REG_READ(sdvo->sdvo_reg); 1720 } 1721 1722 static void psb_intel_sdvo_restore(struct drm_connector *connector) 1723 { 1724 struct drm_device *dev = connector->dev; 1725 struct drm_encoder *encoder = &gma_attached_encoder(connector)->base; 1726 struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(encoder); 1727 struct drm_crtc *crtc = encoder->crtc; 1728 1729 REG_WRITE(sdvo->sdvo_reg, sdvo->saveSDVO); 1730 1731 /* Force a full mode set on the crtc. We're supposed to have the 1732 mode_config lock already. */ 1733 if (connector->status == connector_status_connected) 1734 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, 1735 NULL); 1736 } 1737 1738 static const struct drm_encoder_helper_funcs psb_intel_sdvo_helper_funcs = { 1739 .dpms = psb_intel_sdvo_dpms, 1740 .mode_fixup = psb_intel_sdvo_mode_fixup, 1741 .prepare = gma_encoder_prepare, 1742 .mode_set = psb_intel_sdvo_mode_set, 1743 .commit = gma_encoder_commit, 1744 }; 1745 1746 static const struct drm_connector_funcs psb_intel_sdvo_connector_funcs = { 1747 .dpms = drm_helper_connector_dpms, 1748 .detect = psb_intel_sdvo_detect, 1749 .fill_modes = drm_helper_probe_single_connector_modes, 1750 .set_property = psb_intel_sdvo_set_property, 1751 .destroy = psb_intel_sdvo_destroy, 1752 }; 1753 1754 static const struct drm_connector_helper_funcs psb_intel_sdvo_connector_helper_funcs = { 1755 .get_modes = psb_intel_sdvo_get_modes, 1756 .mode_valid = psb_intel_sdvo_mode_valid, 1757 .best_encoder = gma_best_encoder, 1758 }; 1759 1760 static void psb_intel_sdvo_enc_destroy(struct drm_encoder *encoder) 1761 { 1762 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder); 1763 1764 if (psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL) 1765 drm_mode_destroy(encoder->dev, 1766 psb_intel_sdvo->sdvo_lvds_fixed_mode); 1767 1768 i2c_del_adapter(&psb_intel_sdvo->ddc); 1769 gma_encoder_destroy(encoder); 1770 } 1771 1772 static const struct drm_encoder_funcs psb_intel_sdvo_enc_funcs = { 1773 .destroy = psb_intel_sdvo_enc_destroy, 1774 }; 1775 1776 static void 1777 psb_intel_sdvo_guess_ddc_bus(struct psb_intel_sdvo *sdvo) 1778 { 1779 /* FIXME: At the moment, ddc_bus = 2 is the only thing that works. 1780 * We need to figure out if this is true for all available poulsbo 1781 * hardware, or if we need to fiddle with the guessing code above. 1782 * The problem might go away if we can parse sdvo mappings from bios */ 1783 sdvo->ddc_bus = 2; 1784 1785 #if 0 1786 uint16_t mask = 0; 1787 unsigned int num_bits; 1788 1789 /* Make a mask of outputs less than or equal to our own priority in the 1790 * list. 1791 */ 1792 switch (sdvo->controlled_output) { 1793 case SDVO_OUTPUT_LVDS1: 1794 mask |= SDVO_OUTPUT_LVDS1; 1795 case SDVO_OUTPUT_LVDS0: 1796 mask |= SDVO_OUTPUT_LVDS0; 1797 case SDVO_OUTPUT_TMDS1: 1798 mask |= SDVO_OUTPUT_TMDS1; 1799 case SDVO_OUTPUT_TMDS0: 1800 mask |= SDVO_OUTPUT_TMDS0; 1801 case SDVO_OUTPUT_RGB1: 1802 mask |= SDVO_OUTPUT_RGB1; 1803 case SDVO_OUTPUT_RGB0: 1804 mask |= SDVO_OUTPUT_RGB0; 1805 break; 1806 } 1807 1808 /* Count bits to find what number we are in the priority list. */ 1809 mask &= sdvo->caps.output_flags; 1810 num_bits = hweight16(mask); 1811 /* If more than 3 outputs, default to DDC bus 3 for now. */ 1812 if (num_bits > 3) 1813 num_bits = 3; 1814 1815 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 1816 sdvo->ddc_bus = 1 << num_bits; 1817 #endif 1818 } 1819 1820 /** 1821 * Choose the appropriate DDC bus for control bus switch command for this 1822 * SDVO output based on the controlled output. 1823 * 1824 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 1825 * outputs, then LVDS outputs. 1826 */ 1827 static void 1828 psb_intel_sdvo_select_ddc_bus(struct drm_psb_private *dev_priv, 1829 struct psb_intel_sdvo *sdvo, u32 reg) 1830 { 1831 struct sdvo_device_mapping *mapping; 1832 1833 if (IS_SDVOB(reg)) 1834 mapping = &(dev_priv->sdvo_mappings[0]); 1835 else 1836 mapping = &(dev_priv->sdvo_mappings[1]); 1837 1838 if (mapping->initialized) 1839 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 1840 else 1841 psb_intel_sdvo_guess_ddc_bus(sdvo); 1842 } 1843 1844 static void 1845 psb_intel_sdvo_select_i2c_bus(struct drm_psb_private *dev_priv, 1846 struct psb_intel_sdvo *sdvo, u32 reg) 1847 { 1848 struct sdvo_device_mapping *mapping; 1849 u8 pin, speed; 1850 1851 if (IS_SDVOB(reg)) 1852 mapping = &dev_priv->sdvo_mappings[0]; 1853 else 1854 mapping = &dev_priv->sdvo_mappings[1]; 1855 1856 pin = GMBUS_PORT_DPB; 1857 speed = GMBUS_RATE_1MHZ >> 8; 1858 if (mapping->initialized) { 1859 pin = mapping->i2c_pin; 1860 speed = mapping->i2c_speed; 1861 } 1862 1863 if (pin < GMBUS_NUM_PORTS) { 1864 sdvo->i2c = &dev_priv->gmbus[pin].adapter; 1865 gma_intel_gmbus_set_speed(sdvo->i2c, speed); 1866 gma_intel_gmbus_force_bit(sdvo->i2c, true); 1867 } else 1868 sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter; 1869 } 1870 1871 static bool 1872 psb_intel_sdvo_is_hdmi_connector(struct psb_intel_sdvo *psb_intel_sdvo, int device) 1873 { 1874 return psb_intel_sdvo_check_supp_encode(psb_intel_sdvo); 1875 } 1876 1877 static u8 1878 psb_intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg) 1879 { 1880 struct drm_psb_private *dev_priv = dev->dev_private; 1881 struct sdvo_device_mapping *my_mapping, *other_mapping; 1882 1883 if (IS_SDVOB(sdvo_reg)) { 1884 my_mapping = &dev_priv->sdvo_mappings[0]; 1885 other_mapping = &dev_priv->sdvo_mappings[1]; 1886 } else { 1887 my_mapping = &dev_priv->sdvo_mappings[1]; 1888 other_mapping = &dev_priv->sdvo_mappings[0]; 1889 } 1890 1891 /* If the BIOS described our SDVO device, take advantage of it. */ 1892 if (my_mapping->slave_addr) 1893 return my_mapping->slave_addr; 1894 1895 /* If the BIOS only described a different SDVO device, use the 1896 * address that it isn't using. 1897 */ 1898 if (other_mapping->slave_addr) { 1899 if (other_mapping->slave_addr == 0x70) 1900 return 0x72; 1901 else 1902 return 0x70; 1903 } 1904 1905 /* No SDVO device info is found for another DVO port, 1906 * so use mapping assumption we had before BIOS parsing. 1907 */ 1908 if (IS_SDVOB(sdvo_reg)) 1909 return 0x70; 1910 else 1911 return 0x72; 1912 } 1913 1914 static void 1915 psb_intel_sdvo_connector_init(struct psb_intel_sdvo_connector *connector, 1916 struct psb_intel_sdvo *encoder) 1917 { 1918 drm_connector_init(encoder->base.base.dev, 1919 &connector->base.base, 1920 &psb_intel_sdvo_connector_funcs, 1921 connector->base.base.connector_type); 1922 1923 drm_connector_helper_add(&connector->base.base, 1924 &psb_intel_sdvo_connector_helper_funcs); 1925 1926 connector->base.base.interlace_allowed = 0; 1927 connector->base.base.doublescan_allowed = 0; 1928 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 1929 1930 connector->base.save = psb_intel_sdvo_save; 1931 connector->base.restore = psb_intel_sdvo_restore; 1932 1933 gma_connector_attach_encoder(&connector->base, &encoder->base); 1934 drm_connector_register(&connector->base.base); 1935 } 1936 1937 static void 1938 psb_intel_sdvo_add_hdmi_properties(struct psb_intel_sdvo_connector *connector) 1939 { 1940 /* FIXME: We don't support HDMI at the moment 1941 struct drm_device *dev = connector->base.base.dev; 1942 1943 intel_attach_force_audio_property(&connector->base.base); 1944 intel_attach_broadcast_rgb_property(&connector->base.base); 1945 */ 1946 } 1947 1948 static bool 1949 psb_intel_sdvo_dvi_init(struct psb_intel_sdvo *psb_intel_sdvo, int device) 1950 { 1951 struct drm_encoder *encoder = &psb_intel_sdvo->base.base; 1952 struct drm_connector *connector; 1953 struct gma_connector *intel_connector; 1954 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector; 1955 1956 psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL); 1957 if (!psb_intel_sdvo_connector) 1958 return false; 1959 1960 if (device == 0) { 1961 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; 1962 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 1963 } else if (device == 1) { 1964 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; 1965 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 1966 } 1967 1968 intel_connector = &psb_intel_sdvo_connector->base; 1969 connector = &intel_connector->base; 1970 // connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 1971 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 1972 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 1973 1974 if (psb_intel_sdvo_is_hdmi_connector(psb_intel_sdvo, device)) { 1975 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 1976 psb_intel_sdvo->is_hdmi = true; 1977 } 1978 psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 1979 (1 << INTEL_ANALOG_CLONE_BIT)); 1980 1981 psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo); 1982 if (psb_intel_sdvo->is_hdmi) 1983 psb_intel_sdvo_add_hdmi_properties(psb_intel_sdvo_connector); 1984 1985 return true; 1986 } 1987 1988 static bool 1989 psb_intel_sdvo_tv_init(struct psb_intel_sdvo *psb_intel_sdvo, int type) 1990 { 1991 struct drm_encoder *encoder = &psb_intel_sdvo->base.base; 1992 struct drm_connector *connector; 1993 struct gma_connector *intel_connector; 1994 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector; 1995 1996 psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL); 1997 if (!psb_intel_sdvo_connector) 1998 return false; 1999 2000 intel_connector = &psb_intel_sdvo_connector->base; 2001 connector = &intel_connector->base; 2002 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2003 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2004 2005 psb_intel_sdvo->controlled_output |= type; 2006 psb_intel_sdvo_connector->output_flag = type; 2007 2008 psb_intel_sdvo->is_tv = true; 2009 psb_intel_sdvo->base.needs_tv_clock = true; 2010 psb_intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; 2011 2012 psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo); 2013 2014 if (!psb_intel_sdvo_tv_create_property(psb_intel_sdvo, psb_intel_sdvo_connector, type)) 2015 goto err; 2016 2017 if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector)) 2018 goto err; 2019 2020 return true; 2021 2022 err: 2023 psb_intel_sdvo_destroy(connector); 2024 return false; 2025 } 2026 2027 static bool 2028 psb_intel_sdvo_analog_init(struct psb_intel_sdvo *psb_intel_sdvo, int device) 2029 { 2030 struct drm_encoder *encoder = &psb_intel_sdvo->base.base; 2031 struct drm_connector *connector; 2032 struct gma_connector *intel_connector; 2033 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector; 2034 2035 psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL); 2036 if (!psb_intel_sdvo_connector) 2037 return false; 2038 2039 intel_connector = &psb_intel_sdvo_connector->base; 2040 connector = &intel_connector->base; 2041 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2042 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2043 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2044 2045 if (device == 0) { 2046 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; 2047 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2048 } else if (device == 1) { 2049 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; 2050 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2051 } 2052 2053 psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 2054 (1 << INTEL_ANALOG_CLONE_BIT)); 2055 2056 psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, 2057 psb_intel_sdvo); 2058 return true; 2059 } 2060 2061 static bool 2062 psb_intel_sdvo_lvds_init(struct psb_intel_sdvo *psb_intel_sdvo, int device) 2063 { 2064 struct drm_encoder *encoder = &psb_intel_sdvo->base.base; 2065 struct drm_connector *connector; 2066 struct gma_connector *intel_connector; 2067 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector; 2068 2069 psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL); 2070 if (!psb_intel_sdvo_connector) 2071 return false; 2072 2073 intel_connector = &psb_intel_sdvo_connector->base; 2074 connector = &intel_connector->base; 2075 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2076 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2077 2078 if (device == 0) { 2079 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; 2080 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2081 } else if (device == 1) { 2082 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2083 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2084 } 2085 2086 psb_intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) | 2087 (1 << INTEL_SDVO_LVDS_CLONE_BIT)); 2088 2089 psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo); 2090 if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector)) 2091 goto err; 2092 2093 return true; 2094 2095 err: 2096 psb_intel_sdvo_destroy(connector); 2097 return false; 2098 } 2099 2100 static bool 2101 psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags) 2102 { 2103 psb_intel_sdvo->is_tv = false; 2104 psb_intel_sdvo->base.needs_tv_clock = false; 2105 psb_intel_sdvo->is_lvds = false; 2106 2107 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2108 2109 if (flags & SDVO_OUTPUT_TMDS0) 2110 if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 0)) 2111 return false; 2112 2113 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2114 if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 1)) 2115 return false; 2116 2117 /* TV has no XXX1 function block */ 2118 if (flags & SDVO_OUTPUT_SVID0) 2119 if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_SVID0)) 2120 return false; 2121 2122 if (flags & SDVO_OUTPUT_CVBS0) 2123 if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_CVBS0)) 2124 return false; 2125 2126 if (flags & SDVO_OUTPUT_RGB0) 2127 if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 0)) 2128 return false; 2129 2130 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2131 if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 1)) 2132 return false; 2133 2134 if (flags & SDVO_OUTPUT_LVDS0) 2135 if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 0)) 2136 return false; 2137 2138 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2139 if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 1)) 2140 return false; 2141 2142 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2143 unsigned char bytes[2]; 2144 2145 psb_intel_sdvo->controlled_output = 0; 2146 memcpy(bytes, &psb_intel_sdvo->caps.output_flags, 2); 2147 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2148 SDVO_NAME(psb_intel_sdvo), 2149 bytes[0], bytes[1]); 2150 return false; 2151 } 2152 psb_intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1); 2153 2154 return true; 2155 } 2156 2157 static bool psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo, 2158 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector, 2159 int type) 2160 { 2161 struct drm_device *dev = psb_intel_sdvo->base.base.dev; 2162 struct psb_intel_sdvo_tv_format format; 2163 uint32_t format_map, i; 2164 2165 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, type)) 2166 return false; 2167 2168 BUILD_BUG_ON(sizeof(format) != 6); 2169 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, 2170 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2171 &format, sizeof(format))) 2172 return false; 2173 2174 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 2175 2176 if (format_map == 0) 2177 return false; 2178 2179 psb_intel_sdvo_connector->format_supported_num = 0; 2180 for (i = 0 ; i < ARRAY_SIZE(tv_format_names); i++) 2181 if (format_map & (1 << i)) 2182 psb_intel_sdvo_connector->tv_format_supported[psb_intel_sdvo_connector->format_supported_num++] = i; 2183 2184 2185 psb_intel_sdvo_connector->tv_format = 2186 drm_property_create(dev, DRM_MODE_PROP_ENUM, 2187 "mode", psb_intel_sdvo_connector->format_supported_num); 2188 if (!psb_intel_sdvo_connector->tv_format) 2189 return false; 2190 2191 for (i = 0; i < psb_intel_sdvo_connector->format_supported_num; i++) 2192 drm_property_add_enum( 2193 psb_intel_sdvo_connector->tv_format, 2194 i, tv_format_names[psb_intel_sdvo_connector->tv_format_supported[i]]); 2195 2196 psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[0]; 2197 drm_object_attach_property(&psb_intel_sdvo_connector->base.base.base, 2198 psb_intel_sdvo_connector->tv_format, 0); 2199 return true; 2200 2201 } 2202 2203 #define ENHANCEMENT(name, NAME) do { \ 2204 if (enhancements.name) { \ 2205 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 2206 !psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 2207 return false; \ 2208 psb_intel_sdvo_connector->max_##name = data_value[0]; \ 2209 psb_intel_sdvo_connector->cur_##name = response; \ 2210 psb_intel_sdvo_connector->name = \ 2211 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 2212 if (!psb_intel_sdvo_connector->name) return false; \ 2213 drm_object_attach_property(&connector->base, \ 2214 psb_intel_sdvo_connector->name, \ 2215 psb_intel_sdvo_connector->cur_##name); \ 2216 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 2217 data_value[0], data_value[1], response); \ 2218 } \ 2219 } while(0) 2220 2221 static bool 2222 psb_intel_sdvo_create_enhance_property_tv(struct psb_intel_sdvo *psb_intel_sdvo, 2223 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector, 2224 struct psb_intel_sdvo_enhancements_reply enhancements) 2225 { 2226 struct drm_device *dev = psb_intel_sdvo->base.base.dev; 2227 struct drm_connector *connector = &psb_intel_sdvo_connector->base.base; 2228 uint16_t response, data_value[2]; 2229 2230 /* when horizontal overscan is supported, Add the left/right property */ 2231 if (enhancements.overscan_h) { 2232 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, 2233 SDVO_CMD_GET_MAX_OVERSCAN_H, 2234 &data_value, 4)) 2235 return false; 2236 2237 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, 2238 SDVO_CMD_GET_OVERSCAN_H, 2239 &response, 2)) 2240 return false; 2241 2242 psb_intel_sdvo_connector->max_hscan = data_value[0]; 2243 psb_intel_sdvo_connector->left_margin = data_value[0] - response; 2244 psb_intel_sdvo_connector->right_margin = psb_intel_sdvo_connector->left_margin; 2245 psb_intel_sdvo_connector->left = 2246 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 2247 if (!psb_intel_sdvo_connector->left) 2248 return false; 2249 2250 drm_object_attach_property(&connector->base, 2251 psb_intel_sdvo_connector->left, 2252 psb_intel_sdvo_connector->left_margin); 2253 2254 psb_intel_sdvo_connector->right = 2255 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 2256 if (!psb_intel_sdvo_connector->right) 2257 return false; 2258 2259 drm_object_attach_property(&connector->base, 2260 psb_intel_sdvo_connector->right, 2261 psb_intel_sdvo_connector->right_margin); 2262 DRM_DEBUG_KMS("h_overscan: max %d, " 2263 "default %d, current %d\n", 2264 data_value[0], data_value[1], response); 2265 } 2266 2267 if (enhancements.overscan_v) { 2268 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, 2269 SDVO_CMD_GET_MAX_OVERSCAN_V, 2270 &data_value, 4)) 2271 return false; 2272 2273 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, 2274 SDVO_CMD_GET_OVERSCAN_V, 2275 &response, 2)) 2276 return false; 2277 2278 psb_intel_sdvo_connector->max_vscan = data_value[0]; 2279 psb_intel_sdvo_connector->top_margin = data_value[0] - response; 2280 psb_intel_sdvo_connector->bottom_margin = psb_intel_sdvo_connector->top_margin; 2281 psb_intel_sdvo_connector->top = 2282 drm_property_create_range(dev, 0, "top_margin", 0, data_value[0]); 2283 if (!psb_intel_sdvo_connector->top) 2284 return false; 2285 2286 drm_object_attach_property(&connector->base, 2287 psb_intel_sdvo_connector->top, 2288 psb_intel_sdvo_connector->top_margin); 2289 2290 psb_intel_sdvo_connector->bottom = 2291 drm_property_create_range(dev, 0, "bottom_margin", 0, data_value[0]); 2292 if (!psb_intel_sdvo_connector->bottom) 2293 return false; 2294 2295 drm_object_attach_property(&connector->base, 2296 psb_intel_sdvo_connector->bottom, 2297 psb_intel_sdvo_connector->bottom_margin); 2298 DRM_DEBUG_KMS("v_overscan: max %d, " 2299 "default %d, current %d\n", 2300 data_value[0], data_value[1], response); 2301 } 2302 2303 ENHANCEMENT(hpos, HPOS); 2304 ENHANCEMENT(vpos, VPOS); 2305 ENHANCEMENT(saturation, SATURATION); 2306 ENHANCEMENT(contrast, CONTRAST); 2307 ENHANCEMENT(hue, HUE); 2308 ENHANCEMENT(sharpness, SHARPNESS); 2309 ENHANCEMENT(brightness, BRIGHTNESS); 2310 ENHANCEMENT(flicker_filter, FLICKER_FILTER); 2311 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 2312 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); 2313 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); 2314 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); 2315 2316 if (enhancements.dot_crawl) { 2317 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 2318 return false; 2319 2320 psb_intel_sdvo_connector->max_dot_crawl = 1; 2321 psb_intel_sdvo_connector->cur_dot_crawl = response & 0x1; 2322 psb_intel_sdvo_connector->dot_crawl = 2323 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 2324 if (!psb_intel_sdvo_connector->dot_crawl) 2325 return false; 2326 2327 drm_object_attach_property(&connector->base, 2328 psb_intel_sdvo_connector->dot_crawl, 2329 psb_intel_sdvo_connector->cur_dot_crawl); 2330 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 2331 } 2332 2333 return true; 2334 } 2335 2336 static bool 2337 psb_intel_sdvo_create_enhance_property_lvds(struct psb_intel_sdvo *psb_intel_sdvo, 2338 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector, 2339 struct psb_intel_sdvo_enhancements_reply enhancements) 2340 { 2341 struct drm_device *dev = psb_intel_sdvo->base.base.dev; 2342 struct drm_connector *connector = &psb_intel_sdvo_connector->base.base; 2343 uint16_t response, data_value[2]; 2344 2345 ENHANCEMENT(brightness, BRIGHTNESS); 2346 2347 return true; 2348 } 2349 #undef ENHANCEMENT 2350 2351 static bool psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo, 2352 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector) 2353 { 2354 union { 2355 struct psb_intel_sdvo_enhancements_reply reply; 2356 uint16_t response; 2357 } enhancements; 2358 2359 BUILD_BUG_ON(sizeof(enhancements) != 2); 2360 2361 enhancements.response = 0; 2362 psb_intel_sdvo_get_value(psb_intel_sdvo, 2363 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2364 &enhancements, sizeof(enhancements)); 2365 if (enhancements.response == 0) { 2366 DRM_DEBUG_KMS("No enhancement is supported\n"); 2367 return true; 2368 } 2369 2370 if (IS_TV(psb_intel_sdvo_connector)) 2371 return psb_intel_sdvo_create_enhance_property_tv(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply); 2372 else if(IS_LVDS(psb_intel_sdvo_connector)) 2373 return psb_intel_sdvo_create_enhance_property_lvds(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply); 2374 else 2375 return true; 2376 } 2377 2378 static int psb_intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 2379 struct i2c_msg *msgs, 2380 int num) 2381 { 2382 struct psb_intel_sdvo *sdvo = adapter->algo_data; 2383 2384 if (!psb_intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 2385 return -EIO; 2386 2387 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 2388 } 2389 2390 static u32 psb_intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 2391 { 2392 struct psb_intel_sdvo *sdvo = adapter->algo_data; 2393 return sdvo->i2c->algo->functionality(sdvo->i2c); 2394 } 2395 2396 static const struct i2c_algorithm psb_intel_sdvo_ddc_proxy = { 2397 .master_xfer = psb_intel_sdvo_ddc_proxy_xfer, 2398 .functionality = psb_intel_sdvo_ddc_proxy_func 2399 }; 2400 2401 static bool 2402 psb_intel_sdvo_init_ddc_proxy(struct psb_intel_sdvo *sdvo, 2403 struct drm_device *dev) 2404 { 2405 sdvo->ddc.owner = THIS_MODULE; 2406 sdvo->ddc.class = I2C_CLASS_DDC; 2407 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); 2408 sdvo->ddc.dev.parent = &dev->pdev->dev; 2409 sdvo->ddc.algo_data = sdvo; 2410 sdvo->ddc.algo = &psb_intel_sdvo_ddc_proxy; 2411 2412 return i2c_add_adapter(&sdvo->ddc) == 0; 2413 } 2414 2415 bool psb_intel_sdvo_init(struct drm_device *dev, int sdvo_reg) 2416 { 2417 struct drm_psb_private *dev_priv = dev->dev_private; 2418 struct gma_encoder *gma_encoder; 2419 struct psb_intel_sdvo *psb_intel_sdvo; 2420 int i; 2421 2422 psb_intel_sdvo = kzalloc(sizeof(struct psb_intel_sdvo), GFP_KERNEL); 2423 if (!psb_intel_sdvo) 2424 return false; 2425 2426 psb_intel_sdvo->sdvo_reg = sdvo_reg; 2427 psb_intel_sdvo->slave_addr = psb_intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1; 2428 psb_intel_sdvo_select_i2c_bus(dev_priv, psb_intel_sdvo, sdvo_reg); 2429 if (!psb_intel_sdvo_init_ddc_proxy(psb_intel_sdvo, dev)) { 2430 kfree(psb_intel_sdvo); 2431 return false; 2432 } 2433 2434 /* encoder type will be decided later */ 2435 gma_encoder = &psb_intel_sdvo->base; 2436 gma_encoder->type = INTEL_OUTPUT_SDVO; 2437 drm_encoder_init(dev, &gma_encoder->base, &psb_intel_sdvo_enc_funcs, 2438 0, NULL); 2439 2440 /* Read the regs to test if we can talk to the device */ 2441 for (i = 0; i < 0x40; i++) { 2442 u8 byte; 2443 2444 if (!psb_intel_sdvo_read_byte(psb_intel_sdvo, i, &byte)) { 2445 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", 2446 IS_SDVOB(sdvo_reg) ? 'B' : 'C'); 2447 goto err; 2448 } 2449 } 2450 2451 if (IS_SDVOB(sdvo_reg)) 2452 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS; 2453 else 2454 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; 2455 2456 drm_encoder_helper_add(&gma_encoder->base, &psb_intel_sdvo_helper_funcs); 2457 2458 /* In default case sdvo lvds is false */ 2459 if (!psb_intel_sdvo_get_capabilities(psb_intel_sdvo, &psb_intel_sdvo->caps)) 2460 goto err; 2461 2462 if (psb_intel_sdvo_output_setup(psb_intel_sdvo, 2463 psb_intel_sdvo->caps.output_flags) != true) { 2464 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", 2465 IS_SDVOB(sdvo_reg) ? 'B' : 'C'); 2466 goto err; 2467 } 2468 2469 psb_intel_sdvo_select_ddc_bus(dev_priv, psb_intel_sdvo, sdvo_reg); 2470 2471 /* Set the input timing to the screen. Assume always input 0. */ 2472 if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo)) 2473 goto err; 2474 2475 if (!psb_intel_sdvo_get_input_pixel_clock_range(psb_intel_sdvo, 2476 &psb_intel_sdvo->pixel_clock_min, 2477 &psb_intel_sdvo->pixel_clock_max)) 2478 goto err; 2479 2480 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 2481 "clock range %dMHz - %dMHz, " 2482 "input 1: %c, input 2: %c, " 2483 "output 1: %c, output 2: %c\n", 2484 SDVO_NAME(psb_intel_sdvo), 2485 psb_intel_sdvo->caps.vendor_id, psb_intel_sdvo->caps.device_id, 2486 psb_intel_sdvo->caps.device_rev_id, 2487 psb_intel_sdvo->pixel_clock_min / 1000, 2488 psb_intel_sdvo->pixel_clock_max / 1000, 2489 (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 2490 (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 2491 /* check currently supported outputs */ 2492 psb_intel_sdvo->caps.output_flags & 2493 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 2494 psb_intel_sdvo->caps.output_flags & 2495 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 2496 return true; 2497 2498 err: 2499 drm_encoder_cleanup(&gma_encoder->base); 2500 i2c_del_adapter(&psb_intel_sdvo->ddc); 2501 kfree(psb_intel_sdvo); 2502 2503 return false; 2504 } 2505