1 /* 2 * Copyright (c) 2009, Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, write to the Free Software Foundation, Inc., 15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 */ 17 #ifndef __PSB_INTEL_REG_H__ 18 #define __PSB_INTEL_REG_H__ 19 20 /* 21 * GPIO regs 22 */ 23 #define GPIOA 0x5010 24 #define GPIOB 0x5014 25 #define GPIOC 0x5018 26 #define GPIOD 0x501c 27 #define GPIOE 0x5020 28 #define GPIOF 0x5024 29 #define GPIOG 0x5028 30 #define GPIOH 0x502c 31 # define GPIO_CLOCK_DIR_MASK (1 << 0) 32 # define GPIO_CLOCK_DIR_IN (0 << 1) 33 # define GPIO_CLOCK_DIR_OUT (1 << 1) 34 # define GPIO_CLOCK_VAL_MASK (1 << 2) 35 # define GPIO_CLOCK_VAL_OUT (1 << 3) 36 # define GPIO_CLOCK_VAL_IN (1 << 4) 37 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 38 # define GPIO_DATA_DIR_MASK (1 << 8) 39 # define GPIO_DATA_DIR_IN (0 << 9) 40 # define GPIO_DATA_DIR_OUT (1 << 9) 41 # define GPIO_DATA_VAL_MASK (1 << 10) 42 # define GPIO_DATA_VAL_OUT (1 << 11) 43 # define GPIO_DATA_VAL_IN (1 << 12) 44 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 45 46 #define GMBUS0 0x5100 /* clock/port select */ 47 #define GMBUS_RATE_100KHZ (0<<8) 48 #define GMBUS_RATE_50KHZ (1<<8) 49 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 50 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 51 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 52 #define GMBUS_PORT_DISABLED 0 53 #define GMBUS_PORT_SSC 1 54 #define GMBUS_PORT_VGADDC 2 55 #define GMBUS_PORT_PANEL 3 56 #define GMBUS_PORT_DPC 4 /* HDMIC */ 57 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ 58 /* 6 reserved */ 59 #define GMBUS_PORT_DPD 7 /* HDMID */ 60 #define GMBUS_NUM_PORTS 8 61 #define GMBUS1 0x5104 /* command/status */ 62 #define GMBUS_SW_CLR_INT (1<<31) 63 #define GMBUS_SW_RDY (1<<30) 64 #define GMBUS_ENT (1<<29) /* enable timeout */ 65 #define GMBUS_CYCLE_NONE (0<<25) 66 #define GMBUS_CYCLE_WAIT (1<<25) 67 #define GMBUS_CYCLE_INDEX (2<<25) 68 #define GMBUS_CYCLE_STOP (4<<25) 69 #define GMBUS_BYTE_COUNT_SHIFT 16 70 #define GMBUS_SLAVE_INDEX_SHIFT 8 71 #define GMBUS_SLAVE_ADDR_SHIFT 1 72 #define GMBUS_SLAVE_READ (1<<0) 73 #define GMBUS_SLAVE_WRITE (0<<0) 74 #define GMBUS2 0x5108 /* status */ 75 #define GMBUS_INUSE (1<<15) 76 #define GMBUS_HW_WAIT_PHASE (1<<14) 77 #define GMBUS_STALL_TIMEOUT (1<<13) 78 #define GMBUS_INT (1<<12) 79 #define GMBUS_HW_RDY (1<<11) 80 #define GMBUS_SATOER (1<<10) 81 #define GMBUS_ACTIVE (1<<9) 82 #define GMBUS3 0x510c /* data buffer bytes 3-0 */ 83 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ 84 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 85 #define GMBUS_NAK_EN (1<<3) 86 #define GMBUS_IDLE_EN (1<<2) 87 #define GMBUS_HW_WAIT_EN (1<<1) 88 #define GMBUS_HW_RDY_EN (1<<0) 89 #define GMBUS5 0x5120 /* byte index */ 90 #define GMBUS_2BYTE_INDEX_EN (1<<31) 91 92 #define BLC_PWM_CTL 0x61254 93 #define BLC_PWM_CTL2 0x61250 94 #define PWM_ENABLE (1 << 31) 95 #define PWM_LEGACY_MODE (1 << 30) 96 #define PWM_PIPE_B (1 << 29) 97 #define BLC_PWM_CTL_C 0x62254 98 #define BLC_PWM_CTL2_C 0x62250 99 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 100 /* 101 * This is the most significant 15 bits of the number of backlight cycles in a 102 * complete cycle of the modulated backlight control. 103 * 104 * The actual value is this field multiplied by two. 105 */ 106 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 107 #define BLM_LEGACY_MODE (1 << 16) 108 /* 109 * This is the number of cycles out of the backlight modulation cycle for which 110 * the backlight is on. 111 * 112 * This field must be no greater than the number of cycles in the complete 113 * backlight modulation cycle. 114 */ 115 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 116 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 117 118 #define I915_GCFGC 0xf0 119 #define I915_LOW_FREQUENCY_ENABLE (1 << 7) 120 #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 121 #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4) 122 #define I915_DISPLAY_CLOCK_MASK (7 << 4) 123 124 #define I855_HPLLCC 0xc0 125 #define I855_CLOCK_CONTROL_MASK (3 << 0) 126 #define I855_CLOCK_133_200 (0 << 0) 127 #define I855_CLOCK_100_200 (1 << 0) 128 #define I855_CLOCK_100_133 (2 << 0) 129 #define I855_CLOCK_166_250 (3 << 0) 130 131 /* I830 CRTC registers */ 132 #define HTOTAL_A 0x60000 133 #define HBLANK_A 0x60004 134 #define HSYNC_A 0x60008 135 #define VTOTAL_A 0x6000c 136 #define VBLANK_A 0x60010 137 #define VSYNC_A 0x60014 138 #define PIPEASRC 0x6001c 139 #define BCLRPAT_A 0x60020 140 #define VSYNCSHIFT_A 0x60028 141 142 #define HTOTAL_B 0x61000 143 #define HBLANK_B 0x61004 144 #define HSYNC_B 0x61008 145 #define VTOTAL_B 0x6100c 146 #define VBLANK_B 0x61010 147 #define VSYNC_B 0x61014 148 #define PIPEBSRC 0x6101c 149 #define BCLRPAT_B 0x61020 150 #define VSYNCSHIFT_B 0x61028 151 152 #define HTOTAL_C 0x62000 153 #define HBLANK_C 0x62004 154 #define HSYNC_C 0x62008 155 #define VTOTAL_C 0x6200c 156 #define VBLANK_C 0x62010 157 #define VSYNC_C 0x62014 158 #define PIPECSRC 0x6201c 159 #define BCLRPAT_C 0x62020 160 #define VSYNCSHIFT_C 0x62028 161 162 #define PP_STATUS 0x61200 163 # define PP_ON (1 << 31) 164 /* 165 * Indicates that all dependencies of the panel are on: 166 * 167 * - PLL enabled 168 * - pipe enabled 169 * - LVDS/DVOB/DVOC on 170 */ 171 #define PP_READY (1 << 30) 172 #define PP_SEQUENCE_NONE (0 << 28) 173 #define PP_SEQUENCE_ON (1 << 28) 174 #define PP_SEQUENCE_OFF (2 << 28) 175 #define PP_SEQUENCE_MASK 0x30000000 176 #define PP_CONTROL 0x61204 177 #define POWER_TARGET_ON (1 << 0) 178 179 #define LVDSPP_ON 0x61208 180 #define LVDSPP_OFF 0x6120c 181 #define PP_CYCLE 0x61210 182 183 #define PP_ON_DELAYS 0x61208 /* Cedartrail */ 184 #define PP_OFF_DELAYS 0x6120c /* Cedartrail */ 185 186 #define PFIT_CONTROL 0x61230 187 #define PFIT_ENABLE (1 << 31) 188 #define PFIT_PIPE_MASK (3 << 29) 189 #define PFIT_PIPE_SHIFT 29 190 #define PFIT_SCALING_MODE_PILLARBOX (1 << 27) 191 #define PFIT_SCALING_MODE_LETTERBOX (3 << 26) 192 #define VERT_INTERP_DISABLE (0 << 10) 193 #define VERT_INTERP_BILINEAR (1 << 10) 194 #define VERT_INTERP_MASK (3 << 10) 195 #define VERT_AUTO_SCALE (1 << 9) 196 #define HORIZ_INTERP_DISABLE (0 << 6) 197 #define HORIZ_INTERP_BILINEAR (1 << 6) 198 #define HORIZ_INTERP_MASK (3 << 6) 199 #define HORIZ_AUTO_SCALE (1 << 5) 200 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 201 202 #define PFIT_PGM_RATIOS 0x61234 203 #define PFIT_VERT_SCALE_MASK 0xfff00000 204 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 205 206 #define PFIT_AUTO_RATIOS 0x61238 207 208 #define DPLL_A 0x06014 209 #define DPLL_B 0x06018 210 #define DPLL_VCO_ENABLE (1 << 31) 211 #define DPLL_DVO_HIGH_SPEED (1 << 30) 212 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 213 #define DPLL_VGA_MODE_DIS (1 << 28) 214 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 215 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 216 #define DPLL_MODE_MASK (3 << 26) 217 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 218 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 219 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 220 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 221 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 222 #define DPLL_FPA0h1_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 223 #define DPLL_LOCK (1 << 15) /* CDV */ 224 225 /* 226 * The i830 generation, in DAC/serial mode, defines p1 as two plus this 227 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. 228 */ 229 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 230 /* 231 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 232 * this field (only one bit may be set). 233 */ 234 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 235 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 236 #define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required 237 * in DVO non-gang */ 238 # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 239 #define PLL_REF_INPUT_DREFCLK (0 << 13) 240 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 241 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO 242 * TVCLKIN */ 243 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 244 #define PLL_REF_INPUT_MASK (3 << 13) 245 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 246 /* 247 * Parallel to Serial Load Pulse phase selection. 248 * Selects the phase for the 10X DPLL clock for the PCIe 249 * digital display port. The range is 4 to 13; 10 or more 250 * is just a flip delay. The default is 6 251 */ 252 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 253 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 254 255 /* 256 * SDVO multiplier for 945G/GM. Not used on 965. 257 * 258 * DPLL_MD_UDI_MULTIPLIER_MASK 259 */ 260 #define SDVO_MULTIPLIER_MASK 0x000000ff 261 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 262 #define SDVO_MULTIPLIER_SHIFT_VGA 0 263 264 /* 265 * PLL_MD 266 */ 267 /* Pipe A SDVO/UDI clock multiplier/divider register for G965. */ 268 #define DPLL_A_MD 0x0601c 269 /* Pipe B SDVO/UDI clock multiplier/divider register for G965. */ 270 #define DPLL_B_MD 0x06020 271 /* 272 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 273 * 274 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 275 */ 276 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 277 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 278 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 279 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 280 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 281 /* 282 * SDVO/UDI pixel multiplier. 283 * 284 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 285 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 286 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 287 * dummy bytes in the datastream at an increased clock rate, with both sides of 288 * the link knowing how many bytes are fill. 289 * 290 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 291 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 292 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 293 * through an SDVO command. 294 * 295 * This register field has values of multiplication factor minus 1, with 296 * a maximum multiplier of 5 for SDVO. 297 */ 298 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 299 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 300 /* 301 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 302 * This best be set to the default value (3) or the CRT won't work. No, 303 * I don't entirely understand what this does... 304 */ 305 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 306 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 307 308 #define DPLL_TEST 0x606c 309 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 310 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 311 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 312 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 313 #define DPLLB_TEST_N_BYPASS (1 << 19) 314 #define DPLLB_TEST_M_BYPASS (1 << 18) 315 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 316 #define DPLLA_TEST_N_BYPASS (1 << 3) 317 #define DPLLA_TEST_M_BYPASS (1 << 2) 318 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 319 320 #define ADPA 0x61100 321 #define ADPA_DAC_ENABLE (1 << 31) 322 #define ADPA_DAC_DISABLE 0 323 #define ADPA_PIPE_SELECT_MASK (1 << 30) 324 #define ADPA_PIPE_A_SELECT 0 325 #define ADPA_PIPE_B_SELECT (1 << 30) 326 #define ADPA_USE_VGA_HVPOLARITY (1 << 15) 327 #define ADPA_SETS_HVPOLARITY 0 328 #define ADPA_VSYNC_CNTL_DISABLE (1 << 11) 329 #define ADPA_VSYNC_CNTL_ENABLE 0 330 #define ADPA_HSYNC_CNTL_DISABLE (1 << 10) 331 #define ADPA_HSYNC_CNTL_ENABLE 0 332 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 333 #define ADPA_VSYNC_ACTIVE_LOW 0 334 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 335 #define ADPA_HSYNC_ACTIVE_LOW 0 336 337 #define FPA0 0x06040 338 #define FPA1 0x06044 339 #define FPB0 0x06048 340 #define FPB1 0x0604c 341 #define FP_N_DIV_MASK 0x003f0000 342 #define FP_N_DIV_SHIFT 16 343 #define FP_M1_DIV_MASK 0x00003f00 344 #define FP_M1_DIV_SHIFT 8 345 #define FP_M2_DIV_MASK 0x0000003f 346 #define FP_M2_DIV_SHIFT 0 347 348 #define PORT_HOTPLUG_EN 0x61110 349 #define HDMIB_HOTPLUG_INT_EN (1 << 29) 350 #define HDMIC_HOTPLUG_INT_EN (1 << 28) 351 #define HDMID_HOTPLUG_INT_EN (1 << 27) 352 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 353 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 354 #define TV_HOTPLUG_INT_EN (1 << 18) 355 #define CRT_HOTPLUG_INT_EN (1 << 9) 356 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 357 /* CDV.. */ 358 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 359 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 360 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 361 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 362 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 363 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 364 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 365 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 366 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 367 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 368 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 369 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 370 #define CRT_HOTPLUG_DETECT_MASK 0x000000F8 371 372 #define PORT_HOTPLUG_STAT 0x61114 373 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 374 #define TV_HOTPLUG_INT_STATUS (1 << 10) 375 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 376 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 377 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 378 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 379 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 380 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 381 382 #define SDVOB 0x61140 383 #define SDVOC 0x61160 384 #define SDVO_ENABLE (1 << 31) 385 #define SDVO_PIPE_B_SELECT (1 << 30) 386 #define SDVO_STALL_SELECT (1 << 29) 387 #define SDVO_INTERRUPT_ENABLE (1 << 26) 388 #define SDVO_COLOR_RANGE_16_235 (1 << 8) 389 #define SDVO_AUDIO_ENABLE (1 << 6) 390 391 /** 392 * 915G/GM SDVO pixel multiplier. 393 * 394 * Programmed value is multiplier - 1, up to 5x. 395 * 396 * DPLL_MD_UDI_MULTIPLIER_MASK 397 */ 398 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 399 #define SDVO_PORT_MULTIPLY_SHIFT 23 400 #define SDVO_PHASE_SELECT_MASK (15 << 19) 401 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 402 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 403 #define SDVOC_GANG_MODE (1 << 16) 404 #define SDVO_BORDER_ENABLE (1 << 7) 405 #define SDVOB_PCIE_CONCURRENCY (1 << 3) 406 #define SDVO_DETECTED (1 << 2) 407 /* Bits to be preserved when writing */ 408 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14)) 409 #define SDVOC_PRESERVE_MASK (1 << 17) 410 411 /* 412 * This register controls the LVDS output enable, pipe selection, and data 413 * format selection. 414 * 415 * All of the clock/data pairs are force powered down by power sequencing. 416 */ 417 #define LVDS 0x61180 418 /* 419 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 420 * the DPLL semantics change when the LVDS is assigned to that pipe. 421 */ 422 #define LVDS_PORT_EN (1 << 31) 423 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 424 #define LVDS_PIPEB_SELECT (1 << 30) 425 426 /* Turns on border drawing to allow centered display. */ 427 #define LVDS_BORDER_EN (1 << 15) 428 429 /* 430 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 431 * pixel. 432 */ 433 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 434 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 435 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 436 /* 437 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 438 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 439 * on. 440 */ 441 #define LVDS_A3_POWER_MASK (3 << 6) 442 #define LVDS_A3_POWER_DOWN (0 << 6) 443 #define LVDS_A3_POWER_UP (3 << 6) 444 /* 445 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 446 * is set. 447 */ 448 #define LVDS_CLKB_POWER_MASK (3 << 4) 449 #define LVDS_CLKB_POWER_DOWN (0 << 4) 450 #define LVDS_CLKB_POWER_UP (3 << 4) 451 /* 452 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 453 * setting for whether we are in dual-channel mode. The B3 pair will 454 * additionally only be powered up when LVDS_A3_POWER_UP is set. 455 */ 456 #define LVDS_B0B3_POWER_MASK (3 << 2) 457 #define LVDS_B0B3_POWER_DOWN (0 << 2) 458 #define LVDS_B0B3_POWER_UP (3 << 2) 459 460 #define PIPEACONF 0x70008 461 #define PIPEACONF_ENABLE (1 << 31) 462 #define PIPEACONF_DISABLE 0 463 #define PIPEACONF_DOUBLE_WIDE (1 << 30) 464 #define PIPECONF_ACTIVE (1 << 30) 465 #define I965_PIPECONF_ACTIVE (1 << 30) 466 #define PIPECONF_DSIPLL_LOCK (1 << 29) 467 #define PIPEACONF_SINGLE_WIDE 0 468 #define PIPEACONF_PIPE_UNLOCKED 0 469 #define PIPEACONF_DSR (1 << 26) 470 #define PIPEACONF_PIPE_LOCKED (1 << 25) 471 #define PIPEACONF_PALETTE 0 472 #define PIPECONF_FORCE_BORDER (1 << 25) 473 #define PIPEACONF_GAMMA (1 << 24) 474 #define PIPECONF_PROGRESSIVE (0 << 21) 475 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 476 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 477 #define PIPECONF_PLANE_OFF (1 << 19) 478 #define PIPECONF_CURSOR_OFF (1 << 18) 479 480 #define PIPEBCONF 0x71008 481 #define PIPEBCONF_ENABLE (1 << 31) 482 #define PIPEBCONF_DISABLE 0 483 #define PIPEBCONF_DOUBLE_WIDE (1 << 30) 484 #define PIPEBCONF_DISABLE 0 485 #define PIPEBCONF_GAMMA (1 << 24) 486 #define PIPEBCONF_PALETTE 0 487 488 #define PIPECCONF 0x72008 489 490 #define PIPEBGCMAXRED 0x71010 491 #define PIPEBGCMAXGREEN 0x71014 492 #define PIPEBGCMAXBLUE 0x71018 493 494 #define PIPEASTAT 0x70024 495 #define PIPEBSTAT 0x71024 496 #define PIPECSTAT 0x72024 497 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 498 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) 499 #define PIPE_VBLANK_CLEAR (1 << 1) 500 #define PIPE_VBLANK_STATUS (1 << 1) 501 #define PIPE_TE_STATUS (1UL << 6) 502 #define PIPE_DPST_EVENT_STATUS (1UL << 7) 503 #define PIPE_VSYNC_CLEAR (1UL << 9) 504 #define PIPE_VSYNC_STATUS (1UL << 9) 505 #define PIPE_HDMI_AUDIO_UNDERRUN_STATUS (1UL << 10) 506 #define PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS (1UL << 11) 507 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 508 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) 509 #define PIPE_TE_ENABLE (1UL << 22) 510 #define PIPE_DPST_EVENT_ENABLE (1UL << 23) 511 #define PIPE_VSYNC_ENABL (1UL << 25) 512 #define PIPE_HDMI_AUDIO_UNDERRUN (1UL << 26) 513 #define PIPE_HDMI_AUDIO_BUFFER_DONE (1UL << 27) 514 #define PIPE_FIFO_UNDERRUN (1UL << 31) 515 #define PIPE_HDMI_AUDIO_INT_MASK (PIPE_HDMI_AUDIO_UNDERRUN | \ 516 PIPE_HDMI_AUDIO_BUFFER_DONE) 517 #define PIPE_EVENT_MASK ((1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)|(1 << 22)|(1 << 21)|(1 << 20)|(1 << 16)) 518 #define PIPE_VBLANK_MASK ((1 << 25)|(1 << 24)|(1 << 18)|(1 << 17)) 519 #define HISTOGRAM_INT_CONTROL 0x61268 520 #define HISTOGRAM_BIN_DATA 0X61264 521 #define HISTOGRAM_LOGIC_CONTROL 0x61260 522 #define PWM_CONTROL_LOGIC 0x61250 523 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 524 #define HISTOGRAM_INTERRUPT_ENABLE (1UL << 31) 525 #define HISTOGRAM_LOGIC_ENABLE (1UL << 31) 526 #define PWM_LOGIC_ENABLE (1UL << 31) 527 #define PWM_PHASEIN_ENABLE (1UL << 25) 528 #define PWM_PHASEIN_INT_ENABLE (1UL << 24) 529 #define PWM_PHASEIN_VB_COUNT 0x00001f00 530 #define PWM_PHASEIN_INC 0x0000001f 531 #define HISTOGRAM_INT_CTRL_CLEAR (1UL << 30) 532 #define DPST_YUV_LUMA_MODE 0 533 534 struct dpst_ie_histogram_control { 535 union { 536 uint32_t data; 537 struct { 538 uint32_t bin_reg_index:7; 539 uint32_t reserved:4; 540 uint32_t bin_reg_func_select:1; 541 uint32_t sync_to_phase_in:1; 542 uint32_t alt_enhancement_mode:2; 543 uint32_t reserved1:1; 544 uint32_t sync_to_phase_in_count:8; 545 uint32_t histogram_mode_select:1; 546 uint32_t reserved2:4; 547 uint32_t ie_pipe_assignment:1; 548 uint32_t ie_mode_table_enabled:1; 549 uint32_t ie_histogram_enable:1; 550 }; 551 }; 552 }; 553 554 struct dpst_guardband { 555 union { 556 uint32_t data; 557 struct { 558 uint32_t guardband:22; 559 uint32_t guardband_interrupt_delay:8; 560 uint32_t interrupt_status:1; 561 uint32_t interrupt_enable:1; 562 }; 563 }; 564 }; 565 566 #define PIPEAFRAMEHIGH 0x70040 567 #define PIPEAFRAMEPIXEL 0x70044 568 #define PIPEBFRAMEHIGH 0x71040 569 #define PIPEBFRAMEPIXEL 0x71044 570 #define PIPECFRAMEHIGH 0x72040 571 #define PIPECFRAMEPIXEL 0x72044 572 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 573 #define PIPE_FRAME_HIGH_SHIFT 0 574 #define PIPE_FRAME_LOW_MASK 0xff000000 575 #define PIPE_FRAME_LOW_SHIFT 24 576 #define PIPE_PIXEL_MASK 0x00ffffff 577 #define PIPE_PIXEL_SHIFT 0 578 579 #define FW_BLC_SELF 0x20e0 580 #define FW_BLC_SELF_EN (1<<15) 581 582 #define DSPARB 0x70030 583 #define DSPFW1 0x70034 584 #define DSP_FIFO_SR_WM_MASK 0xFF800000 585 #define DSP_FIFO_SR_WM_SHIFT 23 586 #define CURSOR_B_FIFO_WM_MASK 0x003F0000 587 #define CURSOR_B_FIFO_WM_SHIFT 16 588 #define DSPFW2 0x70038 589 #define CURSOR_A_FIFO_WM_MASK 0x3F00 590 #define CURSOR_A_FIFO_WM_SHIFT 8 591 #define DSP_PLANE_C_FIFO_WM_MASK 0x7F 592 #define DSP_PLANE_C_FIFO_WM_SHIFT 0 593 #define DSPFW3 0x7003c 594 #define DSPFW4 0x70050 595 #define DSPFW5 0x70054 596 #define DSP_PLANE_B_FIFO_WM1_SHIFT 24 597 #define DSP_PLANE_A_FIFO_WM1_SHIFT 16 598 #define CURSOR_B_FIFO_WM1_SHIFT 8 599 #define CURSOR_FIFO_SR_WM1_SHIFT 0 600 #define DSPFW6 0x70058 601 #define DSPCHICKENBIT 0x70400 602 #define DSPACNTR 0x70180 603 #define DSPBCNTR 0x71180 604 #define DSPCCNTR 0x72180 605 #define DISPLAY_PLANE_ENABLE (1 << 31) 606 #define DISPLAY_PLANE_DISABLE 0 607 #define DISPPLANE_GAMMA_ENABLE (1 << 30) 608 #define DISPPLANE_GAMMA_DISABLE 0 609 #define DISPPLANE_PIXFORMAT_MASK (0xf << 26) 610 #define DISPPLANE_8BPP (0x2 << 26) 611 #define DISPPLANE_15_16BPP (0x4 << 26) 612 #define DISPPLANE_16BPP (0x5 << 26) 613 #define DISPPLANE_32BPP_NO_ALPHA (0x6 << 26) 614 #define DISPPLANE_32BPP (0x7 << 26) 615 #define DISPPLANE_STEREO_ENABLE (1 << 25) 616 #define DISPPLANE_STEREO_DISABLE 0 617 #define DISPPLANE_SEL_PIPE_MASK (1 << 24) 618 #define DISPPLANE_SEL_PIPE_POS 24 619 #define DISPPLANE_SEL_PIPE_A 0 620 #define DISPPLANE_SEL_PIPE_B (1 << 24) 621 #define DISPPLANE_SRC_KEY_ENABLE (1 << 22) 622 #define DISPPLANE_SRC_KEY_DISABLE 0 623 #define DISPPLANE_LINE_DOUBLE (1 << 20) 624 #define DISPPLANE_NO_LINE_DOUBLE 0 625 #define DISPPLANE_STEREO_POLARITY_FIRST 0 626 #define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18) 627 /* plane B only */ 628 #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15) 629 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 630 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 631 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 632 #define DISPPLANE_BOTTOM (4) 633 634 #define DSPABASE 0x70184 635 #define DSPALINOFF 0x70184 636 #define DSPASTRIDE 0x70188 637 638 #define DSPBBASE 0x71184 639 #define DSPBLINOFF 0X71184 640 #define DSPBADDR DSPBBASE 641 #define DSPBSTRIDE 0x71188 642 643 #define DSPCBASE 0x72184 644 #define DSPCLINOFF 0x72184 645 #define DSPCSTRIDE 0x72188 646 647 #define DSPAKEYVAL 0x70194 648 #define DSPAKEYMASK 0x70198 649 650 #define DSPAPOS 0x7018C /* reserved */ 651 #define DSPASIZE 0x70190 652 #define DSPBPOS 0x7118C 653 #define DSPBSIZE 0x71190 654 #define DSPCPOS 0x7218C 655 #define DSPCSIZE 0x72190 656 657 #define DSPASURF 0x7019C 658 #define DSPATILEOFF 0x701A4 659 660 #define DSPBSURF 0x7119C 661 #define DSPBTILEOFF 0x711A4 662 663 #define DSPCSURF 0x7219C 664 #define DSPCTILEOFF 0x721A4 665 #define DSPCKEYMAXVAL 0x721A0 666 #define DSPCKEYMINVAL 0x72194 667 #define DSPCKEYMSK 0x72198 668 669 #define VGACNTRL 0x71400 670 #define VGA_DISP_DISABLE (1 << 31) 671 #define VGA_2X_MODE (1 << 30) 672 #define VGA_PIPE_B_SELECT (1 << 29) 673 674 /* 675 * Overlay registers 676 */ 677 #define OV_C_OFFSET 0x08000 678 #define OV_OVADD 0x30000 679 #define OV_DOVASTA 0x30008 680 # define OV_PIPE_SELECT ((1 << 6)|(1 << 7)) 681 # define OV_PIPE_SELECT_POS 6 682 # define OV_PIPE_A 0 683 # define OV_PIPE_C 1 684 #define OV_OGAMC5 0x30010 685 #define OV_OGAMC4 0x30014 686 #define OV_OGAMC3 0x30018 687 #define OV_OGAMC2 0x3001C 688 #define OV_OGAMC1 0x30020 689 #define OV_OGAMC0 0x30024 690 #define OVC_OVADD 0x38000 691 #define OVC_DOVCSTA 0x38008 692 #define OVC_OGAMC5 0x38010 693 #define OVC_OGAMC4 0x38014 694 #define OVC_OGAMC3 0x38018 695 #define OVC_OGAMC2 0x3801C 696 #define OVC_OGAMC1 0x38020 697 #define OVC_OGAMC0 0x38024 698 699 /* 700 * Some BIOS scratch area registers. The 845 (and 830?) store the amount 701 * of video memory available to the BIOS in SWF1. 702 */ 703 #define SWF0 0x71410 704 #define SWF1 0x71414 705 #define SWF2 0x71418 706 #define SWF3 0x7141c 707 #define SWF4 0x71420 708 #define SWF5 0x71424 709 #define SWF6 0x71428 710 711 /* 712 * 855 scratch registers. 713 */ 714 #define SWF00 0x70410 715 #define SWF01 0x70414 716 #define SWF02 0x70418 717 #define SWF03 0x7041c 718 #define SWF04 0x70420 719 #define SWF05 0x70424 720 #define SWF06 0x70428 721 722 #define SWF10 SWF0 723 #define SWF11 SWF1 724 #define SWF12 SWF2 725 #define SWF13 SWF3 726 #define SWF14 SWF4 727 #define SWF15 SWF5 728 #define SWF16 SWF6 729 730 #define SWF30 0x72414 731 #define SWF31 0x72418 732 #define SWF32 0x7241c 733 734 735 /* 736 * Palette registers 737 */ 738 #define PALETTE_A 0x0a000 739 #define PALETTE_B 0x0a800 740 #define PALETTE_C 0x0ac00 741 742 /* Cursor A & B regs */ 743 #define CURACNTR 0x70080 744 #define CURSOR_MODE_DISABLE 0x00 745 #define CURSOR_MODE_64_32B_AX 0x07 746 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 747 #define MCURSOR_GAMMA_ENABLE (1 << 26) 748 #define CURABASE 0x70084 749 #define CURAPOS 0x70088 750 #define CURSOR_POS_MASK 0x007FF 751 #define CURSOR_POS_SIGN 0x8000 752 #define CURSOR_X_SHIFT 0 753 #define CURSOR_Y_SHIFT 16 754 #define CURBCNTR 0x700c0 755 #define CURBBASE 0x700c4 756 #define CURBPOS 0x700c8 757 #define CURCCNTR 0x700e0 758 #define CURCBASE 0x700e4 759 #define CURCPOS 0x700e8 760 761 /* 762 * Interrupt Registers 763 */ 764 #define IER 0x020a0 765 #define IIR 0x020a4 766 #define IMR 0x020a8 767 #define ISR 0x020ac 768 769 /* 770 * MOORESTOWN delta registers 771 */ 772 #define MRST_DPLL_A 0x0f014 773 #define MDFLD_DPLL_B 0x0f018 774 #define MDFLD_INPUT_REF_SEL (1 << 14) 775 #define MDFLD_VCO_SEL (1 << 16) 776 #define DPLLA_MODE_LVDS (2 << 26) /* mrst */ 777 #define MDFLD_PLL_LATCHEN (1 << 28) 778 #define MDFLD_PWR_GATE_EN (1 << 30) 779 #define MDFLD_P1_MASK (0x1FF << 17) 780 #define MRST_FPA0 0x0f040 781 #define MRST_FPA1 0x0f044 782 #define MDFLD_DPLL_DIV0 0x0f048 783 #define MDFLD_DPLL_DIV1 0x0f04c 784 #define MRST_PERF_MODE 0x020f4 785 786 /* 787 * MEDFIELD HDMI registers 788 */ 789 #define HDMIPHYMISCCTL 0x61134 790 #define HDMI_PHY_POWER_DOWN 0x7f 791 #define HDMIB_CONTROL 0x61140 792 #define HDMIB_PORT_EN (1 << 31) 793 #define HDMIB_PIPE_B_SELECT (1 << 30) 794 #define HDMIB_NULL_PACKET (1 << 9) 795 #define HDMIB_HDCP_PORT (1 << 5) 796 797 /* #define LVDS 0x61180 */ 798 #define MRST_PANEL_8TO6_DITHER_ENABLE (1 << 25) 799 #define MRST_PANEL_24_DOT_1_FORMAT (1 << 24) 800 #define LVDS_A3_POWER_UP_0_OUTPUT (1 << 6) 801 802 #define MIPI 0x61190 803 #define MIPI_C 0x62190 804 #define MIPI_PORT_EN (1 << 31) 805 /* Turns on border drawing to allow centered display. */ 806 #define SEL_FLOPPED_HSTX (1 << 23) 807 #define PASS_FROM_SPHY_TO_AFE (1 << 16) 808 #define MIPI_BORDER_EN (1 << 15) 809 #define MIPIA_3LANE_MIPIC_1LANE 0x1 810 #define MIPIA_2LANE_MIPIC_2LANE 0x2 811 #define TE_TRIGGER_DSI_PROTOCOL (1 << 2) 812 #define TE_TRIGGER_GPIO_PIN (1 << 3) 813 #define MIPI_TE_COUNT 0x61194 814 815 /* #define PP_CONTROL 0x61204 */ 816 #define POWER_DOWN_ON_RESET (1 << 1) 817 818 /* #define PFIT_CONTROL 0x61230 */ 819 #define PFIT_PIPE_SELECT (3 << 29) 820 #define PFIT_PIPE_SELECT_SHIFT (29) 821 822 /* #define BLC_PWM_CTL 0x61254 */ 823 #define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT (16) 824 #define MRST_BACKLIGHT_MODULATION_FREQ_MASK (0xffff << 16) 825 826 /* #define PIPEACONF 0x70008 */ 827 #define PIPEACONF_PIPE_STATE (1 << 30) 828 /* #define DSPACNTR 0x70180 */ 829 830 #define MRST_DSPABASE 0x7019c 831 #define MRST_DSPBBASE 0x7119c 832 #define MDFLD_DSPCBASE 0x7219c 833 834 /* 835 * Moorestown registers. 836 */ 837 838 /* 839 * MIPI IP registers 840 */ 841 #define MIPIC_REG_OFFSET 0x800 842 843 #define DEVICE_READY_REG 0xb000 844 #define LP_OUTPUT_HOLD (1 << 16) 845 #define EXIT_ULPS_DEV_READY 0x3 846 #define LP_OUTPUT_HOLD_RELEASE 0x810000 847 # define ENTERING_ULPS (2 << 1) 848 # define EXITING_ULPS (1 << 1) 849 # define ULPS_MASK (3 << 1) 850 # define BUS_POSSESSION (1 << 3) 851 #define INTR_STAT_REG 0xb004 852 #define RX_SOT_ERROR (1 << 0) 853 #define RX_SOT_SYNC_ERROR (1 << 1) 854 #define RX_ESCAPE_MODE_ENTRY_ERROR (1 << 3) 855 #define RX_LP_TX_SYNC_ERROR (1 << 4) 856 #define RX_HS_RECEIVE_TIMEOUT_ERROR (1 << 5) 857 #define RX_FALSE_CONTROL_ERROR (1 << 6) 858 #define RX_ECC_SINGLE_BIT_ERROR (1 << 7) 859 #define RX_ECC_MULTI_BIT_ERROR (1 << 8) 860 #define RX_CHECKSUM_ERROR (1 << 9) 861 #define RX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 10) 862 #define RX_DSI_VC_ID_INVALID (1 << 11) 863 #define TX_FALSE_CONTROL_ERROR (1 << 12) 864 #define TX_ECC_SINGLE_BIT_ERROR (1 << 13) 865 #define TX_ECC_MULTI_BIT_ERROR (1 << 14) 866 #define TX_CHECKSUM_ERROR (1 << 15) 867 #define TX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 16) 868 #define TX_DSI_VC_ID_INVALID (1 << 17) 869 #define HIGH_CONTENTION (1 << 18) 870 #define LOW_CONTENTION (1 << 19) 871 #define DPI_FIFO_UNDER_RUN (1 << 20) 872 #define HS_TX_TIMEOUT (1 << 21) 873 #define LP_RX_TIMEOUT (1 << 22) 874 #define TURN_AROUND_ACK_TIMEOUT (1 << 23) 875 #define ACK_WITH_NO_ERROR (1 << 24) 876 #define HS_GENERIC_WR_FIFO_FULL (1 << 27) 877 #define LP_GENERIC_WR_FIFO_FULL (1 << 28) 878 #define SPL_PKT_SENT (1 << 30) 879 #define INTR_EN_REG 0xb008 880 #define DSI_FUNC_PRG_REG 0xb00c 881 #define DPI_CHANNEL_NUMBER_POS 0x03 882 #define DBI_CHANNEL_NUMBER_POS 0x05 883 #define FMT_DPI_POS 0x07 884 #define FMT_DBI_POS 0x0A 885 #define DBI_DATA_WIDTH_POS 0x0D 886 887 /* DPI PIXEL FORMATS */ 888 #define RGB_565_FMT 0x01 /* RGB 565 FORMAT */ 889 #define RGB_666_FMT 0x02 /* RGB 666 FORMAT */ 890 #define LRGB_666_FMT 0x03 /* RGB LOOSELY PACKED 891 * 666 FORMAT 892 */ 893 #define RGB_888_FMT 0x04 /* RGB 888 FORMAT */ 894 #define VIRTUAL_CHANNEL_NUMBER_0 0x00 /* Virtual channel 0 */ 895 #define VIRTUAL_CHANNEL_NUMBER_1 0x01 /* Virtual channel 1 */ 896 #define VIRTUAL_CHANNEL_NUMBER_2 0x02 /* Virtual channel 2 */ 897 #define VIRTUAL_CHANNEL_NUMBER_3 0x03 /* Virtual channel 3 */ 898 899 #define DBI_NOT_SUPPORTED 0x00 /* command mode 900 * is not supported 901 */ 902 #define DBI_DATA_WIDTH_16BIT 0x01 /* 16 bit data */ 903 #define DBI_DATA_WIDTH_9BIT 0x02 /* 9 bit data */ 904 #define DBI_DATA_WIDTH_8BIT 0x03 /* 8 bit data */ 905 #define DBI_DATA_WIDTH_OPT1 0x04 /* option 1 */ 906 #define DBI_DATA_WIDTH_OPT2 0x05 /* option 2 */ 907 908 #define HS_TX_TIMEOUT_REG 0xb010 909 #define LP_RX_TIMEOUT_REG 0xb014 910 #define TURN_AROUND_TIMEOUT_REG 0xb018 911 #define DEVICE_RESET_REG 0xb01C 912 #define DPI_RESOLUTION_REG 0xb020 913 #define RES_V_POS 0x10 914 #define DBI_RESOLUTION_REG 0xb024 /* Reserved for MDFLD */ 915 #define HORIZ_SYNC_PAD_COUNT_REG 0xb028 916 #define HORIZ_BACK_PORCH_COUNT_REG 0xb02C 917 #define HORIZ_FRONT_PORCH_COUNT_REG 0xb030 918 #define HORIZ_ACTIVE_AREA_COUNT_REG 0xb034 919 #define VERT_SYNC_PAD_COUNT_REG 0xb038 920 #define VERT_BACK_PORCH_COUNT_REG 0xb03c 921 #define VERT_FRONT_PORCH_COUNT_REG 0xb040 922 #define HIGH_LOW_SWITCH_COUNT_REG 0xb044 923 #define DPI_CONTROL_REG 0xb048 924 #define DPI_SHUT_DOWN (1 << 0) 925 #define DPI_TURN_ON (1 << 1) 926 #define DPI_COLOR_MODE_ON (1 << 2) 927 #define DPI_COLOR_MODE_OFF (1 << 3) 928 #define DPI_BACK_LIGHT_ON (1 << 4) 929 #define DPI_BACK_LIGHT_OFF (1 << 5) 930 #define DPI_LP (1 << 6) 931 #define DPI_DATA_REG 0xb04c 932 #define DPI_BACK_LIGHT_ON_DATA 0x07 933 #define DPI_BACK_LIGHT_OFF_DATA 0x17 934 #define INIT_COUNT_REG 0xb050 935 #define MAX_RET_PAK_REG 0xb054 936 #define VIDEO_FMT_REG 0xb058 937 #define COMPLETE_LAST_PCKT (1 << 2) 938 #define EOT_DISABLE_REG 0xb05c 939 #define ENABLE_CLOCK_STOPPING (1 << 1) 940 #define LP_BYTECLK_REG 0xb060 941 #define LP_GEN_DATA_REG 0xb064 942 #define HS_GEN_DATA_REG 0xb068 943 #define LP_GEN_CTRL_REG 0xb06C 944 #define HS_GEN_CTRL_REG 0xb070 945 #define DCS_CHANNEL_NUMBER_POS 0x6 946 #define MCS_COMMANDS_POS 0x8 947 #define WORD_COUNTS_POS 0x8 948 #define MCS_PARAMETER_POS 0x10 949 #define GEN_FIFO_STAT_REG 0xb074 950 #define HS_DATA_FIFO_FULL (1 << 0) 951 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 952 #define HS_DATA_FIFO_EMPTY (1 << 2) 953 #define LP_DATA_FIFO_FULL (1 << 8) 954 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 955 #define LP_DATA_FIFO_EMPTY (1 << 10) 956 #define HS_CTRL_FIFO_FULL (1 << 16) 957 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 958 #define HS_CTRL_FIFO_EMPTY (1 << 18) 959 #define LP_CTRL_FIFO_FULL (1 << 24) 960 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 961 #define LP_CTRL_FIFO_EMPTY (1 << 26) 962 #define DBI_FIFO_EMPTY (1 << 27) 963 #define DPI_FIFO_EMPTY (1 << 28) 964 #define HS_LS_DBI_ENABLE_REG 0xb078 965 #define TXCLKESC_REG 0xb07c 966 #define DPHY_PARAM_REG 0xb080 967 #define DBI_BW_CTRL_REG 0xb084 968 #define CLK_LANE_SWT_REG 0xb088 969 970 /* 971 * MIPI Adapter registers 972 */ 973 #define MIPI_CONTROL_REG 0xb104 974 #define MIPI_2X_CLOCK_BITS ((1 << 0) | (1 << 1)) 975 #define MIPI_DATA_ADDRESS_REG 0xb108 976 #define MIPI_DATA_LENGTH_REG 0xb10C 977 #define MIPI_COMMAND_ADDRESS_REG 0xb110 978 #define MIPI_COMMAND_LENGTH_REG 0xb114 979 #define MIPI_READ_DATA_RETURN_REG0 0xb118 980 #define MIPI_READ_DATA_RETURN_REG1 0xb11C 981 #define MIPI_READ_DATA_RETURN_REG2 0xb120 982 #define MIPI_READ_DATA_RETURN_REG3 0xb124 983 #define MIPI_READ_DATA_RETURN_REG4 0xb128 984 #define MIPI_READ_DATA_RETURN_REG5 0xb12C 985 #define MIPI_READ_DATA_RETURN_REG6 0xb130 986 #define MIPI_READ_DATA_RETURN_REG7 0xb134 987 #define MIPI_READ_DATA_VALID_REG 0xb138 988 989 /* DBI COMMANDS */ 990 #define soft_reset 0x01 991 /* 992 * The display module performs a software reset. 993 * Registers are written with their SW Reset default values. 994 */ 995 #define get_power_mode 0x0a 996 /* 997 * The display module returns the current power mode 998 */ 999 #define get_address_mode 0x0b 1000 /* 1001 * The display module returns the current status. 1002 */ 1003 #define get_pixel_format 0x0c 1004 /* 1005 * This command gets the pixel format for the RGB image data 1006 * used by the interface. 1007 */ 1008 #define get_display_mode 0x0d 1009 /* 1010 * The display module returns the Display Image Mode status. 1011 */ 1012 #define get_signal_mode 0x0e 1013 /* 1014 * The display module returns the Display Signal Mode. 1015 */ 1016 #define get_diagnostic_result 0x0f 1017 /* 1018 * The display module returns the self-diagnostic results following 1019 * a Sleep Out command. 1020 */ 1021 #define enter_sleep_mode 0x10 1022 /* 1023 * This command causes the display module to enter the Sleep mode. 1024 * In this mode, all unnecessary blocks inside the display module are 1025 * disabled except interface communication. This is the lowest power 1026 * mode the display module supports. 1027 */ 1028 #define exit_sleep_mode 0x11 1029 /* 1030 * This command causes the display module to exit Sleep mode. 1031 * All blocks inside the display module are enabled. 1032 */ 1033 #define enter_partial_mode 0x12 1034 /* 1035 * This command causes the display module to enter the Partial Display 1036 * Mode. The Partial Display Mode window is described by the 1037 * set_partial_area command. 1038 */ 1039 #define enter_normal_mode 0x13 1040 /* 1041 * This command causes the display module to enter the Normal mode. 1042 * Normal Mode is defined as Partial Display mode and Scroll mode are off 1043 */ 1044 #define exit_invert_mode 0x20 1045 /* 1046 * This command causes the display module to stop inverting the image 1047 * data on the display device. The frame memory contents remain unchanged. 1048 * No status bits are changed. 1049 */ 1050 #define enter_invert_mode 0x21 1051 /* 1052 * This command causes the display module to invert the image data only on 1053 * the display device. The frame memory contents remain unchanged. 1054 * No status bits are changed. 1055 */ 1056 #define set_gamma_curve 0x26 1057 /* 1058 * This command selects the desired gamma curve for the display device. 1059 * Four fixed gamma curves are defined in section DCS spec. 1060 */ 1061 #define set_display_off 0x28 1062 /* ************************************************************************* *\ 1063 This command causes the display module to stop displaying the image data 1064 on the display device. The frame memory contents remain unchanged. 1065 No status bits are changed. 1066 \* ************************************************************************* */ 1067 #define set_display_on 0x29 1068 /* ************************************************************************* *\ 1069 This command causes the display module to start displaying the image data 1070 on the display device. The frame memory contents remain unchanged. 1071 No status bits are changed. 1072 \* ************************************************************************* */ 1073 #define set_column_address 0x2a 1074 /* 1075 * This command defines the column extent of the frame memory accessed by 1076 * the hostprocessor with the read_memory_continue and 1077 * write_memory_continue commands. 1078 * No status bits are changed. 1079 */ 1080 #define set_page_addr 0x2b 1081 /* 1082 * This command defines the page extent of the frame memory accessed by 1083 * the host processor with the write_memory_continue and 1084 * read_memory_continue command. 1085 * No status bits are changed. 1086 */ 1087 #define write_mem_start 0x2c 1088 /* 1089 * This command transfers image data from the host processor to the 1090 * display modules frame memory starting at the pixel location specified 1091 * by preceding set_column_address and set_page_address commands. 1092 */ 1093 #define set_partial_area 0x30 1094 /* 1095 * This command defines the Partial Display mode s display area. 1096 * There are two parameters associated with this command, the first 1097 * defines the Start Row (SR) and the second the End Row (ER). SR and ER 1098 * refer to the Frame Memory Line Pointer. 1099 */ 1100 #define set_scroll_area 0x33 1101 /* 1102 * This command defines the display modules Vertical Scrolling Area. 1103 */ 1104 #define set_tear_off 0x34 1105 /* 1106 * This command turns off the display modules Tearing Effect output 1107 * signal on the TE signal line. 1108 */ 1109 #define set_tear_on 0x35 1110 /* 1111 * This command turns on the display modules Tearing Effect output signal 1112 * on the TE signal line. 1113 */ 1114 #define set_address_mode 0x36 1115 /* 1116 * This command sets the data order for transfers from the host processor 1117 * to display modules frame memory,bits B[7:5] and B3, and from the 1118 * display modules frame memory to the display device, bits B[2:0] and B4. 1119 */ 1120 #define set_scroll_start 0x37 1121 /* 1122 * This command sets the start of the vertical scrolling area in the frame 1123 * memory. The vertical scrolling area is fully defined when this command 1124 * is used with the set_scroll_area command The set_scroll_start command 1125 * has one parameter, the Vertical Scroll Pointer. The VSP defines the 1126 * line in the frame memory that is written to the display device as the 1127 * first line of the vertical scroll area. 1128 */ 1129 #define exit_idle_mode 0x38 1130 /* 1131 * This command causes the display module to exit Idle mode. 1132 */ 1133 #define enter_idle_mode 0x39 1134 /* 1135 * This command causes the display module to enter Idle Mode. 1136 * In Idle Mode, color expression is reduced. Colors are shown on the 1137 * display device using the MSB of each of the R, G and B color 1138 * components in the frame memory 1139 */ 1140 #define set_pixel_format 0x3a 1141 /* 1142 * This command sets the pixel format for the RGB image data used by the 1143 * interface. 1144 * Bits D[6:4] DPI Pixel Format Definition 1145 * Bits D[2:0] DBI Pixel Format Definition 1146 * Bits D7 and D3 are not used. 1147 */ 1148 #define DCS_PIXEL_FORMAT_3bpp 0x1 1149 #define DCS_PIXEL_FORMAT_8bpp 0x2 1150 #define DCS_PIXEL_FORMAT_12bpp 0x3 1151 #define DCS_PIXEL_FORMAT_16bpp 0x5 1152 #define DCS_PIXEL_FORMAT_18bpp 0x6 1153 #define DCS_PIXEL_FORMAT_24bpp 0x7 1154 1155 #define write_mem_cont 0x3c 1156 1157 /* 1158 * This command transfers image data from the host processor to the 1159 * display module's frame memory continuing from the pixel location 1160 * following the previous write_memory_continue or write_memory_start 1161 * command. 1162 */ 1163 #define set_tear_scanline 0x44 1164 /* 1165 * This command turns on the display modules Tearing Effect output signal 1166 * on the TE signal line when the display module reaches line N. 1167 */ 1168 #define get_scanline 0x45 1169 /* 1170 * The display module returns the current scanline, N, used to update the 1171 * display device. The total number of scanlines on a display device is 1172 * defined as VSYNC + VBP + VACT + VFP.The first scanline is defined as 1173 * the first line of V Sync and is denoted as Line 0. 1174 * When in Sleep Mode, the value returned by get_scanline is undefined. 1175 */ 1176 1177 /* MCS or Generic COMMANDS */ 1178 /* MCS/generic data type */ 1179 #define GEN_SHORT_WRITE_0 0x03 /* generic short write, no parameters */ 1180 #define GEN_SHORT_WRITE_1 0x13 /* generic short write, 1 parameters */ 1181 #define GEN_SHORT_WRITE_2 0x23 /* generic short write, 2 parameters */ 1182 #define GEN_READ_0 0x04 /* generic read, no parameters */ 1183 #define GEN_READ_1 0x14 /* generic read, 1 parameters */ 1184 #define GEN_READ_2 0x24 /* generic read, 2 parameters */ 1185 #define GEN_LONG_WRITE 0x29 /* generic long write */ 1186 #define MCS_SHORT_WRITE_0 0x05 /* MCS short write, no parameters */ 1187 #define MCS_SHORT_WRITE_1 0x15 /* MCS short write, 1 parameters */ 1188 #define MCS_READ 0x06 /* MCS read, no parameters */ 1189 #define MCS_LONG_WRITE 0x39 /* MCS long write */ 1190 /* MCS/generic commands */ 1191 /* TPO MCS */ 1192 #define write_display_profile 0x50 1193 #define write_display_brightness 0x51 1194 #define write_ctrl_display 0x53 1195 #define write_ctrl_cabc 0x55 1196 #define UI_IMAGE 0x01 1197 #define STILL_IMAGE 0x02 1198 #define MOVING_IMAGE 0x03 1199 #define write_hysteresis 0x57 1200 #define write_gamma_setting 0x58 1201 #define write_cabc_min_bright 0x5e 1202 #define write_kbbc_profile 0x60 1203 /* TMD MCS */ 1204 #define tmd_write_display_brightness 0x8c 1205 1206 /* 1207 * This command is used to control ambient light, panel backlight 1208 * brightness and gamma settings. 1209 */ 1210 #define BRIGHT_CNTL_BLOCK_ON (1 << 5) 1211 #define AMBIENT_LIGHT_SENSE_ON (1 << 4) 1212 #define DISPLAY_DIMMING_ON (1 << 3) 1213 #define BACKLIGHT_ON (1 << 2) 1214 #define DISPLAY_BRIGHTNESS_AUTO (1 << 1) 1215 #define GAMMA_AUTO (1 << 0) 1216 1217 /* DCS Interface Pixel Formats */ 1218 #define DCS_PIXEL_FORMAT_3BPP 0x1 1219 #define DCS_PIXEL_FORMAT_8BPP 0x2 1220 #define DCS_PIXEL_FORMAT_12BPP 0x3 1221 #define DCS_PIXEL_FORMAT_16BPP 0x5 1222 #define DCS_PIXEL_FORMAT_18BPP 0x6 1223 #define DCS_PIXEL_FORMAT_24BPP 0x7 1224 /* ONE PARAMETER READ DATA */ 1225 #define addr_mode_data 0xfc 1226 #define diag_res_data 0x00 1227 #define disp_mode_data 0x23 1228 #define pxl_fmt_data 0x77 1229 #define pwr_mode_data 0x74 1230 #define sig_mode_data 0x00 1231 /* TWO PARAMETERS READ DATA */ 1232 #define scanline_data1 0xff 1233 #define scanline_data2 0xff 1234 #define NON_BURST_MODE_SYNC_PULSE 0x01 /* Non Burst Mode 1235 * with Sync Pulse 1236 */ 1237 #define NON_BURST_MODE_SYNC_EVENTS 0x02 /* Non Burst Mode 1238 * with Sync events 1239 */ 1240 #define BURST_MODE 0x03 /* Burst Mode */ 1241 #define DBI_COMMAND_BUFFER_SIZE 0x240 /* 0x32 */ /* 0x120 */ 1242 /* Allocate at least 1243 * 0x100 Byte with 32 1244 * byte alignment 1245 */ 1246 #define DBI_DATA_BUFFER_SIZE 0x120 /* Allocate at least 1247 * 0x100 Byte with 32 1248 * byte alignment 1249 */ 1250 #define DBI_CB_TIME_OUT 0xFFFF 1251 1252 #define GEN_FB_TIME_OUT 2000 1253 1254 #define SKU_83 0x01 1255 #define SKU_100 0x02 1256 #define SKU_100L 0x04 1257 #define SKU_BYPASS 0x08 1258 1259 /* Some handy macros for playing with bitfields. */ 1260 #define PSB_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low)) 1261 #define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK) 1262 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) 1263 1264 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 1265 1266 /* PCI config space */ 1267 1268 #define SB_PCKT 0x02100 /* cedarview */ 1269 # define SB_OPCODE_MASK PSB_MASK(31, 16) 1270 # define SB_OPCODE_SHIFT 16 1271 # define SB_OPCODE_READ 0 1272 # define SB_OPCODE_WRITE 1 1273 # define SB_DEST_MASK PSB_MASK(15, 8) 1274 # define SB_DEST_SHIFT 8 1275 # define SB_DEST_DPLL 0x88 1276 # define SB_BYTE_ENABLE_MASK PSB_MASK(7, 4) 1277 # define SB_BYTE_ENABLE_SHIFT 4 1278 # define SB_BUSY (1 << 0) 1279 1280 #define DSPCLK_GATE_D 0x6200 1281 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* Fixed value on CDV */ 1282 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1283 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) 1284 1285 #define RAMCLK_GATE_D 0x6210 1286 1287 /* 32-bit value read/written from the DPIO reg. */ 1288 #define SB_DATA 0x02104 /* cedarview */ 1289 /* 32-bit address of the DPIO reg to be read/written. */ 1290 #define SB_ADDR 0x02108 /* cedarview */ 1291 #define DPIO_CFG 0x02110 /* cedarview */ 1292 # define DPIO_MODE_SELECT_1 (1 << 3) 1293 # define DPIO_MODE_SELECT_0 (1 << 2) 1294 # define DPIO_SFR_BYPASS (1 << 1) 1295 /* reset is active low */ 1296 # define DPIO_CMN_RESET_N (1 << 0) 1297 1298 /* Cedarview sideband registers */ 1299 #define _SB_M_A 0x8008 1300 #define _SB_M_B 0x8028 1301 #define SB_M(pipe) _PIPE(pipe, _SB_M_A, _SB_M_B) 1302 # define SB_M_DIVIDER_MASK (0xFF << 24) 1303 # define SB_M_DIVIDER_SHIFT 24 1304 1305 #define _SB_N_VCO_A 0x8014 1306 #define _SB_N_VCO_B 0x8034 1307 #define SB_N_VCO(pipe) _PIPE(pipe, _SB_N_VCO_A, _SB_N_VCO_B) 1308 #define SB_N_VCO_SEL_MASK PSB_MASK(31, 30) 1309 #define SB_N_VCO_SEL_SHIFT 30 1310 #define SB_N_DIVIDER_MASK PSB_MASK(29, 26) 1311 #define SB_N_DIVIDER_SHIFT 26 1312 #define SB_N_CB_TUNE_MASK PSB_MASK(25, 24) 1313 #define SB_N_CB_TUNE_SHIFT 24 1314 1315 /* the bit 14:13 is used to select between the different reference clock for Pipe A/B */ 1316 #define SB_REF_DPLLA 0x8010 1317 #define SB_REF_DPLLB 0x8030 1318 #define REF_CLK_MASK (0x3 << 13) 1319 #define REF_CLK_CORE (0 << 13) 1320 #define REF_CLK_DPLL (1 << 13) 1321 #define REF_CLK_DPLLA (2 << 13) 1322 /* For the DPLL B, it will use the reference clk from DPLL A when using (2 << 13) */ 1323 1324 #define _SB_REF_A 0x8018 1325 #define _SB_REF_B 0x8038 1326 #define SB_REF_SFR(pipe) _PIPE(pipe, _SB_REF_A, _SB_REF_B) 1327 1328 #define _SB_P_A 0x801c 1329 #define _SB_P_B 0x803c 1330 #define SB_P(pipe) _PIPE(pipe, _SB_P_A, _SB_P_B) 1331 #define SB_P2_DIVIDER_MASK PSB_MASK(31, 30) 1332 #define SB_P2_DIVIDER_SHIFT 30 1333 #define SB_P2_10 0 /* HDMI, DP, DAC */ 1334 #define SB_P2_5 1 /* DAC */ 1335 #define SB_P2_14 2 /* LVDS single */ 1336 #define SB_P2_7 3 /* LVDS double */ 1337 #define SB_P1_DIVIDER_MASK PSB_MASK(15, 12) 1338 #define SB_P1_DIVIDER_SHIFT 12 1339 1340 #define PSB_LANE0 0x120 1341 #define PSB_LANE1 0x220 1342 #define PSB_LANE2 0x2320 1343 #define PSB_LANE3 0x2420 1344 1345 #define LANE_PLL_MASK (0x7 << 20) 1346 #define LANE_PLL_ENABLE (0x3 << 20) 1347 #define LANE_PLL_PIPE(p) (((p) == 0) ? (1 << 21) : (0 << 21)) 1348 1349 1350 #endif 1351