1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright © 2006-2011 Intel Corporation 4 * 5 * Authors: 6 * Eric Anholt <eric@anholt.net> 7 */ 8 9 #include <linux/i2c.h> 10 11 #include <drm/drmP.h> 12 #include <drm/drm_plane_helper.h> 13 #include "framebuffer.h" 14 #include "psb_drv.h" 15 #include "psb_intel_drv.h" 16 #include "psb_intel_reg.h" 17 #include "gma_display.h" 18 #include "power.h" 19 20 #define INTEL_LIMIT_I9XX_SDVO_DAC 0 21 #define INTEL_LIMIT_I9XX_LVDS 1 22 23 static const struct gma_limit_t psb_intel_limits[] = { 24 { /* INTEL_LIMIT_I9XX_SDVO_DAC */ 25 .dot = {.min = 20000, .max = 400000}, 26 .vco = {.min = 1400000, .max = 2800000}, 27 .n = {.min = 1, .max = 6}, 28 .m = {.min = 70, .max = 120}, 29 .m1 = {.min = 8, .max = 18}, 30 .m2 = {.min = 3, .max = 7}, 31 .p = {.min = 5, .max = 80}, 32 .p1 = {.min = 1, .max = 8}, 33 .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5}, 34 .find_pll = gma_find_best_pll, 35 }, 36 { /* INTEL_LIMIT_I9XX_LVDS */ 37 .dot = {.min = 20000, .max = 400000}, 38 .vco = {.min = 1400000, .max = 2800000}, 39 .n = {.min = 1, .max = 6}, 40 .m = {.min = 70, .max = 120}, 41 .m1 = {.min = 8, .max = 18}, 42 .m2 = {.min = 3, .max = 7}, 43 .p = {.min = 7, .max = 98}, 44 .p1 = {.min = 1, .max = 8}, 45 /* The single-channel range is 25-112Mhz, and dual-channel 46 * is 80-224Mhz. Prefer single channel as much as possible. 47 */ 48 .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7}, 49 .find_pll = gma_find_best_pll, 50 }, 51 }; 52 53 static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc, 54 int refclk) 55 { 56 const struct gma_limit_t *limit; 57 58 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 59 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS]; 60 else 61 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; 62 return limit; 63 } 64 65 static void psb_intel_clock(int refclk, struct gma_clock_t *clock) 66 { 67 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 68 clock->p = clock->p1 * clock->p2; 69 clock->vco = refclk * clock->m / (clock->n + 2); 70 clock->dot = clock->vco / clock->p; 71 } 72 73 /** 74 * Return the pipe currently connected to the panel fitter, 75 * or -1 if the panel fitter is not present or not in use 76 */ 77 static int psb_intel_panel_fitter_pipe(struct drm_device *dev) 78 { 79 u32 pfit_control; 80 81 pfit_control = REG_READ(PFIT_CONTROL); 82 83 /* See if the panel fitter is in use */ 84 if ((pfit_control & PFIT_ENABLE) == 0) 85 return -1; 86 /* Must be on PIPE 1 for PSB */ 87 return 1; 88 } 89 90 static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, 91 struct drm_display_mode *mode, 92 struct drm_display_mode *adjusted_mode, 93 int x, int y, 94 struct drm_framebuffer *old_fb) 95 { 96 struct drm_device *dev = crtc->dev; 97 struct drm_psb_private *dev_priv = dev->dev_private; 98 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 99 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 100 int pipe = gma_crtc->pipe; 101 const struct psb_offset *map = &dev_priv->regmap[pipe]; 102 int refclk; 103 struct gma_clock_t clock; 104 u32 dpll = 0, fp = 0, dspcntr, pipeconf; 105 bool ok, is_sdvo = false; 106 bool is_lvds = false, is_tv = false; 107 struct drm_mode_config *mode_config = &dev->mode_config; 108 struct drm_connector *connector; 109 const struct gma_limit_t *limit; 110 111 /* No scan out no play */ 112 if (crtc->primary->fb == NULL) { 113 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 114 return 0; 115 } 116 117 list_for_each_entry(connector, &mode_config->connector_list, head) { 118 struct gma_encoder *gma_encoder = gma_attached_encoder(connector); 119 120 if (!connector->encoder 121 || connector->encoder->crtc != crtc) 122 continue; 123 124 switch (gma_encoder->type) { 125 case INTEL_OUTPUT_LVDS: 126 is_lvds = true; 127 break; 128 case INTEL_OUTPUT_SDVO: 129 is_sdvo = true; 130 break; 131 case INTEL_OUTPUT_TVOUT: 132 is_tv = true; 133 break; 134 } 135 } 136 137 refclk = 96000; 138 139 limit = gma_crtc->clock_funcs->limit(crtc, refclk); 140 141 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, 142 &clock); 143 if (!ok) { 144 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d", 145 adjusted_mode->clock, clock.dot); 146 return 0; 147 } 148 149 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 150 151 dpll = DPLL_VGA_MODE_DIS; 152 if (is_lvds) { 153 dpll |= DPLLB_MODE_LVDS; 154 dpll |= DPLL_DVO_HIGH_SPEED; 155 } else 156 dpll |= DPLLB_MODE_DAC_SERIAL; 157 if (is_sdvo) { 158 int sdvo_pixel_multiply = 159 adjusted_mode->clock / mode->clock; 160 dpll |= DPLL_DVO_HIGH_SPEED; 161 dpll |= 162 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 163 } 164 165 /* compute bitmask from p1 value */ 166 dpll |= (1 << (clock.p1 - 1)) << 16; 167 switch (clock.p2) { 168 case 5: 169 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 170 break; 171 case 7: 172 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 173 break; 174 case 10: 175 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 176 break; 177 case 14: 178 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 179 break; 180 } 181 182 if (is_tv) { 183 /* XXX: just matching BIOS for now */ 184 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 185 dpll |= 3; 186 } 187 dpll |= PLL_REF_INPUT_DREFCLK; 188 189 /* setup pipeconf */ 190 pipeconf = REG_READ(map->conf); 191 192 /* Set up the display plane register */ 193 dspcntr = DISPPLANE_GAMMA_ENABLE; 194 195 if (pipe == 0) 196 dspcntr |= DISPPLANE_SEL_PIPE_A; 197 else 198 dspcntr |= DISPPLANE_SEL_PIPE_B; 199 200 dspcntr |= DISPLAY_PLANE_ENABLE; 201 pipeconf |= PIPEACONF_ENABLE; 202 dpll |= DPLL_VCO_ENABLE; 203 204 205 /* Disable the panel fitter if it was on our pipe */ 206 if (psb_intel_panel_fitter_pipe(dev) == pipe) 207 REG_WRITE(PFIT_CONTROL, 0); 208 209 drm_mode_debug_printmodeline(mode); 210 211 if (dpll & DPLL_VCO_ENABLE) { 212 REG_WRITE(map->fp0, fp); 213 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); 214 REG_READ(map->dpll); 215 udelay(150); 216 } 217 218 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 219 * This is an exception to the general rule that mode_set doesn't turn 220 * things on. 221 */ 222 if (is_lvds) { 223 u32 lvds = REG_READ(LVDS); 224 225 lvds &= ~LVDS_PIPEB_SELECT; 226 if (pipe == 1) 227 lvds |= LVDS_PIPEB_SELECT; 228 229 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 230 /* Set the B0-B3 data pairs corresponding to 231 * whether we're going to 232 * set the DPLLs for dual-channel mode or not. 233 */ 234 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 235 if (clock.p2 == 7) 236 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 237 238 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 239 * appropriately here, but we need to look more 240 * thoroughly into how panels behave in the two modes. 241 */ 242 243 REG_WRITE(LVDS, lvds); 244 REG_READ(LVDS); 245 } 246 247 REG_WRITE(map->fp0, fp); 248 REG_WRITE(map->dpll, dpll); 249 REG_READ(map->dpll); 250 /* Wait for the clocks to stabilize. */ 251 udelay(150); 252 253 /* write it again -- the BIOS does, after all */ 254 REG_WRITE(map->dpll, dpll); 255 256 REG_READ(map->dpll); 257 /* Wait for the clocks to stabilize. */ 258 udelay(150); 259 260 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | 261 ((adjusted_mode->crtc_htotal - 1) << 16)); 262 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | 263 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 264 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | 265 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 266 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | 267 ((adjusted_mode->crtc_vtotal - 1) << 16)); 268 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | 269 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 270 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | 271 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 272 /* pipesrc and dspsize control the size that is scaled from, 273 * which should always be the user's requested size. 274 */ 275 REG_WRITE(map->size, 276 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); 277 REG_WRITE(map->pos, 0); 278 REG_WRITE(map->src, 279 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 280 REG_WRITE(map->conf, pipeconf); 281 REG_READ(map->conf); 282 283 gma_wait_for_vblank(dev); 284 285 REG_WRITE(map->cntr, dspcntr); 286 287 /* Flush the plane changes */ 288 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 289 290 gma_wait_for_vblank(dev); 291 292 return 0; 293 } 294 295 /* Returns the clock of the currently programmed mode of the given pipe. */ 296 static int psb_intel_crtc_clock_get(struct drm_device *dev, 297 struct drm_crtc *crtc) 298 { 299 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 300 struct drm_psb_private *dev_priv = dev->dev_private; 301 int pipe = gma_crtc->pipe; 302 const struct psb_offset *map = &dev_priv->regmap[pipe]; 303 u32 dpll; 304 u32 fp; 305 struct gma_clock_t clock; 306 bool is_lvds; 307 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 308 309 if (gma_power_begin(dev, false)) { 310 dpll = REG_READ(map->dpll); 311 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 312 fp = REG_READ(map->fp0); 313 else 314 fp = REG_READ(map->fp1); 315 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); 316 gma_power_end(dev); 317 } else { 318 dpll = p->dpll; 319 320 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 321 fp = p->fp0; 322 else 323 fp = p->fp1; 324 325 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS & 326 LVDS_PORT_EN); 327 } 328 329 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 330 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 331 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 332 333 if (is_lvds) { 334 clock.p1 = 335 ffs((dpll & 336 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 337 DPLL_FPA01_P1_POST_DIV_SHIFT); 338 clock.p2 = 14; 339 340 if ((dpll & PLL_REF_INPUT_MASK) == 341 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 342 /* XXX: might not be 66MHz */ 343 psb_intel_clock(66000, &clock); 344 } else 345 psb_intel_clock(48000, &clock); 346 } else { 347 if (dpll & PLL_P1_DIVIDE_BY_TWO) 348 clock.p1 = 2; 349 else { 350 clock.p1 = 351 ((dpll & 352 DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 353 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 354 } 355 if (dpll & PLL_P2_DIVIDE_BY_4) 356 clock.p2 = 4; 357 else 358 clock.p2 = 2; 359 360 psb_intel_clock(48000, &clock); 361 } 362 363 /* XXX: It would be nice to validate the clocks, but we can't reuse 364 * i830PllIsValid() because it relies on the xf86_config connector 365 * configuration being accurate, which it isn't necessarily. 366 */ 367 368 return clock.dot; 369 } 370 371 /** Returns the currently programmed mode of the given pipe. */ 372 struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, 373 struct drm_crtc *crtc) 374 { 375 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 376 int pipe = gma_crtc->pipe; 377 struct drm_display_mode *mode; 378 int htot; 379 int hsync; 380 int vtot; 381 int vsync; 382 struct drm_psb_private *dev_priv = dev->dev_private; 383 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 384 const struct psb_offset *map = &dev_priv->regmap[pipe]; 385 386 if (gma_power_begin(dev, false)) { 387 htot = REG_READ(map->htotal); 388 hsync = REG_READ(map->hsync); 389 vtot = REG_READ(map->vtotal); 390 vsync = REG_READ(map->vsync); 391 gma_power_end(dev); 392 } else { 393 htot = p->htotal; 394 hsync = p->hsync; 395 vtot = p->vtotal; 396 vsync = p->vsync; 397 } 398 399 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 400 if (!mode) 401 return NULL; 402 403 mode->clock = psb_intel_crtc_clock_get(dev, crtc); 404 mode->hdisplay = (htot & 0xffff) + 1; 405 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 406 mode->hsync_start = (hsync & 0xffff) + 1; 407 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 408 mode->vdisplay = (vtot & 0xffff) + 1; 409 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 410 mode->vsync_start = (vsync & 0xffff) + 1; 411 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 412 413 drm_mode_set_name(mode); 414 drm_mode_set_crtcinfo(mode, 0); 415 416 return mode; 417 } 418 419 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = { 420 .dpms = gma_crtc_dpms, 421 .mode_set = psb_intel_crtc_mode_set, 422 .mode_set_base = gma_pipe_set_base, 423 .prepare = gma_crtc_prepare, 424 .commit = gma_crtc_commit, 425 .disable = gma_crtc_disable, 426 }; 427 428 const struct drm_crtc_funcs psb_intel_crtc_funcs = { 429 .cursor_set = gma_crtc_cursor_set, 430 .cursor_move = gma_crtc_cursor_move, 431 .gamma_set = gma_crtc_gamma_set, 432 .set_config = gma_crtc_set_config, 433 .destroy = gma_crtc_destroy, 434 }; 435 436 const struct gma_clock_funcs psb_clock_funcs = { 437 .clock = psb_intel_clock, 438 .limit = psb_intel_limit, 439 .pll_is_valid = gma_pll_is_valid, 440 }; 441 442 /* 443 * Set the default value of cursor control and base register 444 * to zero. This is a workaround for h/w defect on Oaktrail 445 */ 446 static void psb_intel_cursor_init(struct drm_device *dev, 447 struct gma_crtc *gma_crtc) 448 { 449 struct drm_psb_private *dev_priv = dev->dev_private; 450 u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR }; 451 u32 base[3] = { CURABASE, CURBBASE, CURCBASE }; 452 struct gtt_range *cursor_gt; 453 454 if (dev_priv->ops->cursor_needs_phys) { 455 /* Allocate 4 pages of stolen mem for a hardware cursor. That 456 * is enough for the 64 x 64 ARGB cursors we support. 457 */ 458 cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1, 459 PAGE_SIZE); 460 if (!cursor_gt) { 461 gma_crtc->cursor_gt = NULL; 462 goto out; 463 } 464 gma_crtc->cursor_gt = cursor_gt; 465 gma_crtc->cursor_addr = dev_priv->stolen_base + 466 cursor_gt->offset; 467 } else { 468 gma_crtc->cursor_gt = NULL; 469 } 470 471 out: 472 REG_WRITE(control[gma_crtc->pipe], 0); 473 REG_WRITE(base[gma_crtc->pipe], 0); 474 } 475 476 void psb_intel_crtc_init(struct drm_device *dev, int pipe, 477 struct psb_intel_mode_device *mode_dev) 478 { 479 struct drm_psb_private *dev_priv = dev->dev_private; 480 struct gma_crtc *gma_crtc; 481 int i; 482 483 /* We allocate a extra array of drm_connector pointers 484 * for fbdev after the crtc */ 485 gma_crtc = kzalloc(sizeof(struct gma_crtc) + 486 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), 487 GFP_KERNEL); 488 if (gma_crtc == NULL) 489 return; 490 491 gma_crtc->crtc_state = 492 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL); 493 if (!gma_crtc->crtc_state) { 494 dev_err(dev->dev, "Crtc state error: No memory\n"); 495 kfree(gma_crtc); 496 return; 497 } 498 499 /* Set the CRTC operations from the chip specific data */ 500 drm_crtc_init(dev, &gma_crtc->base, dev_priv->ops->crtc_funcs); 501 502 /* Set the CRTC clock functions from chip specific data */ 503 gma_crtc->clock_funcs = dev_priv->ops->clock_funcs; 504 505 drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256); 506 gma_crtc->pipe = pipe; 507 gma_crtc->plane = pipe; 508 509 for (i = 0; i < 256; i++) 510 gma_crtc->lut_adj[i] = 0; 511 512 gma_crtc->mode_dev = mode_dev; 513 gma_crtc->cursor_addr = 0; 514 515 drm_crtc_helper_add(&gma_crtc->base, 516 dev_priv->ops->crtc_helper); 517 518 /* Setup the array of drm_connector pointer array */ 519 gma_crtc->mode_set.crtc = &gma_crtc->base; 520 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 521 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL); 522 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base; 523 dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base; 524 gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1); 525 gma_crtc->mode_set.num_connectors = 0; 526 psb_intel_cursor_init(dev, gma_crtc); 527 528 /* Set to true so that the pipe is forced off on initial config. */ 529 gma_crtc->active = true; 530 } 531 532 struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) 533 { 534 struct drm_crtc *crtc = NULL; 535 536 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 537 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 538 if (gma_crtc->pipe == pipe) 539 break; 540 } 541 return crtc; 542 } 543 544 int gma_connector_clones(struct drm_device *dev, int type_mask) 545 { 546 int index_mask = 0; 547 struct drm_connector *connector; 548 int entry = 0; 549 550 list_for_each_entry(connector, &dev->mode_config.connector_list, 551 head) { 552 struct gma_encoder *gma_encoder = gma_attached_encoder(connector); 553 if (type_mask & (1 << gma_encoder->type)) 554 index_mask |= (1 << entry); 555 entry++; 556 } 557 return index_mask; 558 } 559