1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright © 2006-2011 Intel Corporation
4  *
5  * Authors:
6  *	Eric Anholt <eric@anholt.net>
7  */
8 
9 #include <linux/delay.h>
10 #include <linux/i2c.h>
11 
12 #include <drm/drm_plane_helper.h>
13 
14 #include "framebuffer.h"
15 #include "gma_display.h"
16 #include "power.h"
17 #include "psb_drv.h"
18 #include "psb_intel_drv.h"
19 #include "psb_intel_reg.h"
20 
21 #define INTEL_LIMIT_I9XX_SDVO_DAC   0
22 #define INTEL_LIMIT_I9XX_LVDS	    1
23 
24 static const struct gma_limit_t psb_intel_limits[] = {
25 	{			/* INTEL_LIMIT_I9XX_SDVO_DAC */
26 	 .dot = {.min = 20000, .max = 400000},
27 	 .vco = {.min = 1400000, .max = 2800000},
28 	 .n = {.min = 1, .max = 6},
29 	 .m = {.min = 70, .max = 120},
30 	 .m1 = {.min = 8, .max = 18},
31 	 .m2 = {.min = 3, .max = 7},
32 	 .p = {.min = 5, .max = 80},
33 	 .p1 = {.min = 1, .max = 8},
34 	 .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5},
35 	 .find_pll = gma_find_best_pll,
36 	 },
37 	{			/* INTEL_LIMIT_I9XX_LVDS */
38 	 .dot = {.min = 20000, .max = 400000},
39 	 .vco = {.min = 1400000, .max = 2800000},
40 	 .n = {.min = 1, .max = 6},
41 	 .m = {.min = 70, .max = 120},
42 	 .m1 = {.min = 8, .max = 18},
43 	 .m2 = {.min = 3, .max = 7},
44 	 .p = {.min = 7, .max = 98},
45 	 .p1 = {.min = 1, .max = 8},
46 	 /* The single-channel range is 25-112Mhz, and dual-channel
47 	  * is 80-224Mhz.  Prefer single channel as much as possible.
48 	  */
49 	 .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7},
50 	 .find_pll = gma_find_best_pll,
51 	 },
52 };
53 
54 static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc,
55 						 int refclk)
56 {
57 	const struct gma_limit_t *limit;
58 
59 	if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
60 		limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS];
61 	else
62 		limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
63 	return limit;
64 }
65 
66 static void psb_intel_clock(int refclk, struct gma_clock_t *clock)
67 {
68 	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
69 	clock->p = clock->p1 * clock->p2;
70 	clock->vco = refclk * clock->m / (clock->n + 2);
71 	clock->dot = clock->vco / clock->p;
72 }
73 
74 /**
75  * Return the pipe currently connected to the panel fitter,
76  * or -1 if the panel fitter is not present or not in use
77  */
78 static int psb_intel_panel_fitter_pipe(struct drm_device *dev)
79 {
80 	u32 pfit_control;
81 
82 	pfit_control = REG_READ(PFIT_CONTROL);
83 
84 	/* See if the panel fitter is in use */
85 	if ((pfit_control & PFIT_ENABLE) == 0)
86 		return -1;
87 	/* Must be on PIPE 1 for PSB */
88 	return 1;
89 }
90 
91 static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
92 			       struct drm_display_mode *mode,
93 			       struct drm_display_mode *adjusted_mode,
94 			       int x, int y,
95 			       struct drm_framebuffer *old_fb)
96 {
97 	struct drm_device *dev = crtc->dev;
98 	struct drm_psb_private *dev_priv = dev->dev_private;
99 	struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
100 	const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
101 	int pipe = gma_crtc->pipe;
102 	const struct psb_offset *map = &dev_priv->regmap[pipe];
103 	int refclk;
104 	struct gma_clock_t clock;
105 	u32 dpll = 0, fp = 0, dspcntr, pipeconf;
106 	bool ok, is_sdvo = false;
107 	bool is_lvds = false, is_tv = false;
108 	struct drm_mode_config *mode_config = &dev->mode_config;
109 	struct drm_connector *connector;
110 	const struct gma_limit_t *limit;
111 
112 	/* No scan out no play */
113 	if (crtc->primary->fb == NULL) {
114 		crtc_funcs->mode_set_base(crtc, x, y, old_fb);
115 		return 0;
116 	}
117 
118 	list_for_each_entry(connector, &mode_config->connector_list, head) {
119 		struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
120 
121 		if (!connector->encoder
122 		    || connector->encoder->crtc != crtc)
123 			continue;
124 
125 		switch (gma_encoder->type) {
126 		case INTEL_OUTPUT_LVDS:
127 			is_lvds = true;
128 			break;
129 		case INTEL_OUTPUT_SDVO:
130 			is_sdvo = true;
131 			break;
132 		case INTEL_OUTPUT_TVOUT:
133 			is_tv = true;
134 			break;
135 		}
136 	}
137 
138 	refclk = 96000;
139 
140 	limit = gma_crtc->clock_funcs->limit(crtc, refclk);
141 
142 	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
143 				 &clock);
144 	if (!ok) {
145 		DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
146 			  adjusted_mode->clock, clock.dot);
147 		return 0;
148 	}
149 
150 	fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
151 
152 	dpll = DPLL_VGA_MODE_DIS;
153 	if (is_lvds) {
154 		dpll |= DPLLB_MODE_LVDS;
155 		dpll |= DPLL_DVO_HIGH_SPEED;
156 	} else
157 		dpll |= DPLLB_MODE_DAC_SERIAL;
158 	if (is_sdvo) {
159 		int sdvo_pixel_multiply =
160 			    adjusted_mode->clock / mode->clock;
161 		dpll |= DPLL_DVO_HIGH_SPEED;
162 		dpll |=
163 		    (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
164 	}
165 
166 	/* compute bitmask from p1 value */
167 	dpll |= (1 << (clock.p1 - 1)) << 16;
168 	switch (clock.p2) {
169 	case 5:
170 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
171 		break;
172 	case 7:
173 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
174 		break;
175 	case 10:
176 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
177 		break;
178 	case 14:
179 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
180 		break;
181 	}
182 
183 	if (is_tv) {
184 		/* XXX: just matching BIOS for now */
185 /*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
186 		dpll |= 3;
187 	}
188 	dpll |= PLL_REF_INPUT_DREFCLK;
189 
190 	/* setup pipeconf */
191 	pipeconf = REG_READ(map->conf);
192 
193 	/* Set up the display plane register */
194 	dspcntr = DISPPLANE_GAMMA_ENABLE;
195 
196 	if (pipe == 0)
197 		dspcntr |= DISPPLANE_SEL_PIPE_A;
198 	else
199 		dspcntr |= DISPPLANE_SEL_PIPE_B;
200 
201 	dspcntr |= DISPLAY_PLANE_ENABLE;
202 	pipeconf |= PIPEACONF_ENABLE;
203 	dpll |= DPLL_VCO_ENABLE;
204 
205 
206 	/* Disable the panel fitter if it was on our pipe */
207 	if (psb_intel_panel_fitter_pipe(dev) == pipe)
208 		REG_WRITE(PFIT_CONTROL, 0);
209 
210 	drm_mode_debug_printmodeline(mode);
211 
212 	if (dpll & DPLL_VCO_ENABLE) {
213 		REG_WRITE(map->fp0, fp);
214 		REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
215 		REG_READ(map->dpll);
216 		udelay(150);
217 	}
218 
219 	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
220 	 * This is an exception to the general rule that mode_set doesn't turn
221 	 * things on.
222 	 */
223 	if (is_lvds) {
224 		u32 lvds = REG_READ(LVDS);
225 
226 		lvds &= ~LVDS_PIPEB_SELECT;
227 		if (pipe == 1)
228 			lvds |= LVDS_PIPEB_SELECT;
229 
230 		lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
231 		/* Set the B0-B3 data pairs corresponding to
232 		 * whether we're going to
233 		 * set the DPLLs for dual-channel mode or not.
234 		 */
235 		lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
236 		if (clock.p2 == 7)
237 			lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
238 
239 		/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
240 		 * appropriately here, but we need to look more
241 		 * thoroughly into how panels behave in the two modes.
242 		 */
243 
244 		REG_WRITE(LVDS, lvds);
245 		REG_READ(LVDS);
246 	}
247 
248 	REG_WRITE(map->fp0, fp);
249 	REG_WRITE(map->dpll, dpll);
250 	REG_READ(map->dpll);
251 	/* Wait for the clocks to stabilize. */
252 	udelay(150);
253 
254 	/* write it again -- the BIOS does, after all */
255 	REG_WRITE(map->dpll, dpll);
256 
257 	REG_READ(map->dpll);
258 	/* Wait for the clocks to stabilize. */
259 	udelay(150);
260 
261 	REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
262 		  ((adjusted_mode->crtc_htotal - 1) << 16));
263 	REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
264 		  ((adjusted_mode->crtc_hblank_end - 1) << 16));
265 	REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
266 		  ((adjusted_mode->crtc_hsync_end - 1) << 16));
267 	REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
268 		  ((adjusted_mode->crtc_vtotal - 1) << 16));
269 	REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
270 		  ((adjusted_mode->crtc_vblank_end - 1) << 16));
271 	REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
272 		  ((adjusted_mode->crtc_vsync_end - 1) << 16));
273 	/* pipesrc and dspsize control the size that is scaled from,
274 	 * which should always be the user's requested size.
275 	 */
276 	REG_WRITE(map->size,
277 		  ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
278 	REG_WRITE(map->pos, 0);
279 	REG_WRITE(map->src,
280 		  ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
281 	REG_WRITE(map->conf, pipeconf);
282 	REG_READ(map->conf);
283 
284 	gma_wait_for_vblank(dev);
285 
286 	REG_WRITE(map->cntr, dspcntr);
287 
288 	/* Flush the plane changes */
289 	crtc_funcs->mode_set_base(crtc, x, y, old_fb);
290 
291 	gma_wait_for_vblank(dev);
292 
293 	return 0;
294 }
295 
296 /* Returns the clock of the currently programmed mode of the given pipe. */
297 static int psb_intel_crtc_clock_get(struct drm_device *dev,
298 				struct drm_crtc *crtc)
299 {
300 	struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
301 	struct drm_psb_private *dev_priv = dev->dev_private;
302 	int pipe = gma_crtc->pipe;
303 	const struct psb_offset *map = &dev_priv->regmap[pipe];
304 	u32 dpll;
305 	u32 fp;
306 	struct gma_clock_t clock;
307 	bool is_lvds;
308 	struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
309 
310 	if (gma_power_begin(dev, false)) {
311 		dpll = REG_READ(map->dpll);
312 		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
313 			fp = REG_READ(map->fp0);
314 		else
315 			fp = REG_READ(map->fp1);
316 		is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
317 		gma_power_end(dev);
318 	} else {
319 		dpll = p->dpll;
320 
321 		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
322 			fp = p->fp0;
323 		else
324 		        fp = p->fp1;
325 
326 		is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS &
327 								LVDS_PORT_EN);
328 	}
329 
330 	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
331 	clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
332 	clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
333 
334 	if (is_lvds) {
335 		clock.p1 =
336 		    ffs((dpll &
337 			 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
338 			DPLL_FPA01_P1_POST_DIV_SHIFT);
339 		clock.p2 = 14;
340 
341 		if ((dpll & PLL_REF_INPUT_MASK) ==
342 		    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
343 			/* XXX: might not be 66MHz */
344 			psb_intel_clock(66000, &clock);
345 		} else
346 			psb_intel_clock(48000, &clock);
347 	} else {
348 		if (dpll & PLL_P1_DIVIDE_BY_TWO)
349 			clock.p1 = 2;
350 		else {
351 			clock.p1 =
352 			    ((dpll &
353 			      DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
354 			     DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
355 		}
356 		if (dpll & PLL_P2_DIVIDE_BY_4)
357 			clock.p2 = 4;
358 		else
359 			clock.p2 = 2;
360 
361 		psb_intel_clock(48000, &clock);
362 	}
363 
364 	/* XXX: It would be nice to validate the clocks, but we can't reuse
365 	 * i830PllIsValid() because it relies on the xf86_config connector
366 	 * configuration being accurate, which it isn't necessarily.
367 	 */
368 
369 	return clock.dot;
370 }
371 
372 /** Returns the currently programmed mode of the given pipe. */
373 struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
374 					     struct drm_crtc *crtc)
375 {
376 	struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
377 	int pipe = gma_crtc->pipe;
378 	struct drm_display_mode *mode;
379 	int htot;
380 	int hsync;
381 	int vtot;
382 	int vsync;
383 	struct drm_psb_private *dev_priv = dev->dev_private;
384 	struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
385 	const struct psb_offset *map = &dev_priv->regmap[pipe];
386 
387 	if (gma_power_begin(dev, false)) {
388 		htot = REG_READ(map->htotal);
389 		hsync = REG_READ(map->hsync);
390 		vtot = REG_READ(map->vtotal);
391 		vsync = REG_READ(map->vsync);
392 		gma_power_end(dev);
393 	} else {
394 		htot = p->htotal;
395 		hsync = p->hsync;
396 		vtot = p->vtotal;
397 		vsync = p->vsync;
398 	}
399 
400 	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
401 	if (!mode)
402 		return NULL;
403 
404 	mode->clock = psb_intel_crtc_clock_get(dev, crtc);
405 	mode->hdisplay = (htot & 0xffff) + 1;
406 	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
407 	mode->hsync_start = (hsync & 0xffff) + 1;
408 	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
409 	mode->vdisplay = (vtot & 0xffff) + 1;
410 	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
411 	mode->vsync_start = (vsync & 0xffff) + 1;
412 	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
413 
414 	drm_mode_set_name(mode);
415 	drm_mode_set_crtcinfo(mode, 0);
416 
417 	return mode;
418 }
419 
420 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
421 	.dpms = gma_crtc_dpms,
422 	.mode_set = psb_intel_crtc_mode_set,
423 	.mode_set_base = gma_pipe_set_base,
424 	.prepare = gma_crtc_prepare,
425 	.commit = gma_crtc_commit,
426 	.disable = gma_crtc_disable,
427 };
428 
429 const struct drm_crtc_funcs psb_intel_crtc_funcs = {
430 	.cursor_set = gma_crtc_cursor_set,
431 	.cursor_move = gma_crtc_cursor_move,
432 	.gamma_set = gma_crtc_gamma_set,
433 	.set_config = gma_crtc_set_config,
434 	.destroy = gma_crtc_destroy,
435 	.page_flip = gma_crtc_page_flip,
436 	.enable_vblank = psb_enable_vblank,
437 	.disable_vblank = psb_disable_vblank,
438 	.get_vblank_counter = psb_get_vblank_counter,
439 };
440 
441 const struct gma_clock_funcs psb_clock_funcs = {
442 	.clock = psb_intel_clock,
443 	.limit = psb_intel_limit,
444 	.pll_is_valid = gma_pll_is_valid,
445 };
446 
447 /*
448  * Set the default value of cursor control and base register
449  * to zero. This is a workaround for h/w defect on Oaktrail
450  */
451 static void psb_intel_cursor_init(struct drm_device *dev,
452 				  struct gma_crtc *gma_crtc)
453 {
454 	struct drm_psb_private *dev_priv = dev->dev_private;
455 	u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
456 	u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
457 	struct gtt_range *cursor_gt;
458 
459 	if (dev_priv->ops->cursor_needs_phys) {
460 		/* Allocate 4 pages of stolen mem for a hardware cursor. That
461 		 * is enough for the 64 x 64 ARGB cursors we support.
462 		 */
463 		cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1,
464 						PAGE_SIZE);
465 		if (!cursor_gt) {
466 			gma_crtc->cursor_gt = NULL;
467 			goto out;
468 		}
469 		gma_crtc->cursor_gt = cursor_gt;
470 		gma_crtc->cursor_addr = dev_priv->stolen_base +
471 							cursor_gt->offset;
472 	} else {
473 		gma_crtc->cursor_gt = NULL;
474 	}
475 
476 out:
477 	REG_WRITE(control[gma_crtc->pipe], 0);
478 	REG_WRITE(base[gma_crtc->pipe], 0);
479 }
480 
481 void psb_intel_crtc_init(struct drm_device *dev, int pipe,
482 		     struct psb_intel_mode_device *mode_dev)
483 {
484 	struct drm_psb_private *dev_priv = dev->dev_private;
485 	struct gma_crtc *gma_crtc;
486 	int i;
487 
488 	/* We allocate a extra array of drm_connector pointers
489 	 * for fbdev after the crtc */
490 	gma_crtc = kzalloc(sizeof(struct gma_crtc) +
491 			(INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
492 			GFP_KERNEL);
493 	if (gma_crtc == NULL)
494 		return;
495 
496 	gma_crtc->crtc_state =
497 		kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL);
498 	if (!gma_crtc->crtc_state) {
499 		dev_err(dev->dev, "Crtc state error: No memory\n");
500 		kfree(gma_crtc);
501 		return;
502 	}
503 
504 	/* Set the CRTC operations from the chip specific data */
505 	drm_crtc_init(dev, &gma_crtc->base, dev_priv->ops->crtc_funcs);
506 
507 	/* Set the CRTC clock functions from chip specific data */
508 	gma_crtc->clock_funcs = dev_priv->ops->clock_funcs;
509 
510 	drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256);
511 	gma_crtc->pipe = pipe;
512 	gma_crtc->plane = pipe;
513 
514 	for (i = 0; i < 256; i++)
515 		gma_crtc->lut_adj[i] = 0;
516 
517 	gma_crtc->mode_dev = mode_dev;
518 	gma_crtc->cursor_addr = 0;
519 
520 	drm_crtc_helper_add(&gma_crtc->base,
521 						dev_priv->ops->crtc_helper);
522 
523 	/* Setup the array of drm_connector pointer array */
524 	gma_crtc->mode_set.crtc = &gma_crtc->base;
525 	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
526 	       dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL);
527 	dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base;
528 	dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base;
529 	gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1);
530 	gma_crtc->mode_set.num_connectors = 0;
531 	psb_intel_cursor_init(dev, gma_crtc);
532 
533 	/* Set to true so that the pipe is forced off on initial config. */
534 	gma_crtc->active = true;
535 }
536 
537 struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
538 {
539 	struct drm_crtc *crtc = NULL;
540 
541 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
542 		struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
543 		if (gma_crtc->pipe == pipe)
544 			break;
545 	}
546 	return crtc;
547 }
548 
549 int gma_connector_clones(struct drm_device *dev, int type_mask)
550 {
551 	int index_mask = 0;
552 	struct drm_connector *connector;
553 	int entry = 0;
554 
555 	list_for_each_entry(connector, &dev->mode_config.connector_list,
556 			    head) {
557 		struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
558 		if (type_mask & (1 << gma_encoder->type))
559 			index_mask |= (1 << entry);
560 		entry++;
561 	}
562 	return index_mask;
563 }
564